APW7057KC-TU

APW7057 High Power Step-Down Synchronous DC/DC Controller Features • Operates from +5V Input • 0.8V Internal Reference Voltage - ±1.5% Accuracy Over Line, Load and Temp. General Description The APW7057 is a 300kHz constant frequency voltage mode synchronous switching controller that drives external N-channel MOSFETs. When the input supply drops close to output, the upper MOSFET remains on, achieving 100% duty cycle. Internal loop compensation is optimized for fast transient response, eliminating external compensation network. The precision 0.8V reference makes this part suitable for a wide variety of low voltage applications. Soft start is internally set to 2ms, limiting the input in-rush current and preventing the output from overshoot during powering up. The APW7057 has over current and short circuit protections. Over current protection is achieved by monitoring the voltage drop across the high side MOSFET, eliminating the need for a current sensing resistor and short circuit condition is detected through the FB pin. If either fault conditions occur, the APW7057 would initiate the soft start cycle. After three cycles and if the fault condition persists, the controller will be shut down. To restart the controller, either recycle the VCC supply or momentarily pull the OSCSET pin below 1.25V. The APW7057 can be shutdown by pulling the OCSET pin below 1.25V. In shutdown, both gate drive signals will be low. The controller is available in a small SOP8 package. • 0.8V to VCC Output Range • Full Duty Cycle Range - 0% to 100% • Internal Loop Compensation • Internal Soft Start - Typical 2ms • Programmable Over-Current Protection - Lossless Sensing Using MOSFET RDS (ON) • • • • Under-Voltage Protection Drives External N-Channel MOSFETs Shutdown Control Small SOP-8 Package Applications • • • • • • • Motherboard Graphics Cards Cable or DSL Modems, Set Top Boxes DSP Supplies Memory Supplies 5V Input DC-DC Regulators Distributed Power Supplies Pinouts BOOT UGATE GND LGATE 1 2 3 4 8 7 6 5 PHASE OCSET FB VCC SOP-8 (Top View ) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 1 www.anpec.com.tw APW7057 Ordering and Marking Information Package Code APW 7057 K : SOP-8 Operating Junction Tem p. Range Handling Code Tem p. Range Package Code C : 0 to 70 °C Handling Code TU : Tube TR : Tape & Reel APW 7057 K : APW 7057 XXXXX XXXXX - Date Code Block Diagram VCC BOOT UnderVoltage Lockout Shutdown OCSET IOCSET 40uA OC Com parator Soft-Start and Fault Logic OCP UVLO PHASE UGATE 0.5V UVP Soft-Start Inhibit Gate PW M Control V CC FB VR E F 0.8V - COMP + Error Am plifier + - LGATE FO S C 300kHz Oscillator GND . E C K H / Figure 1. C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 2 www.anpec.com.tw APW7057 Typical Application R3 C3 1uF 5 2.2 VIN D1 1N4148 C1 1uF + +5V C2 1000uF x2 R4 8.2k C7 470pF 7 OCSET VCC BOOT 1 Q3 U G ATE 2 C4 0.1uF Q1 L1 3.3uH VO UT +2.5V/10A C5 1000uF x2 Shutdown 8 P H AS E 6 U1 APW 7057 LG ATE FB GND 3 + 4 Q2 R1 5.1k R2 2.4k C6 0.1uF Q1: APM2014N UC Q2: APM2014N UC Q3: APM2300A AC C2: 1000uF/10V, ESR = 25m Ω C5: 1000uF/6.3V, ESR = 25m Ω .ECKH/Figure 2. Absolute Maximum Ratings Symbol V CC V BOOT Parameter VCC Supply Voltage (VCC to GND) BOOT Supply Voltage (BOOT to GND) PHASE, OCSET to GND Input Voltage FB to GND Input Voltage Maxim um Junction Tem perature T STG T SDR V ESD Storage Tem perature Maxim um Soldering Tem perature, 10 Seconds Minim um ESD Rating Rating -0.3 ~ 7 -0.3 ~ 15 -0.3 ~ 12 -0.3 ~ V CC +0.3 125 -65 ~ 150 300 ±2 Unit V V V V o o o C C C kV Thermal Characteristics Symbol θJA Parameter Junction-to-Ambient Resistance in free air (SOP-8) 3 Value 160 Unit o C/W C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 www.anpec.com.tw APW7057 Recommended Operating Conditions Symbol V CC V OUT V IN TA TJ V CC Supply Voltage Output Voltage of the Switching Regulator (Note) Input Voltage of the Switching Regulator (Note) A mbient Temperature Junction Temperature Parameter Range 5 ± 5% 0.8 ~ V CC 3.3 ~ V CC 0 ~ 70 0 ~ 125 Unit V V V o o C C Note : Refer to the typical application circuit  Electrical Characteristics Unless otherwise specified, these specifications apply over VCC=5V, VBOOT=12V and TA= 0~70 oC. Typical values are at TA=25oC. Symbol Parameter Test Conditions APW7057 Min Typ Max Unit SUPPLY CURRENT IVCC IBOOT VCC Nominal Supply Current BOOT Nominal Supply Current Rising VCC Threshold Falling VCC Threshold OSCILLATOR FOSC Free Running Frequency Ramp Upper Threshold Ramp Lower Threshold ∆V OSC VREF Ramp Amplitude Reference Voltage Reference Voltage Accuracy ERROR AMPLIFIER DC Gain FP FZ First Pole Frequency First Zero Frequency UGATE Duty Range FB Input Current C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 4 UGATE and LGATE Open UGATE Open 2.1 2.1 mA mA Under Voltage Lockout(UVLO) 4.0 3.8 250 4.2 4.0 300 2.85 0.95 1.9 0.8 -1.5 +1.5 4.4 4.2 340 V V kHz V V VP-P V % REFERENCE VOLTAGE 75 10 1 0 100 0.1 dB Hz kHz % µA www.anpec.com.tw APW7057 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC=5V, VBOOT=12V and TA= 0~70 oC. Typical values are at TA=25oC. Symbol Parameter Test Conditions APW7057 Min Typ 0.6 7.3 0.6 1.8 50 VOCSET=4.5V FB falling 34 40 0.5 15 46 Max Unit PWM CONTROLLER GATE DRIVERS UGATE Source UGATE Sink LGATE Source LGATE Sink TD IOCSET UVFB Dead Time OCSET Sink Current FB Under-Voltage Level FB Under-Voltage Hysteresis SOFT-START AND SHUTDOWN TSS Soft-Start Interval Shutdown Threshold OCSET Shutdown Hysteresis VOCSET Falling 2 1.25 20 mS V mV PROTECTION µA V mV VUAGTE=1V VUGATE=1V VLGATE=1V VLGATE=1V A Ω A Ω nS Functional Pin Description BOOT (Pin 1) This pin provides the supply voltage to the high side MOSFET driver. A voltage no greater than 13V can be connected to this pin as a supply to the driver. For driving logic level N-channel MOSEFT, a bootstrap circuit can be use to create a suitable driver’s supply. UGATE (Pin 2) This pin provides gate drive for the high-side MOSFET. GND (Pin 3) Signal and power ground for the IC. All voltage levels are measured with respect to this pin. Tie this pin to the ground plane through the lowest impedance connection available. C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 5 LGATE (Pin 4) This pin provides the gate drive signal for the low side MOSFET. VCC (Pin 5) This is the main bias supply for the controller and its low side MOSFET driver. Must be closely decoupled to GND (Pin 3). DO NOT apply a voltage greater than 5.5V to this pin. FB (Pin 6) This pin is the inverting input of the error amplifier and it receives the feedback voltage from an exter- www.anpec.com.tw APW7057 Functional Pin Description nal resistive divider across the output (VOUT). The output voltage is determined by: VOUT = 0.8V(1+ ROUT ) RGND the over current limit. An internally generated 40uA current source will flow through this resistor, creating a voltage drop. This voltage will be compared with the voltage across the high side MOSFET. The threshold of the over current limit is therefore given where ROUT is the resistor connected between VOUT and FB while RGND is the resistor connected from FB to GND. OCSET (Pin 7) This pin serves two functions: as a shutdown control and for setting the over current limit threshold. Pulling this pin below 1.25V shuts the controller down, forcing the UGATE and LGATE signals to be at 0V. A soft start cycle will be initiated upon the release of this pin. A resistor (Rocset) connected between this pin and the drain of the high side MOSFET will determine PHASE (Pin 8) This pin is connected to the source of the high-side MOSFET and is used to monitor the voltage drop across the high-side MOSFET for over-current protection. by: IOI = 40uA x ROCSET RDS(ON) An over current condition will cycle the soft start function. After three consecutive cycles and if the fault condition persists, the controller will be shut down. To restart the controller, either recycle the VCC supply or momentarily pull the OSCSET pin below 1.25V. Typical Characteristics Reference Voltage vs. Junction Temperature 0.812 Switching Frequency vs. Junction Temperature 350 Switching Frequency, FOSC (kHz) 340 330 320 310 300 290 280 270 260 250 -50 -25 0 25 50 75 100 125 150 Reference Voltage, VREF (V) 0.808 0.804 0.800 0.796 0.792 0.788 -50 -25 0 25 50 75 100 125 150 Junction Temperature (oC) C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 6 Junction Temperature (°C) www.anpec.com.tw APW7057 Typical Characteristics (Cont.) OCSET Current vs. Junction Temperature 46 45 44 43 42 41 40 39 38 37 36 35 34 -50 -25 0 25 50 75 100 125 150 OCSET Current , IOCSET (µA) Junction Temperature (oC) Operating Waveforms (Refer to the typical application circuit) 1. Load Transient Response : IOUT = 0A -> 10A -> 0A - IOUT slew rate = Ó 10A/µS IOUT = 0A -> 10A IOUT = 0A -> 10A -> 0A VOUT IOUT = 10A -> 0A VOUT VOUT VUGATE 10A VUGATE IOUT 0A IOUT IOUT Ch1 : VOUT, 100mV/Div, DC, Offset = 2.50V Ch2 : VUGATE, 10V/Div, DC Ax1 : IOUT, 5A/Div Time : 10µS/Div BW = 20MHz Ch1 : VOUT, 100mV/Div, DC, Offset = 2.50V Ax1 : IOUT, 5A/Div Time : 100µS/Div BW = 20MHz Ch1 : VOUT, 100mV/Div, DC, Offset = 2.50V Ch2 : VUGATE, 10V/Div, DC Ax1 : IOUT, 5A/Div Time : 10µS/Div BW = 20MHz C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 7 www.anpec.com.tw APW7057 Operating Waveforms 2. UGATE and LGATE UGATE Rising IOUT=10A VUGATE IOUT=10A VUGATE (Refer to the typical application circuit) UGATE Falling VLGATE VLGATE Ch1 : VUGATE, 2V/Div, DC Time : 125nS/Div Ch2 : VLGATE, 2V/Div, DC BW = 500MHz Ch1 : VUGATE, 2V/Div, DC Time : 125nS/Div Ch2 : VLGATE, 2V/Div, DC BW = 500MHz 3. Powering ON / OFF Soft-start at Powering ON VIN VIN Powering OFF VOUT VOUT Ch1 : VIN, 2V/Div, DC Time : 1mS/Div Ch2 : VOUT, 1V/Div, DC BW = 20MHz Ch1 : VIN, 2V/Div, DC Time : 5mS/Div Ch2 : VOUT, 1V/Div, DC BW = 20MHz 4. Short-Circuit Protection Under-Voltage (UVP) and Over-Current Protection (OCP) OCP VOUT Ch1 : VOUT, 1V/Div, DC Ax1 : IOUT, 10A/Div Time : 1mS/Div BW = 20MHz UVP OCP IOUT C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 8 www.anpec.com.tw APW7057 Application Information Component Selection Guidelines Output Capacitor Selection The selection of COUT is determined by the required effective series resistance (ESR) and voltage rating rather than the actual capacitance requirement. Therefore select high performance low ESR capacitors that are intended for switching regulator applications. In some applications, multiple capacitors have to be paralled to achieve the desired ESR value. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2 , where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor between 0.1uF to 1uF can be connected between VCC and ground pin. Inductor Selection The inductance of the inductor is determined by the output voltage requirement. The larger the inductance, the lower the inductor’s current ripple. This will translate into lower output ripple voltage. The ripple current and ripple voltage can be approximated by: IRIPPLE = VIN - VOUT Fs x L V x OUT VIN ∆VOUT = IRIPPLE x ESR where Fs is the switching frequency of the regulator. There is a tradeoff exists between the inductor’s ripple current and the regulator load transient response time A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current and vice versa. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some type of inductors, especially core that is make of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. MOSFET Selection The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement.The losses in the MOSFETs have two components: conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the following : PUPPER = Iout (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS PLOWER = Iout (1+ TC)(RDS(ON))(1-D) where IOUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tsw is the switching interval D is the duty cycle 2 2 . E C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 9 www.anpec.com.tw APW7057 Application Information Note that both MOSFETs have conduction losses while the upper MOSFET include an additional transition loss.The switching internal, tsw, is a function of the reverse transfer capacitance CRSS. Figure 3 illustrates the switching waveform internal of the MOSFET. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. single point grounding. Figure 4 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: • Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. There fore keep traces to these nodes as short as possible. Layout Considerations In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedances should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally combined using ground plane construction or • Decoupling capacitor CIN provides the bulk capaci tance and needs to be placed close to the IC since it will provide the MOSFET drivers transient current requirement. • The ground return of CIN must return to the combine COUT (-) terminal. • Capacitor CBOOT should be connected as close to the BOOT and PHASE pins as possible. V DS C HF CIN + VIN V oltage across drain and source of MO SFET VCC BOOT LGATE 5 1 4 APW7057 U 2 1UGATE PHASE 8 t sw Tim e Q1 Q2 C OUT + L1 VOUT Figure 3. Switching waveform across MOSFET Figure 4. Recommended Layout Diagram C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 10 www.anpec.com.tw APW7057 Packaging Information SOP-8 pin ( Reference JEDEC Registration MS-012) E H e1 D e2 A1 A 1 L 0.004max. Dim A A1 D E H L e1 e2 φ1 Mi ll im et er s Min . 1. 35 0. 10 4. 80 3. 80 5. 80 0. 40 0. 33 1. 27B S C 8° Max . 1. 75 0. 25 5. 00 4. 00 6. 20 1. 27 0. 51 Min. 0. 053 0. 004 0. 189 0. 150 0. 228 0. 016 0. 013 0.015X45 Inche s Max . 0. 069 0. 010 0. 197 0. 157 0. 244 0. 050 0. 020 0. 50B S C 8° C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 11 www.anpec.com.tw APW7057 Physical Specifications Terminal Material Lead Solderability Packaging Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. 2500 devices per reel (IR/Convection or VPR Reflow) Reflow Condition temperature Reference JEDEC Standard J-STD-020A APRIL 1999 Peak temperature 183°C Pre-heat temperature Time Classification Reflow Profiles Convection or IR/ Convection 3 °C/second max. 120 seconds max. 60 ~ 150 seconds 10 ~ 20 seconds 220 +5/-0 °C or 235 +5/-0 °C 6 °C /second max. 6 minutes max. VPR 10 °C /second max. Average ramp-up rate(183 °C to Peak) Preheat temperature 125 ± 25 °C) Temperature maintained above 183 °C Time within 5 °C of actual peak temperature Peak temperature range Ramp-down rate Time 25 °C to peak temperature 60 seconds 215~ 219 °C or 235 +5/-0 °C 10 °C /second max. Package Reflow Conditions pkg. thickness ≥ 2.5mm and all bags Convection 220 +5/-0 °C VPR 215-219 °C IR/Convection 220 +5/-0 °C pkg. thickness < 2.5mm and pkg. volume ≥ 350 mm pkg. thickness < 2.5mm and pkg. volume < Convection 235 +5/-0 °C VPR 235 +5/-0 °C IR/Convection 235 +5/-0 °C C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 12 www.anpec.com.tw APW7057 Reliability test program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C , 5 SEC 1000 Hrs Bias @ 125 °C 168 Hrs, 100 % RH , 121 °C -65°C ~ 150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms , Itr > 1 00mA Carrier Tape & Reel Dimension t E Po P P1 D F W Bo Ao D1 T2 Ko J C A B T1 Application A 330±1 F 5.5 ± 0.1 B 62 ± 1.5 C 12.75 + 0.1 5 J 2 + 0.5 T1 12.4 +0.2 P1 2.0 ± 0.1 T2 2± 0.2 Ao 6.4 ± 0.1 W 12 + 0.3 - 0.1 Bo 5.2± 0.1 P 8± 0.1 E 1.75± 0.1 SOP-8 D D1 Po 1.55±0.1 1.55+ 0.25 4.0 ± 0.1 Ko t 2.1± 0.1 0.3±0.013 (mm) C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 13 www.anpec.com.tw APW7057 Cover Tape Dimensions Application SOP- 8 Carrier Width 12 Cover Tape Width 9.3 Devices Per Reel 2500 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 C opyright  A NPEC Electronics Corp. Rev. A.3 - Oct., 2003 14 www.anpec.com.tw