APW7061

APW7061 Synchronous Buck PWM Controller Features • • Fast Transient Response - 0~85% Duty Ratio Excellent Output Voltage Regulation - 0.8V Internal Reference - ±1% Over Line Voltage and Temperature General Description The APW7061 is a voltage mode, synchronous PWM cont roller which drives dual N-c hannel MOSFETs . It integrates t he c ont rols, monitoring and protec tion funct ions into a single package, which provides one c ontrolled power output s wit h under-voltage and over-current protections. APW7061 provides excellent regulation for output load variation. An internal 0.8V temperature-compensated reference voltage is designed to meet the various low output voltage applications. A power-on-reset (POR) circuit limits the VCC minimum opearting s upply voltage to ass ure the c ontroller working well. Over current protec tion is achieved by monit oring t he volt age drop ac ros s the low s ide MOSFET, eliminating the need for a current sensing resistor and short circuit condition is detected through the FB pin. The over-current protection triggers the soft -start function until the fault events be removed, but Under-voltage protection will shutdown IC directly. Pull the COMP pin below 0.4V will shutdown t he controller, and both gate drive signals will be low. • • • • • • Internal Soft-Start - Typical 2mS Over Current Protection - Sense Low-side MOSFET’s RDS(ON) Under Voltage Lockout Small Converter Size - 250kHz Free-running Oscillator 8-lead SOIC Package Lead Free Available (RoHS Compliant) Applications • • • • • Graphic Cards Memory Power Supplies DSL or Cable MODEMs Set Top Boxes Low-Voltage Distributed Power Supplies Pinouts VCC FB COMP GND 1 2 3 4 8 7 6 5 LGATE BOOT UGATE PHASE ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 1 www.anpec.com.tw APW7061 Ordering and Marking Information APW7061 Lead Free Code Handling Code Temp. Range Package Code APW7061 K : APW7061 XXXXX Package Code K : SOP-8 Operating Junction Temp. Range C : 0 to 70 ° C Handling Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code No te : ANPEC lea d-fre e p ro ducts co ntain mo ld ing comp oun ds /di e attach m ate ri als and 100 % matte ti n p la te te rmin atio n fi nish ; wh ich are full y compl iant with Ro HS and compa tibl e wi th both SnPb an d le ad-free sold ieri ng op era tio ns. AN PEC le ad-free produ cts me et or exceed th e l ead -free req uireme nts of IPC /JEDEC J STD -02 0C fo r MSL classi ficati on at lea d-fre e p eak re flo w temp era ture. Block Diagram VCC GND Power-On Reset BOOT Soft Start Gate Control V CC IOCSET 250uA UGATE PHASE 50%VR E F U.V.P Comparator :2 PWM Comparator O.C.P Comparator VCC LGATE Error Amp V REF Triangle Wave FB COMP C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 2 www.anpec.com.tw APW7061 Application Circuit 12V L1 1uH R1 2R2 + C1 470uF 16V 25mR D1 1N4148 LGATE BOOT UGATE PHASE 8 7 6 5 8 7 6 5 4 C7 R4 620R C8 0.01uF 0.1uF L2 8 7 6 5 R6 0R 4 1 2 3 Q2 APM4220 2.2uH R5 100R D2 SR24 2A/40V R7 2.32KF 1% 1 2 3 2.5V Q1 APM4220 C2 4.7uF + C3 470uF 16V 25mR + C4 470uF 16V 25mR /SHDN C5 1uF 1 2 3 4 R2 20K C6 56pF U1 APW7061 VCC FB COMP GND R3 0R + C9 1000uF 6.3V 30mR + C10 1000uF 6.3V 30mR C11 4.7uF C12 0.1uF R8 1.07KF 1% Absolute Maximum Ratings Symbol VCC, LGATE Parameter VCC to GND, LGATE to GND Rating 30 30 30 0~150 -65 ~ 150 300 ±2 Unit V V V o o o VBOOT, UGATE BOOT to GND, UGATE to GND PHASE to GND Operating Junction Temperature T STG TSDR VESD Storage Temperature Soldering Temperature (10 Seconds) Minimum ESD Rating C C C KV Recommended Operating Conditions Symbol VCC VBOOT Supply Voltage Boot Voltage Parameter Min. 7 Nom. 12 Max. 19 26 Unit V V Thermal Characteristics Symbol θJA Parameter Junction to Ambient Resistance in free air (SOP-8) 3 Value 160 Unit o C/W C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 www.anpec.com.tw APW7061 Electrical Characteristics Unless otherswise specified, these specifications apply over VCC= 12V, VBOOT = 12V and TA = 0 ~ 70oC. Typlcal values are at TA = 25oC. Symbol SUPPLY CURRENT ICC IBOOT Parameter Test Conditions APW7061 Min Typ 2 2 7.0 6.6 7.2 6.8 2 50 3.0 1.3 1.7 0.80 -1 75 0 85 0.1 +1 7.4 7.0 280 M ax Unit VCC Nominal Supply BOOT Nominal Supply Rising VCC Threshold Falling VCC Threshold UGATE and LGATE Open UGATE Open mA mA V V kHz V V VP-P V % dB % uA mA 8 8 Ω mA Ω nS % uA POWER-ON-RESET OSCILLATOR FOSC Free Running Frequency Ramp Upper Threshold Ramp Lower Threshold ∆VOSC VREF Ramp Amplitude Reference Voltage Reference Voltage Tolerance ERROR AMPLIFIER DC Gain UGATE Duty Range FB Input Current GATE DRIVERS IUGATE R UGATE ILGATE RLGATE TD Upper Gate Source Upper Gate Sink Lower Gate Source Lower Gate Sink Dead Time FB Under Voltage Level O CSET source current SOFT START and SHUTDOWN TSS Internal Soft-Start Interval Shutdown Threshold Shutdown Hysteresis C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 4 VCC=12V 220 REFERENCE VBOOT=12V, V UGATE=6V IUGATE=0.3A VCC=12V, V LGATE =6V ILGATE =0.3A 650 550 800 4 700 4 30 PROTECTION FB Falling 50 250 2 COMP Falling 0.4 50 mS V mV www.anpec.com.tw APW7061 Functional Pin Description VCC (Pin 1) This pin provides a supply voltage to the device, When VCC is rising above the threshold 4.2V, the device is turned on, and convers ely, when V CC drops below the falling threshold, the device is turned off. A 1uF decoupling capacitor to GND is recommended. FB (Pin 2) FB pin is the inverting input of the error amplifier, and it receives the feedback voltage from an external resistive divider across the output (V OUT). The output voltage is determined by: COMP (Pin 3) This pin is the output of the error amplifier. Add an ex ternal resist or and capacitor net work to provide the loop c ompensation for the P WM c onverter (s ee Applicat ion Informat ion). Pull this pin below 0.4V will shutdown t he controller, forcing the UGATE and LGATE signals to be 0V. A soft st art c ycle will be init iated upon the release of this pin. PHASE (Pin 5) A resistor (ROCSET) is connected between this pin and the drain of the low-side MOSFET will determine the over current limit. A n int ernally generated 250uA current source will flow through this resistor, creating a voltage drop. This voltage will be compared with the voltage across the low-side MOSFET. The threshold of the over current limit is therefore given by : VOUT   R = 0.8V ×  1 + OUT   R GND    where ROUT is the resistor connected from VOUT to FB, and RGND is the resistor connected from FB to GND. When the FB voltage is under 50% VREF, it will cause the under voltage protection, and shutdown the device. Remove t he condit ion and restart the VCC voltage, will enable again the device. GND (Pin 4) Signal ground for the IC. UGATE (Pin 6) This pin provides gate drive for the high-side MOSFET. BOOT (Pin 7) This pin provides the supply voltage to the high side MOS FE T driver. For driving logic level N-channel MOSEFT, a boots trap circuit can be use to create a suitable driver’ supply. s LGATE (Pin 8) This pin provides the gate drive signal for the low side MOSFET. ILIMIT = 250 µ A × R OCSET R DS(ON) An over current condit ion will cy cle the soft s tart funct ion unt il the over current condition is removed. Because of the comparator delay time, so the on time of the low-side MOSFET must be longer than 800ns to have the over current protection work. C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 5 www.anpec.com.tw APW7061 Typical Characteristics Power Up Power Down VCC(5V/div) VCC(5V/div) VOUT(1V/div) VOUT(1V/div) Time (2ms/div) Time (5ms/div) Enable (COMP is left open) Shutdown(COMP is pulled to GND) COMP(1V/div) COMP(1V/div) VOUT(1V/div) VOUT(1V/div) Time (2ms/div) Time (5ms/div) C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 6 www.anpec.com.tw APW7061 Typical Characteristics (Cont.) UGATE Falling VCC=12V, VI N=12V UGATE Rising VCC=12V, VIN=12V LGATE(10V/div) LGATE(10V/div) PHASE(10V/div) PHASE(10V/div) UGATE(10V/div) UGATE(10V/div) Time (50ns/div) Time (50ns/div) Over Current Protection Under Voltage Protection VCC=12,VIN=12V VOUT=2.5V, L=2.2mH VCC=12V,VIN=12V, VOUT =2.5V, ROCSET=1kW RDS(ON)=16mW, L=2.2mH, IOUT =15A IL(10A/div) IL(10A/div) UGATE (20V/div) UGATE (20V/div) VOUT (1V/div) VOUT (1V/div) Time (10us/div) Time (2us/div) C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 7 www.anpec.com.tw APW7061 Typical Characteristics (Cont.) Supply Current vs. Supply Voltage 4 3.5 PWM Load Transient VCC=12V VIN=12V VOUT =3.3V C OUT=470mFx2 ESR=22.5mW L=1.5mH f=400kHz Supply Current (mA) 3 2.5 2 1.5 1 0.5 0 0 2 4 ICC ICC(SHDN) VOUT(100mV/div) IOUT1(5A/div) 6 8 10 12 Supply Voltage (V) Time (20us/div) UGATE Source Current vs. UGATE Voltage 1.4 UGATE Sink Current vs. UGATE Voltage 1.2 UGATE Source Current (A) 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 VBOOT=12V VBOOT=12V UGATE Sink Current (A) 8 10 12 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 UGATE Voltage (V) UGATE Voltage (V) C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 8 www.anpec.com.tw APW7061 Typical Characteristics (Cont.) LGATE Source Current vs. LGATE Voltage 1.4 1.2 VCC=12V LGATE Sink Current vs. LGATE Voltage 1.2 VCC=12V 1 LGATE Source Current (A) 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 LGATE Sink Current (A) 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 LGATE Voltage (V) LGATE Voltage (V) Sink Current vs. Comp Voltage 150 VCC=12V Source Current vs. Comp Voltage 150 VCC=12V 125 125 Source Current (µA) Sink Current (µA) 100 75 50 25 0 0 0.5 1 1.5 2 2.5 3 3.5 4 100 75 50 25 0 1 1.5 2 2.5 3 3.5 4 Comp Voltage (V) Comp Voltage (V) C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 9 www.anpec.com.tw APW7061 Typical Characteristics (Cont.) Reference Voltage vs. Junction Temperature 0.8 Reference Voltage (V) 0.798 0.796 0.794 0.792 0.79 -40 -20 0 20 40 60 80 100 120 Junction Temperature (°C) Application Information Component Selection Guidelines Output Capacitor Selection The s election of COU T is determined by the required effective series resist ance (ESR) and voltage rat ing rat her t han t he ac tual c apacit anc e requirement . Therefore select high performance low ESR capacitors that are intended for switching regulator applications. In some applications, multiple capacitors have to be paralled to achieve the desired ESR value. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufac turer. Input Capacitor Selection The input capacitor is chos en based on the volt age rat ing and the RMS c urrent rat ing. For reliable operation, select the capacitor voltage rating to be at C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 10 least 1.3 times higher than the maximum input voltage. The maximum RMS c urrent rating requirement is approximately IOUT/2 , where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are us ed, make s ure they are surge t est ed by t he manufact ures . If in doubt, c onsult t he c apac it ors manufac turer. For high frequency decoupling, a ceramic capacitor between 0.1uF to 1uF can be connected between VCC and ground pin. Inductor Selection The inductanc e of the inductor is determined by the output voltage requirement. The larger the inductance, the lower the inductor’ current ripple. This will translate s www.anpec.com.tw APW7061 Application Information (Cont.) Inductor Selection (Cont.) into lower output ripple voltage. The ripple current and ripple voltage can be approximated by: IRIPPLE = VIN - VOUT Fs x L x VOUT VIN FESR FLC The poles and zero of this transfer function are: = = 1 2 × π × L × COUT 1 2 × π × ESR × COUT ∆VOUT = IRIPPLE x ESR where Fs is the switching frequency of the regulator. There is a tradeoff exists between the inductor’ ripple s current and the regulator load transient response time A smaller inductor will give the regulator a faster load trans ient res ponse at the expens e of higher ripple current and vice versa. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the induct ance value has been chosen, s elect an inductor that is capable of carrying the required peak current without going into s aturation. In s ome ty pe of induc tors, es pec ially core that is make of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. Compensation The output LC filter introduces a double pole, which contributes wit h – 40dB/decade gain slope and 180 degrees phase shift in the control loop. A compensation network between COMP pin and ground should be added. The simplest loop compensation network is shown in Figure. 4. The out put LC filter consist s of the output induc tor and output capacitors. The transfer function of the LC filter is given by: GAINLC The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. PHASE L COUT ESR Output Figure 1. The Output LC Filter F LC -40dB/dec FESR Gain -20dB/dec Frequency Figure 2. The Output LC Filter Gain & Frequency The PWM modulator is shown in Figure. 3. The input is the output of the error amplifier and the output is the P HA SE node. The trans fer func tion of t he PW M modulator is given by: = 1 + s × ESR × COUT s × L × COUT + s × ESR + 1 2 GAINPWM = VIN ∆V OSC C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 11 www.anpec.com.tw APW7061 Application Information (Cont.) Compensation (Cont.) V IN Driver PWM Comparator V OSC Output of Error Amplifier Driver PHASE The c losed loop gain of the converter c an be written as: GAINLC x GAINPWM x R2 R1+ R2 x GAINAMP Figure 5 s hows t he converter gain and the following guidelines will help t o des ign the c ompens at ion network. 1.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) x FS > FO>FZ Use the following equation to calculate R3: Figure 3. The PWM Modulator The compens ation circuit is s hown in Figure 4. R3 and C1 introduce a zero and C2 introduces a pole to reduce the switc hing noise. The transfer function of error amplifier is given by: R3 = Where: ∆ VOSC VIN × F ESR R1 + R2 FO × × 2 R2 gm FLC gm = 900uA/V 2.Place the zero FZ before the LC filter double poles FLC: FZ = 0.75 x FLC Calculate the C1 by the equation:  1 1  // GAINAMP = gm× Zo = gm ×   R3 +  sC1  sC2   1   s +  R3 × C1   = gm × C1 + C2   s× s +  × C2 R3 × C1 × C2   The poles and zero of the compensation network are: 1 FP = C1× C2 2 × π × R3× C1+ C2 FZ C1 = 1 2 × π × R1× 0.75 × FLC 3. Set the pole at the half the switching frequency: FP = 0.5 x FS Calculate the C2 by the equation: C1 C2 = π × R3 × C1 × F S − 1 FZ=0.75FLC 20⋅log(gm⋅R3) = V OUT 1 2 × π × R3 × C1 FP=0.5FS R1 FB Error Amplifier COMP Compensation Gain Gain FLC 20 ⋅ log VIN ? VOSC FO FESR Converter Gain R2 V REF + R3 C2 C1 PWM & Filter Gain Frequency Figure 4. Compensation Network C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 12 Figure 5. Converter Gain & Frequency www.anpec.com.tw APW7061 Application Information (Cont.) MOSFET Selection The s election of the N-c hannel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (C RSS) and max imum out put c urrent requirement . The los ses in t he MOSFE Ts have two components: conduc tion loss and transition loss. For the upper and lower MOSFE T, the losses are approximately given by the following : PUPPER = Iout (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS 2 • Keep t he switching nodes (UGATE, LGATE and PHA SE) away from s ensit ive small signal nodes since these nodes are fast moving signals. Therefore keep traces to these nodes as short as possible. • The ground return of CIN must return to the combine COUT (-) terminal. • Capacitor CBOOT s hould be connected as close to the BOOT and PHASE pins as possible. VDS PLOWER = Iout (1+ TC)(RDS(ON))(1-D) 2 where IOUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tsw is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while the upper MOSFET include an additional transition loss. The switching internal, tsw, is a function of the reverse transfer capac it anc e CRSS. Figure 6 illustrat es t he switching waveform internal of the MOSFET. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET . VIN Voltage across drain and source of MOSFET t sw Time Figure 6. Switching waveform across MOSFET Layout Considerations In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, int erconnec ting impedanc es should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally combined using ground plane cons truction or single point grounding. Figure 8 illustrates the layout, wit h bold lines indic at ing high c urrent pat hs . Component s along the bold lines should be placed close together. Below is a checklist for your layout: Figure 7. Recommended Layout Diagram 13 www.anpec.com.tw PGND APW7061 11 C IN + LGATE 12 U 9 1 UGATE PHASE 8 C OUT Q1 Q2 L1 + L O A D VO U T C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 APW7061 Package Information SOP-8 pin ( Reference JEDEC Registration MS-012) E H e1 D e2 A1 A 1 L 0.004max. Dim A A1 D E H L e1 e2 φ1 Millimeters Min. 1.35 0.10 4.80 3.80 5.80 0.40 0.33 1.27BSC 8° Max. 1.75 0.25 5.00 4.00 6.20 1.27 0.51 Min. 0.053 0.004 0.189 0.150 0.228 0.016 0.013 0.015X45 Inches Max. 0.069 0.010 0.197 0.157 0.244 0.050 0.020 0.50BSC 8° C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 14 www.anpec.com.tw APW7061 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. (IR/Convection or VPR Reflow) Reflow Condition TP Ramp-up tp Critical Zone T L to T P TL Temperature tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25 C to Peak ° Time Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate 3°C/second max. 3° C/second max. (TL to T P) Preheat 100°C 150° C - Temperature Min (Tsmin) 150°C 200° C - Temperature Max (Tsmax) 60-120 seconds 60-180 seconds - Time (min to max) (ts) Time maintained above: 183°C 217° C - Temperature (TL) 60-150 seconds 60-150 seconds - Time (t L) Peak/Classificatioon Temperature (Tp) See table 1 See table 2 Time within 5° C of actual 10-30 seconds 20-40 seconds Peak Temperature (tp) Ramp-down Rate 6°C/second max. 6° C/second max. 6 minutes max. 8 minutes max. Time 25° C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. C opyright © A NPEC Electronics C orp. Rev. A.7 - Nov., 2005 15 www.anpec.com.tw APW7061 Classification Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures Package Thickness Volume mm3