APW7088

APW7088 Two-Phase Buck PWM Controller with Integrated MOSFET Drivers Features • Voltage-Mode Operation with Current Sharing - Adjustable Feedback Compensation - Fast Load Transient Response • • • • • • • • • • • • • • • • Operate with 8V~13.2VCC Supply Voltage Programmable 3-Bit DAC Reference -±1.5% System Accuracy Over Temperature Support Single- and Two-Phase Operations 5V Linear Regulator Output on 5VCC 8~12V Gate Drivers with Internal Bootstrap Diode Lossless Inductor DCR Current Sensing Fixed 300kHz Operating Frequency Per Phase Power-OK Indicator Output - Regulated 1.5V on POK Adjustable Over-Current Protection (OCP) Accurate Load Line (DROOP) Programming Adjustable Soft-Start Over-Voltage Protection (OVP) Under-Voltage Protection (UVP) Over-Temperature Protection (OTP) QFN4x4 24-Lead Package (QFN4x4-24) Lead Free and Green Devices Available (RoHS Compliant) General Description The APW7088, two-phase PWM control IC, provides a precision voltage regulation system for advanced graphic microprocessors in graphics card applications. The integration of power MOSFET drivers into the controller IC reduces the number of external parts for a cost and space saving power management solution. The APW7088 uses a voltage-mode PWM architecture, operating with fixed-frequency, to provides excellent load transient response. The device uses the voltage across the DCRs of the inductors for current sensing. Load line voltage positioning (DROOP), channel-current balance and over-current protection are accomplished through continuous inductor DCR current sensing. The MODE pin programs single- or two- phase operation. When IC operates in two-phase mode normally, it can transfer two-phase mode to single phase mode at liberty. Nevertheless, once operates in single-phase mode, the operation mode is latched. It is required to toggle SS or 5VCC pin to reset the IC. Such feature of the MODE pin makes the APW7088 ideally suitable for dual power input applications, such as PCIE interfaced graphic cards. This control IC‘ protection features include a set of sos phisticated over temperature, over-voltage, under-voltage, and over-current protections. Over-voltage results in the converter turning the lower MOSFETs on to clamp the rising output voltage and protects the microprocessor. The over-current protection level is set through external resistors. The device also provides a power-on-reset function and a programmable soft-start to prevent wrong operation and limit the input surge current during power-on or start-up. VOUT Simplified Application Circuit VIN1 VID0 VID1 VID2 APW7088 POK The APW7088 is available in a QFN4x4-24 package. VIN2 COMP FB Applications • • • Graphics Card GPU Core Power Supply Motherboard Chipset or DDR SDRAM Core Power Supply On-Board High Power PWM Converter with Output Current up to 60A ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright © ANPEC Electronics Corp. Rev. A.4 - Feb., 2009 1 www.anpec.com.tw APW7088 Ordering and Marking Information APW7088 Assembly Material Handling Code Temperature Range Package Code Package Code QA : QFN4x4-24 Operating Ambient Temperature Range E : -20 to 70 °C Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device XXXXX - Date Code APW7088 QA : APW7088 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration PHASE1 LGATE1 PHASE2 18 UGATE2 17 BOOT2 25 PGND 16 POK 15 VID1 14 SS 13 FB 7 CSN1 8 CSN2 9 CSP2 10 11 12 DROOP COMP VID0 VCC VID2 LGATE2 24 23 22 21 20 19 UGATE1 1 BOOT1 2 5VCC 3 AGND 4 MODE 5 CSP1 6 4x4 QFN-24L Top View Absolute Maximum Ratings Symbol VCC VBOOT1/2 VCC Supply Voltage (VCC to AGND) (Note 1) Rating -0.3 ~ 15 -0.3 ~ 15 200ns pulse width -5 ~ VBOOT1/2+5 -0.3 ~ VBOOT1/2+0.3 -5 ~ VCC+5 -0.3 ~ VCC+0.3 -10 ~ 30 -2 ~ 15 -0.3 ~ 42 -0.3 ~ 30 Unit V V V Parameter BOOT1/2 Voltage (BOOT1/2 to PHASE1/2) UGATE1/2 Voltage (UGATE1/2 to PHASE1/2) LGATE1/2 Voltage (LGATE1/2 to PGND) 200ns pulse width PHASE1/2 Voltage (PHASE1/2 to PGND) 200ns pulse width BOOT1/2 to AGND Voltage 200ns pulse width V V V C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 2 www.anpec.com.tw APW7088 Absolute Maximum Ratings (Cont.) Symbol V5VCC VMODE Parameter 5VCC Supply Voltage (5VCC to AGND, V5VCC < VCC +0.3V) MODE to AGND Voltage Input Voltage (SS, FB, COMP, DROOP, CSP1/2, CSN1/2, VID0/1/2 to AGND) PGND to AGND Voltage PDMAX TSTG TSDR Maximum Power Dissipation Maximum Junction Temperature Storage Temperature Range Maximum Soldering Temperature, 10 Seconds (Note 1) Rating -0.3 ~ 7 -0.3 ~ 7 -0.3 ~ V5VCC +0.3 -0.3 ~ +0.3 Limited Internally 150 -65 ~ 150 260 Unit V V V V W o o o C C C Note 1: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Thermal Characteristics Symbol θJA θJC Parameter Junction-to-Ambient Resistance (Note 2) Junction-to-Case Resistance (Note 3) Rating 45 7 Unit °C/W Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of QFN4x4-24 is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the QFN4x4-24 package. Recommended Operating Conditions (Note 4) Symbol VCC V5VCC VOUT VIN1 VIN2 IOUT TA TJ CVCC C5VCC VCC Supply Voltage 5VCC Supply Voltage (V5VCC < VCC +0.3V) Converter Output Voltage PWM 1 Converter Input Voltage PWM 2 Converter Input Voltage Converter Output Current Ambient Temperature Junction Temperature Linear Regulator Output Capacitor 5VCC Linear Regulator Output Capacitor Parameter Range 8 ~ 13.2 5 ± 5% 0.85 ~ 2.5 3.1 ~ 13.2 3.1 ~ 13.2 ~ 60 -20 ~ 70 -20 ~ 125 0.8 ~ 15 0.8 ~ 15 Unit V V V V V A o o C C µF µF Note 4 : Refer to the typical application circuits. Electrical Characteristics Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70°C, unless otherwise specified. Typical values are at TA=25°C. The V5VCC is supplied by the internal regulator. Symbol SUPPLY CURRENT ICC ISD VCC Nominal Supply Current VCC Shutdown Supply Current UGATEx and LGATEx Open, FB forced above regulation point SS=GND 5 5 10 mA mA Parameter Test Conditions APW7088 Min. Typ. Max. Unit C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 3 www.anpec.com.tw APW7088 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70°C, unless otherwise specified. Typical values are at TA=25°C. The V5VCC is supplied by the internal regulator. Symbol Parameter Test Conditions APW7088 Min. Typ. Max. Unit POWER-ON-RESET (POR) AND OPERATION PHASE SELECTION V5VCC_THR 5VCC Rising Threshold Voltage 5VCC POR Hysteresis MODE Rising Threshold Voltage IMODE MODE Pin Input Current VMODE Rising 4.2 0.4 0.77 -100 4.5 0.58 0.8 4.8 0.76 0.83 +100 V V V nA 5VCC LINEAR REGULATOR VREG_5VCC Output Voltage Line Regulation Load Regulation Current-Limit REFERENCE VOLTAGE Accuracy IFB FB Pin Input Current VID0/1/2 Logic High Threshold VID0/1/2 Logic Low Threshold VID0/1/2 Pull-high Current VPOK POK Output Voltage POK Accuracy POK Current-Limit POK Pull-Low Resistance ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate Upper Clamp Voltage Lower Clamp Voltage COMP Pull-Low Resistance OSCILLATOR FOSC ∆VOSC1/2 Oscillator Frequency Oscillator Sawtooth Amplitude Maximum Duty Cycle 255 85 300 1.5 88 345 kHz V % RL = 10kΩ to the ground CL = 100pF, RL = 10kΩ to the ground CL = 100pF, IO = ± µA 400 IO = 1mA IO = -1mA In fault or shutdown condition 2.7 85 20 8 3.0 2 0.1 dB MHz V/µs V V kΩ IO = 0~3mA, TA=25 C IO = 0~3mA, Over temperature POK = GND IPOK = 5mA o IO = 0A, VCC =8V IO = 0A, VCC = 8V ~ 13.2V IO = 3mA, VCC > 8V 5VCC = GND TA=25oC Over temperature 4.75 -20 -200 20 5 30 5.25 20 200 - V mV mV mA -1 -1.5 -100 1.2 -2 -3 4 - 1 1.5 8 70 +1 +1.5 +100 0.5 +2 +3 15 100 % nA V V µA V % mA Ω C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 4 www.anpec.com.tw APW7088 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=1.2V and TA= -20 ~ 70°C, unless otherwise specified. Typical values are at TA=25°C. The V5VCC is supplied by the internal regulator. Symbol Parameter Test Conditions APW7088 Min. Typ. 2.6 1 2.6 1.4 2.5 2 2 1.4 30 Max. 3.75 3 3 2.1 Unit MOSFET GATE DRIVERS UGATE1/2 Source Current UGATE1/2 Sink Current LGATE1/2 Source Current LGATE1/2 Sink Current UGATE1/2 Source Resistance UGATE1/2 Sink Resistance LGATE1/2 Source Resistance LGATE1/2 Sink Resistance TD Dead-Time VBOOT = 12V, VUGATE-VPHASE = 2V VBOOT = 12V, VUGATE-VPHASE = 2V VCC = 12V, VLGATE = 2V VCC =12V, VLGATE = 2V VBOOT = 12V, 100mA Source Current VBOOT = 12V, 100mA Sink Current VCC = 12V, 100mA Source Current VCC = 12V, 100mA Sink Current A A A A Ω Ω Ω Ω ns CURRENT SENSE AND DROOP FUNCTION ICSP ICSN CSP1/2 Pin Input Current CSN1/2 Maximum Output Current Current Sense Amplifier Bandwidth DROOP Output Current Accuracy DROOP Accuracy Current Difference Between Channel1/2 and Average Current SOFT-START AND ENABLE ISS Soft-Start Current Source Soft-Start Complete Threshold SS Pull-low Resistance POWER OK AND PROTECTIONS Over-Current Trip Level VUV VPOK_L VOV, VPOK_H FB Under-Voltage Threshold POK Lower Threshold FB Over-Voltage Threshold and POK Upper Threshold FB Over-Voltage Hysteresis TOTR Over-Temperature Trip Level Over-Temperature Hysteresis TJ rising ~ 2µs noise filter, VFB rising Percentage of VR at Error Amplifier ICS1 + ICS2 ~ 2µs noise filter, VFB falling, Percentage of VR at Error Amplifier 110 40 115 120 50 87.5 125 60 150 50 140 60 135 80 µA % % % mV o o -100 R CSN1/2 = 2kΩ, Sourcing current Sinking current 80 15 RDROOP = 2kΩ, VDROOP =0.005V ∆VFB = VDROOP/20, VDROOP=1V -5 -10 3 50 - +100 +5 +10 nA µA MHz µA mV % Flowing out of SS pin 8 - 10 3.2 10 12 18 µA V kΩ C C C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 5 www.anpec.com.tw APW7088 Typical Operating Characteristics 5VCC Line Regulation 6 5VCC Load Regulation 6 VCC=12V, VIN=12V 5VCC Voltage,V5VCC (V) 5VCC Voltage,V5VCC (V) 5 4 3 2 1 0 0 2 4 6 8 10 12 14 5 4 3 2 1 0 0 5 10 15 20 25 30 35 40 VCC Voltage,VCC (V) 5VCC Load Current ,I5VCC (mA) Output Voltage Load Regulation 0.857 Output Voltage Line Regulation 0.857 VID0, VID1 and VID2 are high 0.855 Feedback Voltage,VFB (V) Feedback Voltage,VFB (V) 0.855 0.853 0.851 0.849 0.847 0.845 0.843 0.841 0 VCC=12V, VIN=12V VID0, VID1 and VID2 are high 0.853 0.851 0.849 0.847 0.845 0.843 0.841 10 20 30 40 50 5 6 7 8 9 10 11 12 13 Output Current,IOUT (A) VIN Voltage,VIN (V) Reference Voltage Accuracy Over Temperature 0.863 330 Switching Frequency Over Temperature Reference Voltage,VDAC (V) Switching Frequency, FSW (kHz) 0.860 0.857 0.854 0.851 0.849 0.846 0.843 0.840 0.837 -40 VID0, VID1 and VID2 are high 320 310 300 290 280 270 -40 -20 0 20 40 60 80 o 100 120 -20 0 20 40 60 80 o 100 120 Junction Temperature, TJ ( C) C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 6 Junction Temperature, TJ ( C) www.anpec.com.tw APW7088 Operating Waveforms Power On IOUT=10A V5VCC Power Off IOUT=10A V5VCC 1 1 VCOMP 2 VCOMP 2 VSS VSS 3 VOUT 3 VOUT 4 4 CH1: V5VCC (5V/div) CH2: VCOMP (1V/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div CH1: V5VCC (5V/div) CH2: VCOMP (1V/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div Enable by SS Pin IOUT=10A IOUT=10A Shutdown by SS Pin VSS VSS 1 VCOMP 1 VCOMP 2 2 VOUT 3 3 VOUT CH1: VSS (2V/div) CH2: VCOMP (1V/div) CH3: VOUT (1V/div) Time: 10ms/div CH1: VSS (2V/div) CH2: VCOMP (1V/div) CH3: VOUT (1V/div) Time: 10ms/div C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 7 www.anpec.com.tw APW7088 Operating Waveforms (Cont.) Power On Without VIN2 Voltage VOUT 1 VPHASE1 2 VPHASE2 3 Vss CH1: VOUT (1V/div) CH2: VPHASE1 (10V/div) CH3: VPHASE2 (2V/div) CH4: VSS (2V/div) Time: 5ms/div 2 1 Under-Voltage Protection (UVP) VFB VPHASE1 VPHASE2 3 Vss 4 CH1: VFB (500mV/div) CH2: VPHASE1 (10V/div) CH3: VPHASE2 (10V/div) CH4: VSS (2V/div) Time: 500µs/div 4 Load Transient , 0A==>40A 1 2 3 VPHASE1 IPHASE2 VOUT Load Transient , 40A==>0A VPHASE1 1 IPHASE2 2 VOUT 3 IOUT RSEN=3kΩ L=0.56µH DCR=4mΩ IOUT 4 CH1: VPHASE1 (20V/div) CH2: IPHASE2 (20A/div) CH3: VOUT (AC, 200mV/div) CH4: IOUT (10A/div) Time: 20µs/div RSEN=3kΩ L=0.56µH DCR=4mΩ 4 CH1: VPHASE1 (20V/div) CH2: IPHASE2(20A/div) CH3: VOUT (AC, 200mV/div) CH4: IOUT (10A/div) Time: 20µs/div C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 8 www.anpec.com.tw APW7088 Operating Waveforms (Cont.) OCP at Slow Slew IOUT RSEN=1.5kΩ L=0.56µH DCR=4mΩ Short-Circuit Test After Power On IL1 RSEN=1.5kΩ L=0.56µH DCR=4mΩ IL1 1 1 IL2 2 3 4 CH1: IL1 (10A/div) CH2: IL2 (10A/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div VSS VOUT IL2 2 3 4 CH1: IL1 (10A/div) CH2: IL2 (10A/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div VSS VOUT Short-Circuit Test Before Power On RSEN=1.5kΩ L=0.56µH DCR=4mΩ IL1 OVP After Power On Pull-Up VFB > V OV VFB VSS 1 1 VLG1 2 IL2 3 2 3 4 CH1: IL1 (10A/div) CH2: IL2 (10A/div) CH3: VSS (5V/div) CH4: VOUT (1V/div) Time: 5ms/div VSS VLG2 4 VOUT CH1: VFB (500mV/div) CH2: VSS (2V/div) CH3: VLG1 (10V/div) CH4: VLG2 (10V/div) Time: 100µs/div C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 9 www.anpec.com.tw APW7088 Pin Description PIN 1 NAME UGATE1 FUNCTION High-side Gate Driver Output for channel 1. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. Bootstrap Supply for the floating high-side gate driver of channel 1. Connect the Bootstrap capacitor between the BOOT1 pin and the PHASE1 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT ranged from 0.1µF to 1µF. Ensure that CBOOT is placed near the IC. Internal Regulator Output. This is the output pin of the linear regulator, which is converting power from VCC and provides output current up to 20 mA minimums for internal bias and external usage. Signal Ground for the IC. All voltage levels are measured with respect to this pin. Tie this pin to ground island/plane through the lowest impedance connection available. Operation Phase Selection Input. Pulling this pin lower than 0.64V sets two-phase operation with both channels enabled. Pulling this pin higher than 0.8V sets single-phase operation with the channel 2 disabled. Once operating in single-phase mode, the operation mode is latched. It is required to toggle SS or 5VCC pin to reset the IC. Positive Input of current sensing Amplifier for channel 1. This pin combined with CSN1 senses the inductor current through an RC network. Negative Input of current sensing amplifier for channel 1. This pin combined with CSP1 senses the inductor current through an RC network. Negative Input of current sensing amplifier for channel 2. This pin combined with CSP2 senses the inductor current through an RC network. Positive Input of current sensing Amplifier for Channel 2. This pin combined with CSN2 senses the inductor current through an RC network. Load Line (droop) Setting. Connect a resistor between this pin and AGND to set the droop. A sourcing current, proportional to output current is present on the DROOP pin. The droop scale factor is set by the resistors (connected with CSP1, CSP2, and DROOP), resistance of the output inductors and the internal voltage divider with the ratio of 5%. This is one of the inputs for the internal DAC that provides the reference voltage for output regulation. This pin responds to logic threshold. The APW7088 decodes the VID inputs to establish the output voltage; see VID Tables for correspondence between DAC codes and output voltage settings. This pin is internally pulled high at floating status. Error Amplifier Output. Connect the compensation network between COMP, FB, and VOUT for Type 2 or Type 3 feedback compensation. Feedback Voltage. This pin is the inverting input to the error comparator. A resistor divider from the output to AGND is used to set the regulation voltage. Soft-start Current Output. Connect a capacitor from this pin to AGND to set the soft-start interval. Pulling the voltage on this pin below 0.5V causes COMP to pull low and then shuts off the output. One of DAC Inputs, same as VID0 and VID2. Power OK and 1.5V Reference Output. This pin is a reference output used to indicate the status of the voltages on SS pin and FB pin. POK provides 1.5V reference if VFB> 87.5% of reference (VR). Bootstrap Supply for the floating high-side gate driver of channel 2. Connect the Bootstrap capacitor between the BOOT2 pin and the PHASE2 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT range from 0.1µF to 1µF. Ensure that CBOOT is placed near the IC. High-side Gate Driver Output for Channel 2. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. Switch Node for Channel 2. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATE2 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. An Schottky diode between this pin and ground is recommended to reduce negative transient voltage that is common in a power supply system. Low-side Gate Driver Output for Channel 2. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off. 2 BOOT1 3 4 5VCC AGND 5 MODE 6 7 8 9 CSP1 CSN1 CSN2 CSP2 10 DROOP 11 VID0 12 13 14 15 16 COMP FB SS VID1 POK 17 BOOT2 18 UGATE2 19 PHASE2 20 LGATE2 C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 10 www.anpec.com.tw APW7088 Pin Description (Cont.) PIN 21 22 NAME VID2 VCC FUNCTION One of DAC Inputs, same as VID0 and VID1. Supply Voltage Input. This pin provides bias supply for the low-side gate drivers and the bootstrap circuit for high-side drivers. This pin can receive a well-decoupled 8V~13.2V supply voltage. Ensure that this pin is bypassed by a ceramic capacitor next to the pin. Low-side Gate Driver Output for Channel 1. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off. Switch Node for Channel 1. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATT1 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off. An Schottky diode between this pin and ground is recommended to reduce negative transient voltage which is common in a power supply system. Power Ground for the low-side gate drivers. Connect this pin to the source of low-side MOSFETs. This pin is used as sink for LGATE1 and LGATE2 drivers. 23 LGATE1 24 PHASE1 25 PGND Block Diagram POK VCC 5VCC Linear Regulator 1.5V Reference 87.5% 125% 5VCC VCC OV UV Power-onReset V5VCC 50% FB DROOP Droop Control SSEND Over-Temperature Protection PGND Control Logic Operation Phase Selection 3.6V VID0 VID1 VID2 VDROOP 3-Bit DAC VDAC + MODE VR Error Amplifier ISS 10µA Soft-Start SS COMP AGND 300kHz Oscillator and Sawtooth VCC VOSC1 VOSC2 VCC BOOT2 UGATE2 PHASE2 LGATE2 120µA VCC BOOT1 PWM Signal Controller VCC UGATE1 PHASE1 LGATE1 CSN2 CSP2 Current Sense ICS2 Current Balance ICS1+ICS2 ICS1 OC ICS1+ICS2 Current Sense CSN1 CSP1 C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 11 www.anpec.com.tw APW7088 Typical Application Circuit VIN +12V 2 5 BOOT1 MODE UGATE1 PHASE1 VCC LGATE1 5VCC PGND C4 10µF Q1 C5 0.1µF L1 0.56µH DCR=4mΩ VOUT 1.2V C6 1200µFx3 C7 47µFx2 IOCP=45A Q1 : APM4350KPx1 Q2 : APM4354KPx2 1 24 22 C13 1µF 3 23 25 Q2 C14 1µF 14 SS VID0 VID1 VID2 APW7088 BOOT2 17 C15 0.1µF 11 15 21 10 C8 10µF Q3 C10 0.1µF L2 0.56µH DCR=4mΩ C9 330µFx3 UGATE2 PHASE2 18 DROOP POK 19 R11 2kΩ C3 2.2nF 16 LGATE2 20 Q4 R4 2kΩ C2 22nF 12 13 CSP1 CSN1 COMP CSP2 FB AGND 4 6 7 9 8 R5 1.5kΩ PHASE1 PHASE2 R7 1.5kΩ C12 0.1µF C11 0.1µF CSN2 R2 3.6kΩ R1 1.5kΩ R3 51Ω C1 10nF R8 1.5kΩ R6 1.5kΩ C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 12 www.anpec.com.tw APW7088 Function Description 5VCC Linear Regulator 5VCC is the output terminal of the internal 5V linear regulator which regulates a 5V voltage on 5VCC by controlling an internal bypass transistor between VCC and 5VCC. The linear regulator powers the internal control circuitry and is stable with a low-ESR ceramic output capacitor. Bypass 5VCC to GND with a ceramic capacitor of at least 1µF. Place the capacitor physically close to the IC to provide good noise decoupling. The linear regulator can also provide output current, up to 20mA, for external loads. The linear regulator with currentlimit protection can protect itself during over-load or shortcircuit conditions on 5VCC pin. The 5VCC linear regulator stop regulating in Over-Temperature Protection. When the junction temperature is cooled by 50oC, the 5VCC linear regulator starts to regulate the output voltage again. 5VCC Power-On-Reset (POR) Figure 1 shows the power sequence. T he APW7088 keeps monitoring the voltage on 5VCC pin to prevent wrong logic operations which may occur when 5VCC voltage is not high enough for the internal control circuitry to operate. The 5VCC POR has a rising threshold of 4.6V (typical) with 0.58V of hysteresis. After the 5VCC voltage exceeds its rising Power-On-Reset (POR) voltage threshold, the IC starts a start-up process and then ramps up the output voltage to the setting of output voltage. The 5VCC POR signal resets the fault latch, set by the undervoltage or over-current event, when the signal is at low level. Voltage(V) When soft-start is initiated, the internal 10 µA current source starts to charge the capacitor. When the soft-start voltage across the soft-start capacitor reaches the enabled threshold about 0.8V (VSS_VT), the internal reference starts to rise and follows the soft-start voltage with converter operating at fixed 300kHz PWM switchin g frequency. When output voltage rises up to 87.5% of the regulation voltage, the power-ok is enabled. The softstart time (from the moment of enabling the IC to the moment when V POK g oes high) can be expressed as below : TSS = CSS × ( VSS _ VT + VDAC × 0.875) ISS where CSS= external soft-start capacitor VSS_VT= internal soft start threshold voltage, is about 0.8V VDAC= Internal digital VID programmable reference voltage ISS= soft-start current=10µA During soft-start stage, the under-voltage protection is inhibited. However, the over-voltage and over-current protection functions are enabled. If the output capacitor has residue voltage before startup, both lower and upper MOSFETs are in off-state until the internal soft-start voltage equals the FB pin voltage. This will ensure the output voltage starts from its existing voltage level. Operation Phase Selection The MODE pin programs single- or two- phase operation. It has a typical value for rising threshold of 0.8V, VMODE_THR, with 0.16V of hysteresis (0.64V), VMODE_THF. When the MODE pin voltage is higher than the VMODE_THR, the device operates in single-phase; when the MODE pin voltage is lower than VMODE_THF and VIN2 supply voltage is above approximate 4V, the device operates in two-phase operation. This function makes the APW7088 ideally suitable for dual power input applications like PCIE interfaced graphic VCC VSS 5VCC POR VSS_VT V5VCC VPOK VFB 1.5V cards. The figure 2 shows the power sources of the two channels. The input power of PWM1 converter is supplied by PCIE bus power and the input power of PWM2 Time Figure 1. Power Sequence C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 13 converter is supplied by an external power. If the input power connector of PWM2 converter is not plugged into www.anpec.com.tw APW7088 Function Description (Cont.) Operation Phase Selection (Cont.) the socket before start-up, the internal VIN2 sensing circuit can sense the absence of VIN2 and set the IC to operate in single-phase mode with PWM2 disabled. When the IC operates in two-phase mode, it can switch the operating mode from two-phase to single-phase operation. Once operating in single-phase mode, the operation mode is latched. It is required to toggle SS or 5VCC pin to reset the IC. PCIE +12V VCC rent protection responds, the output voltage will fall out of the required regulation range. The under-voltage continually monitors the VFB v oltage after soft-start is completed. If a load step is strong enough to pull the output voltage lower than the under-voltage threshold, the IC shuts down converter’ output. Cycling the 5VCC s POR resets the fault latch and starts a start-up process. The under-voltage threshold is 50% of the nominal output voltage. The under-voltage comparator has a built-in 2 µs noise filter to prevent the chips from wrong UVP shutdown being caused by noise. Over-Current Protection (OCP) PWM 1 converter External Power MODE VIN2 PWM 2 converter PHASE2 Operation Phase Selection Figure 3 shows the circuit of sensing inductor current. Connecting a series resistor (R S) and a capacitor (C S) network in parallel with the inductor and measuring the voltage (VC) across the capacitor can sense the inductor current. VL L PHASE IL Rs CSP CSN R2 Cs VC DCR 4V VIN2 sensing circuit Figure 2. VIN2 Sensing Circuit Over-Voltage Protection (OVP) The over-voltage protection function monitors the output voltage through FB pin. When the FB voltage increases over 125% of the reference voltage (VR) due to the highside MOSFET failure or other reasons, the over-voltage protection comparator designed with a 2µs noise filter will force the low-side MOSFET gate drivers high. This action actively pulls down the output voltage and eventually attempts to trigger the over-current shutdown of an ATX power supply. As soon as the output voltage is within regulation, the OVP comparator is disengaged. The chip will restore its normal operation. When the OVP occurs, the POK will drop to low as well. This OVP scheme only clamps the voltage overshoot and does not invert the output voltage when otherwise activated with a continuously high output from low-side MOSFETs driver, which is a common problem for OVP schemes with a latch. Under-Voltage Protection (UVP) In the operational process, when a short-circuit occurs, the output voltage will drop quickly. Before the over-curC opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 14 Figure 3. Illustration of Inductor Current Sensing Circuit The equations of the sensing network are, VL (s)=IL (s) × (SL+DCR) VC(S) = VL(S) × 1 IL(S) × (SL + DCR) = 1 + SRSCS 1 + SRSCS Take L DCR for example, if the above is true, the voltage across the RSCS = capacitor CS is equal to voltage drop across the inductor DCR, and the voltage VC is proportional to the current IL. The sensing current through the resistor R2 can be expressed as below : ICS = IL × DCR R2 www.anpec.com.tw APW7088 Function Description (Cont.) Over-Current Protection (OCP) (Cont.) Droop Control where ICS is the sensed current IL is the inductor current DCR is the inductor resistance R2 is the sense resistor The APW7088 is a two-phase PWM controller; therefore, the IC has two sensed current parts, ICS1 and ICS2. When ICS1 plus ICS2 is greater than 120µA, the over current occurs. In over-current protection, the IC shuts off the converter and then initials a new soft-start process. After 3 overcurrent events are counted, the device turns off both highside and low-side MOSFETs and the converter’ output s is latched to be floating. Current Sharing The APW7088 uses inductor’ DCRs and external nets works to sense the both currents flowing through the inductors of the PWM1 and PWM2 channels. The current sharing circuit, with closed-loop control, uses the sensed currents to adjust the two-phase inductor currents. For example, if the sensed current of PWM1 is bigger than PWM2, the duty of PWM1 will decrease and the duty of PWM2 will increase. Then, the device will reduce IL1 current and increase IL2 c urrent for current sharing. DROOP In some high current applications, a requirement on precisely controlled output impedance is imposed. This dependence of output voltage on load current is often termed droop regulation. As shown in figure 4, the droop control block generates a voltage through external resistor R DROOP , then set the droop voltage. The droop voltage, VDROOP , is proportional to the total current in two channels. As the following equation shows, VDROOP = 0.05 × [(ICS1 + ICS 2 ) × RDROOP ] RDROOP VREFIN/EN or 0.6V VDROOP VR Figure 4. Illustration of Droop Setting Function Over-Temperature Protection (OTP) When the junction temperature increases above the rising threshold temperature TOTR, the IC will enter the overtemperature protection state that suspends the PWM, which forces the LGATE and UGATE gate drivers to output low voltages and turns off the 5VCC linear regulator output. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 50oC. The OTP is designed with a 50oC hysteresis to lower the average TJ during continuous thermal overload conditions, which increases lifetime of the APW7088. Table 1. DAC Output Voltage vs. VID Inputs VID2 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 DAC Output Voltage, VDAC (V) 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 The VDROOP voltage is used the regulator to adjust the output voltage so that it’ equal to the reference voltage mis nus the droop voltage. C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 15 www.anpec.com.tw APW7088 Application Information Output Voltage Setting The output voltage is adjustable from 0.85V to 2.5V with a resistor-divider connected with FB, AGND, and converter’ s output. Using 1% or better resistors for the resistor-divider is recommended. The output voltage is determined RTOP   VOUT = VDAC ×  1 +   RGND  GAIN (dB) FLC -40dB/dec by : FESR Where VDAC is the internal digital VID programmable reference voltage, the RTOP is the resistor connected from converter’ output to FB and RGND i s the resistor cons nected from FB to AGND. Suggested RGND is in the range from 1K to 20KΩ . To prevent stray pickup, locate resistors RTOP and RGND close to the APW7088. PWM Compensation The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 180 degrees phase shift in the control loop. A compensation network among COMP, FB, and V OUT should be added. The compensation network is shown in Figure 8. The output LC filters consists of the output inductors and output capacitors. For two-phase convertor, when assuming VIN1=VIN2=VIN, L1=L2=L, the transfer function of the LC filter is given by : 1 + s × ESR × COUT 1 s × L × COUT + s × ESR × COUT + 1 2 The poles and zero of this transfer functions are : 1 FLC = 1 2× π× L × COUT 2 GAINLC = 2 -20dB/dec Frequency(Hz) Figure 6. Frequency Resopnse of the LC filters The PWM modulator is shown in figure 7. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given by : GAINPWM = VIN ∆VOSC Driver OSC PWM Comparator PHASE VIN ∆VOSC Output of Error Amplifier Driver Figure 7. The PWM Modulator The compensation network is shown in figure 8. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by: FESR = 1 2 × π × ESR × COUT The FLC is the double-pole frequency of the two-phase LC filters, and FESR is the frequency of the zero introduced by the ESR of the output capacitors. VPHASE1 L1=L L2=L VPHASE2 COUT ESR VOUT GAINAMP 1 1 //  R2 +  VCOMP sC1  sC2  = = 1 VOUT  R1//  R3 +  sC3   Figure 5. The Output LC Filter C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 16  1 1    s + ×s + R2 × C2   (R1 + R3) × C3  R1 + R3    = × C1 + C2   1 R1× R3 × C1   s s + × s +  R2 × C1× C2   R3 × C3   www.anpec.com.tw APW7088 Application Information (Cont.) PWM Compensation (Cont.) The pole and zero frequencies of the transfer function are: 1 FZ1 = 2 × π × R2 × C2 4. Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the following equation: C1 = C2 2 × π × R2 × C2 × FESR − 1 1 FZ2 = 2 × π × (R1 + R3 ) × C3 1 FP1 =  C1× C2  2 × π × R2 ×    C1 + C2  1 FP2 = 2 × π × R3 × C3 C1 R3 VOUT R1 FB VDAC VCOMP C3 R2 C2 5. Set the second pole FP2 a t the half of the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 w ith the capabilities of the error amplifier. FP2 = 0.5 X FSW FZ2 = FLC Combine the two equations will get the following component calculations: R3 = Figure 8. Compensation Network The closed loop gain of the converter can be written as: GAINLC X GAINPWM X GAINAMP Figure 9. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the R1 FSW −1 2 × FLC 1 C3 = π × R3 × FSW FZ1 FZ2 FP1 FP2 GAIN (dB) curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. 1. Choose a value for R1, usually between 1K and 5K. 2. Select the desired zero crossover frequency FO= (1/5 ~ 1/10) X FSW Use the following equation to calculate R2: ∆VOSC FO R2 = × × R1 VIN FLC 3. Place the first zero FZ1 before the output LC filter double pole frequency FLC. FZ1 = 0.75 X FLC Calculate the C2 by the following equation: 1 C2 = 2 × π × R2 × FLC × 0.75 20log (R2/R1) Compensation Gain 20log (VIN/ΔVOSC) FLC FESR PWM & Filter Gain Converter Gain Frequency(Hz) Figure 9. Converter Gain and Frequency Output Inductor Selection The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output voltage is fixed, it can be written as: C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 17 www.anpec.com.tw APW7088 Application Information (Cont.) Output Inductor Selection (Cont.) D= VOUT VIN of the inductor’ current. The ripple voltage of output cas pacitors can be represented by: ∆VCOUT = ∆VESR ∆ IP − P 8 × COUT × FSW = ∆IP − P × RESR For two-phase converter, the inductor value (L) determines the sum of the two inductor ripple currents, ∆IP-P, and affects the load transient reponse. Higher inductor value reduces the output capacitors’ripple current and induces lower output ripple voltage. The ripple current can be approxminated by : VIN - 2VOUT VOUT ∆IP - P = × FSW × L VIN These two components constitute a large portion of the total output voltage ripple. In some applications, multiple capacitors have to be parallelled to achieve the desired ESR value. If the output of the converter has to support another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors must also be considered. To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing the voltage excursion during load step change. For getting same load transient response, the output capacitance of two-phase converter only needs around half of output capacitance of single-phase converter. Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current specified on the capacitors in order to prevent the capacitor from over-heating. Input Capacitor Selection Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed each time high-side MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of high-side MOSFET and the source of low-side MOSFET. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. For two-phase converter, the RMS current of the bulk input capacitor is roughly calculated as the following equation: 18 www.anpec.com.tw Where FSW i s the switching frequency of the regulator. Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor’ ripple current and the regus lator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (FSW ) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage. Output Capacitor Selection Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting output capacitors. Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is recommended for switching regulator applications. In addition to high frequency noise related to MOSFET turn-on and turn-off, the output voltage ripple includes the capacitance voltage drop ∆VCOUT and ESR voltage drop ∆VESR caused by the AC peak-to-peak sum C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 APW7088 Application Information (Cont.) Input Capacitor Selection (Cont.) IRMS = IOUT × 2D ⋅ (1 - 2D) 2 where I OUT is the load current For a through hole design, several electrolytic capacitors may be needed. For surface mount design, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. MOSFET Selection The APW7088 requires two N-Channel power MOSFETs on each phase. These should be selected based upon RDS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection, and heatsink are the dominant design factors. The power dissipation includes two loss components, conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the high-side and the lowside MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the high-side MOSFET has switching losses since the low-side MOSFETs body diode or an external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous rectifier turns on. These equations assume linear voltagecurrent transitions and do not adequately model power loss due the reverse-recovery of the low-side MOSFET body diode. The gate-charge losses are dissipated by the APW7088 and don’ heat the MOSFETs. However, t large gate-charge increases the switching interval, tSW which increases the high-side MOSFET switching losses. Ensure that all MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature, and air flow. For the high-side and low-side MOSFETs, the losses are approximately given by the following equations: Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW Plow-side = IOUT (1+ TC)(RDS(ON))(1-D) 2 2 TC is the temperature dependency of RDS(ON) FSW is the switching frequency tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition loss. The switching interval, t SW , is the function of the reverse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET. Layout Consideration In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at higher frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short, wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. Besides, signal and power grounds are to be kept separating and finally combined using ground plane construction or single point grounding. The best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not recommended. Figure 10. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout : C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 19 www.anpec.com.tw APW7088 Application Information (Cont.) Layout Consideration (Cont.) • Keep the switching nodes (UGATEx, LGATEx, BOOTx, and PHASEx) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any layer. APW7088 VIN1=VIN BOOT1 • The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and discharging current. The traces from the gate drivers to the MOSFETs (UGATEx, LGATEx) should be short and wide. UGATE1 L1 PHASE1 LGATE1 RS1 CS1 VOUT • Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. In addition, the large layout plane between the drain of the MOSFETs (VIN and PHASEx nodes) can get better heat sinking. CSP1 CSN1 CSN2 CSP2 CS2 RS2 L O A D • For experiment result of accurate current sensing, the current sensing components are suggested to place close to the inductor part. To avoid the noise interference, the current sensing trace should be away from the noisy switching nodes. LGATE2 PHASE2 UGATE2 L2 • Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example, place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible). BOOT2 • The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capacitors should be close to the loads. The input capacitor’ ground should be close to the grounds of the s output capacitors and low-side MOSFET. VIN2=VIN Figure 10. Layout Guidelines • Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces can’ be close to the switching signal traces t (UGATEx, LGATEx, BOOTx, and PHASEx). C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 20 www.anpec.com.tw APW7088 Package Information QFN4x4-24 D A E Pin 1 D2 A1 A3 Pin 1 Corner E2 e S Y M B O L A A1 A3 b D D2 E E2 e L K 0.35 0.20 0.18 3.90 2.50 3.90 2.50 0.50 BSC 0.45 0.014 0.008 QFN4x4-24 MILLIMETERS MIN. 0.80 0.00 0.20 REF 0.30 4.10 2.80 4.10 2.80 0.008 0.154 0.098 0.154 0.098 0.020 BSC 0.018 MAX. 1.00 0.05 MIN. 0.031 0.000 0.008 REF 0.012 0.161 0.110 0.161 0.110 INCHES MAX. 0.039 0.002 Note : 1. Followed from JEDEC MO-220 WGGD-6. C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 21 LK b www.anpec.com.tw APW7088 Carrier Tape & Reel Dimensions OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B d Application A 330.0± 2.00 H 50 MIN. P1 8.0± 0.10 H A T1 T1 C d 1.5 MIN. D1 1.5 MIN. D 20.2 MIN. T 0.6+0.00 -0.40 W W E1 F 5.5± 0.05 K0 1.30± 0.20 12.4+2.00 13.0+0.50 -0.00 -0.20 P2 2.0± 0.05 D0 1.5+0.10 -0.00 12.0± 0.30 1.75± 0.10 A0 4.30± 0.20 B0 4.30± 0.20 QFN4x4-24 P0 4.0± 0.10 (mm) Devices Per Unit Package Type QFN4x4-24 Unit Tape & Reel Quantity 3000 C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 22 www.anpec.com.tw APW7088 Taping Direction Information QFN4x4-24 USER DIRECTION OF FEED Classification Profile C opyright © A NPEC Electronics Corp. Rev. A.4 - Feb., 2009 23 www.anpec.com.tw APW7088 Classification Reflow Profiles Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak (Tp)* package body Temperature Sn-Pb Eutectic Assembly 100 °C 150 °C 60-120 seconds 3 °C/second max. 183 °C 60-150 seconds See Classification Temp in table 1 20** seconds 6 °C/second max. 6 minutes max. Pb-Free Assembly 150 °C 200 °C 60-120 seconds 3°C/second max. 217 °C 60-150 seconds See Classification Temp in table 2 30** seconds 6 °C/second max. 8 minutes max. Time (tP)** within 5°C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness