APW7104BI-TRG

APW7104 1.5MHz, 1A Synchronous Buck Regulator Features General Description • 1A Output Current • Wide 2.7V~6.0V Input Voltage APW7104 is a 1.5MHz high efficiency monolithic synchronous buck regulator. Design with current mode scheme, • Fixed 1.5MHz Switching Frequency • Low Dropout Operating at 100% Duty Cycle • 25µA Quiescent Current • Integrate Synchronous Rectifier • 0.6V Reference Voltage • Current-Mode Operation with Internal the APW7104 is stable with ceramic output capacitor. Input voltage from 2.7V to 6.0V makes the APW7104 ideally suited for single Li-Ion battery powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable electrical devices. The internally fixed 1.5MHz operating frequency allows the using of small surface mount inductors and capacitors. The synchronous switches included inside increase the efficiency Compensation - Stable with Ceramic Output Capacitors - Fast Line Transient Response and eliminate the need of an external Schottky diode. The APW7104 is available in SOT-23-5/TSOT-23-5A • Short-Circuit Protection packages. • Over-Temperature Protection with Hysteresis • Available in SOT-23-5/TSOT-23-5A Packages • Lead Free and Green Devices Available (RoHS Compliant) Pin Configuration Applications • HD STB • BT Mouse RUN 1 • PND Instrument GND 2 • Portable Instrument APW7104 SW 3 C1 4.7µF (MLCC) L1 2.2µH 4 VIN 1 VOUT SW 3 APW7104 RUN FB 5 GND 2 4 VIN SOT-23-5/TSOT-23-5A (Top View) Simplified Application Circuit VIN 5 FB C2 10µF (MLCC) R1 C3 (option) R2 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 1 www.anpec.com.tw APW7104 Ordering and Marking Information Package Code BT : TSOT-23-5A B : SOT-23-5 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7104 Assembly Material Handling Code Temperature Range Package Code APW7104 BT : W04X X - Date Code APW7104 B : W04X X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol VIN Parameter Input Bias Supply Voltage (VIN to GND) RUN, FB, SW to GND Voltage PD Power Dissipation TSDR Unit V -0.3 ~ VIN+0.3 V Internally Limited Maximum Junction Temperature TSTG Rating -0.3 ~ 7 Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds W 150 o -65 ~ 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Junction-to-Ambient Resistance in Free Air Typical Value Unit (Note 2) TSOT-23-5A SOT-23-5 o C/W 220 250 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol VIN Parameter Input Bias Supply Voltage (VIN to GND) Range Unit 2.7 ~ 6 V VOUT Converter Output Voltage 0.6 ~ VIN V IOUT Converter Output Current 0~1 A L1 Converter Output Inductor 1.0 ~ 10 µH CIN Converter Input Capacitor 4.7 ~100 µF Converter Output Capacitor 4.7 ~100 µF Ambient Temperature -40 ~ 85 o -40 ~ 125 o COUT TA TJ Junction Temperature C C Note 3: Refer to the typical application circuit Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 2 www.anpec.com.tw APW7104 Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=3.6V and TA= 25 oC. Symbol Parameter APW7104 Test Conditions Unit Min. Typ. Max. 2.7 - 6 V SUPPLY VOLTAGE AND CURRENT VIN Input Voltage Range IDD Quiescent Current VFB = 0.66V - 25 40 µA ISD Shutdown Input Current RUN = GND - - 0.5 µA UVLO Threshold 2.1 2.35 2.6 V UVLO Hysteresis - 0.1 - V 0.588 0.6 0.612 V -2.5 - +2.5 % -50 - 50 nA POWER-ON-RESET (POR) and LOCKOUT VOLTAGE THRESHOLDS REFERENCE VOLTAGE VREF IFB Reference Voltage VIN=2.7V~6V, TA = -40~85 oC Output Voltage Accuracy 0A < IOUT < 1A FB Input Current INTERNAL POWER MOSFETS FSW Switching Frequency VFB = 0.6V 1.2 1.5 1.8 MHz Foldback Frequency VFB = 0.1V - 210 - kHz Foldback Threshold Voltage on FB VFB Falling - 0.2 - V - 50 - mV RP-FET Foldback Hysteresis High Side N-FET Switch ON Resistance ISW =200mA - 0.28 - Ω RN-FET Low Side P-FET Switch ON Resistance ISW =200mA - 0.25 - Ω Minimum On-Time - - 100 ns Maximum Duty Cycle - - 100 % 1.4 1.6 - A PROTECTION ILIM TOTP Maximum Inductor Current-Limit IP-FET, 2.7V≦VIN≦6V Over-Temperature Protection TJ Rising - 150 - Over-Temperature Protection Hysteresis TJ Falling - 30 - °C START-UP AND SHUTDOWN TSS Soft-Start Duration (Note 4) - 0.7 - ms RUN Input High Threshold VIN = 2.7V~6V - - 1 V RUN Input Low Threshold VIN = 2.7V~6V 0.4 - - V RUN Leakage Current VRUN = 5V, VIN = 5V -1 - 1 µA Note 4: Guarantee by design, not production test. Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 3 www.anpec.com.tw APW7104 Typical Operating Characteristics 100 100 90 90 80 80 Efficiency (%) Efficiency (%) (Refer to the application circuit in the section “Typical Application Circuits”, VIN=3.6V, VOUT=1.8V, TA=25oC unless otherwise specified ) Efficiency vs. Load Current Efficiency vs. Load Current 70 60 VIN=3.3V VIN=5V 50 40 VIN=3.3V VIN=5V 50 VOUT = 1.2V L = 2.2µH COUT = 10µF 30 20 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Load Current, IOUT(A) Load Current, IOUT(A) Supply Voltage v.s. Quiescent Current Supply Voltage vs. ON Resistance 40 1 0.35 35 RP-FET 0.30 30 ON Resistance(Ω) Quiescent Current, IDD(µA) 60 40 VOUT = 1.8V L = 2.2µH COUT = 10µF 30 70 25 20 15 10 5 0.25 0.20 RN-FET 0.15 0.10 0.05 0 2 2.5 3 3.5 4 4.5 5 5.5 0.00 6 Supply Voltage, V IN(V) 2 2.5 3 3.5 4 4.5 5 5.5 6 Supply Voltage, VIN(V) Supply Voltage v.s. Reference Voltage 0.65 Reference Voltage, VREF(V) 0.64 0.63 0.62 0.61 0.6 0.59 0.58 0.57 0.56 0.55 2 2.5 3 3.5 4 4.5 5 5.5 6 Supply Voltage, VIN (V) Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 4 www.anpec.com.tw APW7104 Operating Waveforms (Refer to the application circuit in the section “Typical Application Circuits”, VIN=3.6V, VOUT=1.8V, TA=25oC unless otherwise specified) Soft Start Load Transient Response 1A 1 VRUN 300mA 1 VOUT ,1V/Div, DC 2 IOUT, 0.5A/Div, DC VOUT ,100mV/Div, AC 2 3 IIN, 200mA/Div L=2.2µH, VIN=5V, VOUT=1.8V, COUT=10µF L=2.2µH, VIN=5V, COUT=10µF Time: 100µs/Div Time: 100µs/Div Normal Operation 2.5V 1.5V VIN, 0.5V/Div 1 VSW ,2V/Div, DC 2 VOUT ,20mV/Div, AC VOUT,200mV/Div,AC IL, 500mV/Div, DC 3 L=2.2µH, VINI=5V, VOUT=1.2V, COUT=10µF = 100mA OUT Time: 500ns/Div Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 5 www.anpec.com.tw APW7104 Pin Description PIN FUNCTION NO. NAME 1 RUN Enable Control Input. Forcing this pin above 1.0V enables the device. Forcing this pin below 0.4V shuts it down. In shutdown, all functions are disabled to decrease the supply current below 0.5µA. Do not leave RUN pin floating. 2 GND Power and Signal Ground. 3 SW Switch Node Connected to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFETs switches. 4 VIN Device and Converter Supply Pin. Must be closely decoupled to GND with a 4.7µF or greater ceramic capacitor. 5 FB Feedback Input Pin. The buck regulator senses feedback voltage via FB and regulates the FB voltage at 0.6V. Connecting FB with a resistor-divider from the output sets the output voltage of the buck converter. Block Diagram Current Sense Amplifier RUN VIN Shutdown Control Logic Control SW OverTemperature Protection Gate Driver Current -Limit Slope Compensation ZeroCrossing Comparator ∑ GND Oscillator ICMP Error Amplifier FB COMP EAMP SoftStart Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 6 VREF 0.6V www.anpec.com.tw APW7104 Typical Application Circuit IIN VIN L1 2.2µH 4 SW VIN VOUT 3 2.7~6V C1 4.7µF (MLCC) APW7104 1 RUN FB R1 5 C3 (option) GND 2 0.6V~VIN C2 0~1A 10µF (MLCC) R2 R1 ≤ 1MΩ is recommended R2 ≤ 200kΩ is recommended C1 closed to IC. Less than 2mm is recommended. Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 7 www.anpec.com.tw APW7104 Function Description Main Control Loop tion to reduce the dominant switching losses. In PFM The APW7104 is a constant frequency, synchronous rec- operation, the inductor current may reach zero or reverse on each pulse. A zero current comparator turn off the N- tifier and current-mode switching regulator. In normal operation, the internal P-channel power MOSFET is FET, forcing DCM operation at light load. These controls get very low quiescent current, help to maintain high effi- turned on each cycle. The peak inductor current at which ICMP turn off the P-FET is controlled by the voltage on the ciency over the complete load range. COMP node, which is the output of the error amplifier (EAMP). An external resistive divider connected between Slope Compensation and Inductor Peak Current The APW7104 is a peak current mode PWM step down converter. To prevent sub-harmonic oscillations, the VOUT and ground allows the EAMP to receive an output feedback voltage VFB at FB pin. When the load current APW7104 sense the peak current and add slope compensation to stable the converter. It is accomplished in- increases, it causes a slightly decrease in VFB relative to the 0.6V reference, which in turn causes the COMP volt- ternally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, age to increase until the average inductor current matches the new load current. Under-Voltage Lockout this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the APW7104 uses a An under-voltage lockout function prevents the device from operating if the input voltage on VIN is lower than approxi- special scheme that counteracts this compensating ramp, which allows the maximum inductor peak current mately 1.8V. The device automatically enters the shutdown mode if the voltage on VIN drops below approxi- to remain unaffected throughout all duty cycles. Adaptive Shoot-Through Protection mately 1.8V. This under-voltage lockout function is implemented in order to prevent the malfunctioning of the The gate driver incorporates adaptive shoot-through pro- converter. tection to high-side and low-side MOSFETs from conducting simultaneously and shorting the input supply. Soft-Start This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to The APW7104 has a built-in soft-start to control the output voltage rise during start-up. During soft-start, an in- rise. During turn-off the low-side MOSFET, the internal LGATE ternal ramp voltage, connected to the one of the positive inputs of the error amplifier, raises up to replace the ref- voltage is monitored until it is below 1.5V threshold, at which time the UGATE is released to rise after a constant erence voltage (0.6V typical) until the ramp voltage reaches the reference voltage. Then, the voltage on FB delay. During turn-off the high-side MOSFET, the UGATE voltage is also monitored until it is above 1.5V threshold, regulated at reference voltage. at which time the LGATE is released to rise after a constant delay. Enable/Shutdown Driving RUN to the ground places the APW7104 in shutdown mode. When in shutdown, the internal power Dropout Operation As the input supply voltage decreases to a value ap- MOSFETs turn off, all internal circuitry shuts down and the quiescent supply current reduces to 0.5µA maximum. proaching the output voltage, the duty cycle increases toward the maximum on time. Further, reduction of the Pulse Frequency Modulation Mode (PFM) The APW7104 is a fixed frequency, peak current mode supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The PWM step-down converter. At light loads, the APW7104 will automatically enter in pulse frequency mode opera- input voltage minus the voltage drop will determine the output voltage across the P-FET and the inductor. Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 8 www.anpec.com.tw APW7104 Function Description (Cont.) Dropout Operation (Cont.) An important detail to remember is that on resistance of P-FET switch will increase at low input supply voltage. Therefore, the user should calculate the power dissipation when the APW7104 is used at 100% duty cycle with low input voltage. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7104. When the junction temperature exceeds 150oC, a thermal sensor turns off the both power MOSFETs, allowing the devices to cool. The thermal sensor allows the converters to start a soft-start process and regulate the output voltage again after the junction temperature cools by 30oC. The OTP is designed with a 30oC hysteresis to lower the average Junction Temperature (TJ) during continuous thermal overload conditions, increasing the lifetime of the device. Short-Circuit Protection When the output is shortened to the ground, the frequency of the oscillator is reduced to about 210kHz, 1/7 of the nominal frequency. This frequency foldback ensures that the inductor current has more time to decay, thereby preventing runaway. The oscillator’s frequency will progressively increase to 1.5MHz when VFB or VOUT rises above 0V. Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 9 www.anpec.com.tw APW7104 Application Information Input Capacitor Selection shown in “Typical Application Circuits”. A suggestion of Because buck converters have a pulsating input current, a low ESR input capacitor is required. This results in the maximum value of R2 is 200kΩ to keep the minimum current that provides enough noise rejection ability through best input voltage filtering, minimizing the interference with other circuits caused by high input voltage spikes. the resistor divider. The output voltage can be calculated as below: R1  R1    VOUT = VREF ⋅  1 +  = 0.6 ⋅ 1 +  R2  R2    Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For good input voltage filtering, usually a 4.7µF input capacitor is sufficient. It can be increased without any limit for VOUT better input-voltage filtering. Ceramic capacitors show better performance because of the low ESR value, and R1≤1MΩ they are less sensitive against voltage transients and spikes compared to tantalum capacitors. Place the input FB R2 ≤ 200kΩ APW7104 capacitor as close as possible to the input and GND pin of the device for better performance. GND Inductor Selection Output Capacitor Selection For high efficiencies, the inductor should have a low DC The current-mode control scheme of the APW7104 allows the use of tiny ceramic capacitors. The higher ca- resistance to minimize conduction losses. Especially at high-switching frequencies, the core material has a pacitor value provides the good load transients response. higher impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. If required, inductor core losses. This needs to be considered when selecting the appropriate inductor. The inductor value de- tantalum capacitors may be used as well. The output ripple is the sum of the voltages across the ESR and the termines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the ideal output capacitor. lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient ∆VOUT response. A reasonable starting point for setting ripple current, ∆IL, is 40% of maximum output current. The rec-  V VOUT ⋅ 1 − OUT VIN  ≅ FSW ⋅ L     1  ⋅  ESR +  8 ⋅ FSW ⋅ COUT      When choosing the input and output ceramic capacitors, ommended inductor value can be calculated as below: choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage char-   V VOUT 1 − OUT  VIN   L≥ FSW ⋅ ∆IL acteristics of all the ceramics for a given value and size. VIN IL(MAX) = IOUT(MAX) + 1/2 x ∆IL IIN IP-FET To avoid the saturation of the inductor, the inductor should IL be rated at least for the maximum output current of the converter plus the inductor ripple current. CIN Output Voltage Setting P-FET VOUT SW N-FET In the adjustable version, the output voltage is set by a resistive divider. The external resistive divider is con- IOUT ESR COUT nected to the output, allowing remote voltage sensing as Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 10 www.anpec.com.tw APW7104 Application Information (Cont.) Output Capacitor Selection (Cont.) The maximum power dissipation on the device can be shown as follow figure: IL 0.8 Maximum Power Disspation (W) ILIM IPEAK ∆IL IOUT IP-FET 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 Junction Temperature (oC) Thermal Consideration Layout Consideration In most applications, the APW7104 does not dissipate much heat due to its high efficiency. But, in applications For all switching power supplies, the layout is an impor- where the APW7104 is running at high ambient temperature with low supply voltage and high duty cycles, the heat tant step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully dissipated may exceed the maximum junction tempera- done, the regulator might show noise problems and duty cycle jitter. ture of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned 1. The input capacitor should be placed close to the VIN and GND. Connecting the capacitor and VIN/GND with off and the SW node will become high impedance. To avoid the APW7104 from exceeding the maximum junc- short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GND tion temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to deter- to capacitor less than 2mm respectively is recommended. mine whether the power dissipated exceeds the maximum junction temperature of the part. The power dissi- 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed pated by the part is approximated: as close as possible to the SW pin to minimize the noise coupling into other circuits. PD ≅ IOUT2 x (RP-FET x D+RN-FET x (1-D)) The temperature rise is given by: 3. The output capacitor should be place closed to converter VOUT and GND. TR = (PD)(θJA) 4. Since the feedback pin and network is a high impedance circuit the feedback network should be routed Where PD is the power dissipated by the regulator, D is duty cycle of main switch away from the inductor. The feedback pin and feedback network should be shielded with a ground plane D = VOUT/VIN The θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, or trace to minimize noise coupling into this circuit. 5. A star ground connection or ground plane minimizes TJ, is given by: ground shifts and noise is recommended. TJ = TA + TR Where TA is the ambient temperature. Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 11 www.anpec.com.tw APW7104 Layout Consideration (cont.) Via to GND R2 FB VRUN R1 L1 Via to VOUT VOUT SW COUT CIN VIN GND APW7104 Layout Suggestion Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 12 www.anpec.com.tw APW7104 Package Information TSOT-23-5A D e E E1 SEE VIEW A b c 0.25 A GAUGE PLANE SEATING PLANE A1 A2 e1 L VIEW A TSOT-23-5A S Y M B O L MIN. MAX. MIN. MAX. MILLIMETERS INCHES A 0.70 1.00 0.028 0.039 A1 0.01 0.10 0.000 0.004 A2 0.70 0.90 0.028 0.035 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 e 0.95 BSC e1 0.071 0.037 BSC 1.90BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Followed from JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 13 www.anpec.com.tw APW7104 Package Information SOT-23-5 D e E E1 SEE VIEW A b c 0.25 A L 0 GAUGE PLANE SEATING PLANE A1 A2 e1 VIEW A S Y M B O L SOT-23-5 INCHES MILLIMETERS MIN. MAX. MIN. A MAX. 1.45 0.057 A1 0.00 0.15 0.000 0.006 A2 0.90 1.30 0.035 0.051 0.020 b 0.30 0.50 0.012 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 0.118 0.071 E 2.60 3.00 0.102 E1 1.40 1.80 0.055 e 0.95 BSC e1 1.90 BSC 0.037 BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 14 www.anpec.com.tw APW7104 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TSOT-23-5A A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 Application SOT-23-5 4.0±0.10 4.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity TSOT-23-5A Tape & Reel 3000 SOT-23-5 Tape & Reel 3000 Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 15 www.anpec.com.tw APW7104 Taping Direction Information TSOT-23-5A USER DIRECTION OF FEED SOT-23-5 USER DIRECTION OF FEED Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 16 www.anpec.com.tw APW7104 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3 °C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright  ANPEC Electronics Corp. Rev. A.6 - Mar., 2012 17 www.anpec.com.tw APW7104 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness