APW7120
5V to 12V Supply Voltage, 8-PIN, Synchronous Buck PWM Controller
Features
General Description
•
Operating with Single 5~12V Supply Voltage
The APW7120 is a fixed 300kHz frequency, voltage
or Two Supply Voltages
mode, and synchronous PWM controller. The device
•
•
•
drives two low cost N-channel MOSFETs and is de-
Drive Dual Low Cost N-Channel MOSFETs
signed to work with single 5~12V or two supply
- Adaptive Shoot-Through Protection
voltage(s), providing excellent regulation for load
Built-in Feedback Compensation
transients.
- Voltage-Mode PWM Control
The APW7120 integrates controls, monitoring, and
- 0~100% Duty Ratio
protection functions into a single 8-pin package to
- Fast Transient Response
provide a low cost and perfect power solution.
±2% 0.8V Reference
A power-on-reset (POR) circuit monitors the VCC
- Over Line, Load Regulation, and Operating
supply voltage to prevent wrong logic controls. An
internal 0.8V reference provides low output voltage
Temperature
•
•
•
•
•
•
•
•
down to 0.8V for further applications. An built-in digital
Programmable Over-Current Protection
soft-start with fixed soft-start interval prevents the
- Using RDS(ON) of Low-Side MOSFET
output voltage from overshoot as well as limits the
Hiccup-Mode Under-Voltage Protection
input current. The controller’s over-current protection
118% Over-Voltage Protection
monitors the output current by using the voltage drop
Adjustable Output Voltage
across the low-side MOSFET’s RDS(ON), eliminating the
need of a current sensing resistor. Additional under
Small Converter Size
voltage and over voltage protections monitor the
- 300kHz Constant Switching Frequency
voltage on FB pin for short-circuit and over-voltage
- Small SOP-8 Package
protections. The over-current protection cycles the
Built-In Digital Soft-Start
soft-start function until 4 over-current events are
counted.
Shutdown Control Using an External MOSFET
Pulling and holding the voltage on OCSET pin below
Lead Free and Green Devices Available
0.15V with an open drain device shuts down the
(RoHS Compliant)
controller.
Applications
•
•
•
Pin Configuration
Motherboard
Graphics Card
BOOT 1
8 PHASE
UGATE 2
7 OCSET
GND 3
High Current, up to 20A, DC-DC Converters
6 FB
LGATE 4
5 VCC
SOP-8
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
1
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APW7120
Ordering and Marking Information
Package Code
K : SOP-8
Operating Ambient Temperature Range
E : -20 to 70 °C
Handling Code
TR : Tape & Reel
Assembly Material
L : Lead Free Device
G : Halogen and Lead Free Device
APW7120
Assembly Material
Handling Code
Temperature Range
Package Code
APW7120 K :
APW7120
XXXXX
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish;
which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and
halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed
1500ppm by weight).
Absolute Maximum Ratings
Symbol
(Note 1)
Parameter
Rating
Unit
VCC
VCC Supply Voltage (VCC to GND)
-0.3 ~ 16
V
VBOOT
BOOT Voltage (BOOT to PHASE)
-0.3 ~ 16
V
-5 ~ VBOOT+0.3
-0.3 ~ VBOOT+0.3
V
-5 ~ VCC+0.3
-0.3 ~ VCC+0.3
V
-10 ~ 30
-3 ~ 16
V
UGATE Voltage (UGATE to PHASE)
400ns pulse width
LGATE Voltage (LGATE to GND)
400ns pulse width
PHASE Voltage (PHASE to GND)
400ns pulse width
VI/O
Input Voltage (OCSET, FB to GND)
-0.3 ~ 7
Maximum Junction Temperature
TSTG
TSDR
Storage Temperature
Maximum Lead Soldering Temperature, 10 Seconds
V
150
o
-65 ~ 150
o
260
o
C
C
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
θJA
Parameter
Junction-to-Ambient Resistance in free air
Typical Value
(Note 2)
160
Unit
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Copyright ANPEC Electronics Corp.
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APW7120
Recommended Operating Conditions
Symbol
(Note 3)
Parameter
Range
Unit
VCC
VCC Supply Voltage
4.5 ~ 13.2
V
VOUT
Converter Output Voltage
0.8 ~ 80%VIN
V
VIN
Converter Input Voltage
2.2 ~ 13.2
V
IOUT
Converter Output Current
TA
0 ~ 20
Ambient Temperature
TJ
Junction Temperature
A
-20 ~ 70
o
-20 ~ 125
o
C
C
Note 3: Please refer to the typical application circuit.
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC.
Typical values are at TA = 25oC.
Symbol
Parameter
Test Conditions
APW7120
Min.
Typ. Max.
Unit
SUPPLY CURRENT
-
2.1
6
mA
-
1.5
4
mA
Rising VCC Threshold
3.8
4.1
4.4
V
Hysteresis
0.1
0.45
0.6
V
250
300
350
kHz
-
1.5
-
VP-P
-
0.8
-
V
TA =25°C
-0.75
-
+0.75
TA =-20~70°C, VCC=5V ~ 12V
-1.5
-
+1.5
-
0.05
+0.3
%
DC Gain
-
86
-
dB
FP1
First Pole Frequency
-
0.4
-
Hz
FZ
Zero Frequency
-
0.4
-
kHz
FP2
Second Pole Frequency
-
430
-
kHz
Average UGATE Duty Range
0
-
85
%
FB Input Current
-
-
0.1
µA
IVCC
VCC Nominal Supply Current
UGATE and LGATE Open
VCC Shutdown Supply Current
POWER-ON-RESET
OSCILLATOR
FOSC
∆VOSC
Free Running Frequency
Ramp Amplitude
REFERENCE VOLTAGE
VREF
Reference Voltage
Accuracy
Line Regulation
Measured at FB Pin
VCC=5V ~ 12V
%
ERROR AMPLIFIER
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
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APW7120
Electrical Characteristics (Cont.)
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC.
Typical values are at TA = 25oC.
Symbol
Parameter
Test Conditions
APW7120
Min.
Typ.
Max.
Unit
PWM CONTROLLER GATE DRIVERS
TD
UGATE Source
VBOOT-PHASE =12V, VUGATE-PHASE =6V
1.0
2.0
-
A
UGATE Sink
VBOOT-PHASE =12V, VUGATE-PHASE=1V
-
3.5
7
Ω
LGATE Source
VCC=12V, VLGATE=6V
1.0
1.9
-
A
LGATE Sink
VCC=12V, VLGATE=1V
-
2.6
5
Ω
Dead-Time
Guaranteed by Design
-
40
100
ns
35
40
45
µA
0.37
0.4
0.43
V
62
67
72
%
-
45
-
mV
114
118
122
%
2
3.8
5
ms
0.1
0.15
0.3
V
-
40
-
mV
PROTECTIONS
IOCSET OCSET Current Source
UVFB
Over-Current Reference
Voltage
FB Under-Voltage Threshold
VPHASE=0V, Normal Operation
TA =-20~70°C
VFB Falling
FB Under-Voltage Hysteresis
Over-Voltage Threshold
VFB Rising
SOFT-START AND SHUTDOWN
TSS
Soft-Start Interval
OCSET Shutdown Threshold
Falling VOCSET
OCSET Shutdown Hysteresis
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APW7120
Function Pin Description
BOOT (Pin 1)
This pin provides ground referenced bias voltage to
where R1 is the resistor connected from VOUT to FB ,
the high-side MOSFET driver. A bootstrap circuit with
and R2 is the resistor connected from FB to GND. The
a diode connected to 5~12V is used to create a
FB pin is also monitored for under and over-voltage
voltage suitable to drive a logic-level N-channel
events.
MOSFET.
OCSET (Pin 7)
UGATE (Pin 2)
The OCSET is a dual-function input pin for over-
Connect this pin to the high-side N-channel MOSFET’s
current protection and shutdown control. Connect a
gate. This pin provides gate drive for the high-side
resistor (ROCSET) from this pin to the Drain of the low-
MOSFET.
side MOSFET. This resistor, an internal 40µA current
source (IOCSET), and the MOSFET’s on-resistance
GND (Pin 3)
(RDSON) set the converter over-current trip level (IPEAK)
The GND terminal provides return path for the IC’s bias
according to the following formula:
current and the low-side MOSFET driver’s pull-low
I PEAK =
current. Connect the pin to the system ground via very
low impedance layout on PCBs.
40μ A ⋅ R OCSET - 0.4V
R DSON
(A)
Pulling and holding this pin below 0.15V with an open
LGATE (Pin 4)
drain device, with very low parasitic capacitor, shuts
Connect this pin to the low-side N-channel MOSFET’s
down the IC with floating output and also resets the
gate. This pin provides gate drive for the low-side
over-current counter. Releasing OCSET pin initiates a
MOSFET.
new soft-start and the converter works again.
VCC (Pin 5)
PHASE (Pin 8)
Connect this pin to a 5~12V supply voltage. This pin
The pin provides return path for the high-side MOSFET
provides bias supply for the control circuitry and the
driver’s pull-low current. Connect this pin to the high-
low-side MOSFET driver. The voltage at this pin is
side MOSFET’s source.
monitored for the Power-On-Reset (POR) purpose.
FB (Pin 6)
This pin is the inverting input of the internal Gm amplifier.
Connect this pin to the output (VOUT) of the converter
via an external resistor divider for closed-loop operation.
The output voltage set by the resistor divider is determined using the following formula :
V OUT = 0.8V ⋅ ( 1 +
R1
)
R2
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
(V)
5
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APW7120
Block Diagram
VCC
3VCC
40uA
OCSET
Power-OnReset
Regulator
POR
3VCC
67%VREF
0.4V
OC
2.5V
Enable
0.15V
Soft-Start
and Fault
Logic
UV
BOOT
OV
UGATE
118%VREF
Inhibit
Soft-Start
COMP
FB
PHASE
Gate
Control
PWM
VCC
Gm
Amplifier
VREF
0.8V
LGATE
FOSC
300kHz
Oscillator
GND
Application Circuit
L1
1uH
D1
1N 4148
VBIAS
VIN
+5V /12V
C5
1uF
1
C2
0. 1uF
C 3, C 4
820uF x 2
+5/12V
B OOT
R4
2.2
UGA TE
5
PH A SE
VC C
C1
1uF
U 1 OC SET
APW 7120
6
Q1
APM2512
2
8
7
VOU T
C 6, C 7
1000uF x 2
1.8V /15A
Q2
APM2512
4
FB
L2
1.5uH
R5
LGA TE
GN D
3
Shutdown
R1
1.5k
Q3
2N 7002
R2
1.2k
C8
0.1uF
R3
200
C3, C4 : 820µF/16V , ESR=25 mΩ
C6, C7 : 1000µF/6.3V, ESR=30 mΩ
Copyright ANPEC Electronics Corp.
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APW7120
Typical Operating Characteristics
Reference Voltage vs Junction Temperature
Switching Frequency vs Junction Temperature
0.812
350
Switching Frequency, FOSC (kHz)
Reference Voltage, VREF (V)
0.810
0.808
0.806
0.804
0.802
0.800
0.798
0.796
0.794
0.792
0.790
0.788
340
330
320
310
300
290
280
270
260
250
-50
-25
0
25
50
75
100
125
150
-50
-25
OCSET Current vs Junction Temperature
25
50
75
100
125
150
VCC POR Threshold Voltage vs Junction Temperature
45
4.4
44
4.3
VCC POR Threshold Voltage (V)
OCSET Current , IOCSET (µA)
0
Junction Temperature (oC)
Junction Temperature (oC)
43
42
41
40
39
38
37
36
35
4.2
4.1
Rising VCC
4.0
3.9
3.8
Falling VCC
3.7
3.6
3.5
3.4
-50
-25
0
25
50
75
100
125
150
-50
0
25
50
75
100
125
150
o
Junction Temperature ( C)
Junction Temperature (oC)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
-25
7
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APW7120
Typical Operating Characteristics (Cont.)
OCSET Shutdown Threshold Voltage
OCSET Shutdown Threshold Voltage (V)
vs Junction Temperature
0.20
Falling VOCSET
0.18
0.16
0.14
0.12
0.10
-50
-25
0
25
50
75
100
125
150
Junction Temperature (oC)
Operating Waveforms
(Refer to the typical application circuit, VBAIS=VIN=+12V supplied by an ATX Power Supply)
1. Load Transient Response : IOUT = 0A -> 15A -> 0A
- IOUT slew rate = ±15A/µs
IOUT = 0A -> 15A
IOUT = 0A -> 15A -> 0A
IOUT = 15A -> 0A
VOUT=1.8V
VOUT
1
1
VOUT
VOUT
VUGATE
VUGATE
3
3
2
Ch1 : VOUT, 100mV/Div, DC,
Offset = 1.8V
Ch2 : IOUT, 10A/Div
Ch3 : VUGATE, 20V/Div, DC
Time : 2µs/Div
BW = 20 MHz
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
VUGATE
3
15A
IOUT
2
1
IOUT
0A
Ch1 : VOUT, 100mV/Div, DC,
Offset = 1.8V
Ch2 : IOUT, 10A/Div
Ch3 : VUGATE, 20V/Div, DC
Time : 50µs/Div
BW = 20 MHz
8
2
IOUT
Ch1 : VOUT, 100mV/Div, DC,
Offset = 1.8V
Ch2 : IOUT, 10A/Div
Ch3 : VUGATE, 20V/Div, DC
Time : 2µs/Div
BW = 20 MHz
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APW7120
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)
2. UGATE and LGATE Switching Waveforms
Falling VUGATE
Rising VUGATE
IOUT = 15A
VLGATE
VUGATE
VLGATE
VUGATE
1,2
1,2
Ch1 : VUGATE, 5V/Div, DC
Time : 20ns/Div
Ch2 : VLGATE, 2V/Div, DC
BW = 500 MHz
Ch1 : VUGATE, 5V/Div, DC Ch2 : VLGATE, 2V/Div, DC
Time : 20ns/Div
BW = 500 MHz
3. Powering ON / OFF
Powering ON
VCC=VIN=5V
RL=0.12Ω
Powering OFF
VCC
VCC
VCC=VIN=5V
RL=0.12Ω
1
1
IL
IL
3
3
VOUT
2
2
Ch1 : VCC, 2V/Div, DC
Ch3 : IL, 10A/Div, DC
BW = 20 MHz
Ch2 : VOUT, 1V/Div, DC
Time : 5ms/Div
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
VOUT
Ch1 : VCC, 2V/Div, DC
Ch3 : IL, 10A/Div, DC
BW = 20 MHz
9
Ch2 : VOUT, 1V/Div, DC
Time : 10ms/Div
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APW7120
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)
3. Powering ON / OFF (Cont.)
Powering ON
VCC=VIN=12V
RL=0.12Ω
Powering OFF
VCC=VIN=12V
RL=0.12Ω
VCC
VCC
1
1
IL
IL
3
3
VOUT
VOUT
2
2
Ch1 : VCC, 5V/Div, DC
Ch3 : IL, 10A/Div, DC
BW = 20 MHz
Ch1 : VCC, 5V/Div, DC
Ch3 : IL, 10A/Div, DC
BW = 20 MHz
Ch2 : VOUT, 1V/Div, DC
Time : 5ms/Div
Ch2 : VOUT, 1V/Div, DC
Time : 10ms/Div
4. Enabling and Shutting Down
Enabling by Releasing OCSET Pin
3
Shutting Down by Pulling OCSET Low
VOCSET
3
VOCSET
2
VUGATE
2
VUGATE
VOUT
1
VOUT
1
IOUT=2A
Ch1 : VOUT, 1V/Div, DC
Ch2 : VUGATE, 20V/Div, DC
Ch3 : VOCSET, 2V/Div, DC Time : 2ms/Div
BW = 20 MHz
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
Ch1 : VOUT, 1V/Div, DC
Ch3 : VOCSET, 2V/Div, DC
BW = 20 MHz
10
Ch2 : VUGATE, 20V/Div, DC
Time : 2ms/Div
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APW7120
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)
5. Over-Current Protection
No Connecting a shutdown MOSFET
at OCSET Pin
Connecting a shutdown MOSFET
(2N7002) at OCSET Pin
ROCSET=15k
APM2512
ROCSET=15k
APM2512
VOUT
1
IL
2
Ch1 : VOUT, 1V/Div, DC
Time : 5ms/Div
VOUT
1
IL
2
Ch2 : IL, 10A/Div, DC
BW = 20 MHz
Ch1 : VOUT, 1V/Div, DC
Time : 5ms/Div
Ch2 : IL, 10A/Div, DC
BW = 20 MHz
6. OCSET Voltage RC Delay
No Connecting a shutdown MOSFET
Connecting a shutdown MOSFET
(2N7002) at OCSET Pin
at OCSET Pin
VOCSET
VOCSET
IL
IL
OCP
1,2
1,2
CProber=8pF
Ch1 : VOCSET, 0.5V/Div, DC
Time : 2µS/Div
Ch2 : IL, 10A/Div, DC
BW = 20 MHz
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
CProber=8pF
C2N7002=44pF (measured)
Ch1 : VOCSET, 0.5V/Div, DC
Time : 2µ S/Div
11
OCP
Ch2 : IL, 10A/Div, DC
BW = 20 MHz
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APW7120
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)
7. Short-Circuit Test
6. OCSET Voltage RC Delay (Cont.)
Connecting a shutdown MOSFET
(APM2322) at OCSET Pin
Shorted by a wire
IL
OCP
OCP
OCP
OCP
VOUT
1
UVP
VOCSET
1,2
CProber=8pF
CAPM2322 =89pF (measured)
IL
OCP
2
Ch1 : VOCSET, 0.5V/Div, DC Ch2 : IL, 10A/Div, DC
BW = 20 MHz
Time : 2µS/Div
Ch1 : VOUT, 1V/Div, DC
Time : 5ms/Div
Ch2 : IL, 10A/Div, DC
BW = 20 MHz
Function Description
Power-On-Reset (POR)
ence voltage. The soft-start interval is about 3.2ms
typical, independent of the converter’s input and out-
The APW7120 monitors the VCC voltage (V CC) for
put voltages.
Power-On-Reset function, preventing wrong logic
operation during powering on. When the VCC voltage
Over-Current Protection (OCP)
is ready, the APW7120 starts a start-up process and
The over-current function protects the switching
then ramps the output voltage up to the target voltage.
c o nverter against over-current or short-circuit
conditions. The controller senses the inductor current
Soft-Start
by detecting the drain-to-source voltage, product of
The APW7120 has a built-in digital soft-start to control
the inductor’s current and the on-resistance, of the
the output voltage rise and limit the current surge at
low-side MOSFET during it’s on-state. This method
the start-up. During the soft-start, an internal ramp con-
enhances the converter’s efficiency and reduces cost
nected to the one of the positive inputs of the Gm
by eliminating a current sensing resistor.
amplifier rises up from 0V to 2V to replace the reference
A resistor (ROCSET), connected from the OCSET to the
voltage (0.8V) until the ramp voltage reaches the referCopyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
12
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APW7120
Function Description (Cont.)
Over-Current Protection (OCP) (Cont.)
latching. The function is disabled during soft-start
low-side MOSFET’s drain, programs the over-current
process.
trip level. An internal 40µA (typical) current source
Over-Voltage Protection (OVP)
flowing through the ROCSET develops a voltage (VROCSET)
The over-voltage protection monitors the FB voltage to
across the ROCSET. When the VOCSET (VROCSET+ VDS of
prevent the output from over-voltage. When the
the low-side MOSFET) is less than the internal over-
output voltage rises to 118% of the nominal output
current reference voltage (0.4V, typical), the IC shuts
voltage, the APW7120 turns on the low-side MOSFET
off the converter and then initiates a new soft-start
until the output voltage falls below the OVP
process. After 4 over-current events are counted, the
threshold, regulating the output voltage around the
device turns off both high-side and low-side MOSFETs
OVP thresholds.
and the converter’s output is latched to be floating.
Please pay attention to the RC delay effect. It causes
Adaptive Shoot-Through Protection
the OCP trip level to be the function of the
The gate driver incorporates adaptive shoot-through
operating duty. The parasitic capacitance, includ-
protection to high-side and low-side MOSFETs from
ing the capacitance inside the OCSET, external PCB
conducting simultaneously and shorting the input
trace capacitance, and the COSS of the shutdown
supply. This is accomplished by ensuring the falling
MOSFET, must be minimized, especially selecting a
gate has turned off one MOSFET before the other is
shutdown MOSFET with very small COSS. The OCP
allowed to rise.
trip level follows the duty to increase a little at low
During turn-off of the low-side MOSFET, the LGATE
operating duty, but very much at high operating duty,
voltage is monitored until it reaches a 1.5V threshold,
like the RC delay curve. Due to load regulation or
at which time the UGATE is released to rise after a
current-limit, heavy load normally reduces converter’s
constant delay. During turn-off of the high-side
input voltage and increases the power loses. During
MOSFET, the UGATE-to-PHASE voltage is also
heavy load, the APW7120 regulates the output voltage
monitored until it reaches a 1.5V threshold, at which
by expending the duty. This rises up the OCP trip level
time the LGATE is released to rise after a constant
at the same time.
delay.
Under-Voltage Protection (UVP)
Shutdown Control
The under-voltage function monitors the FB voltage
Pulling the OCSET voltage below 0.15V by an open
(VFB) to protect the converter against short-circuit
drain transistor, shown in typical application circuit,
shuts down the APW7120 PWM controller. In shutdown mode, the UGATE and LGATE are pulled to
PHASE and GND respectively, the output is floating.
conditions. When the VFB falls below the falling UVP
threshold (67% VREF), the APW7120 shuts off the
converter. After a preceding delay, which starts at
the beginning of the under-voltage shutdown, the
APW 7120 initiates a new soft-start to resume
regulating. The under-voltage protection shuts off
and then re-starts the converter repeatedly without
Copyright ANPEC Electronics Corp.
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APW7120
Application Information
T=1/FOSC
Input Capacitor Selection
Use small ceramic capacitors for high frequency
V U GA TE
decoupling and bulk capacitors to supply the surge
DT
I
IOU T
current needed each time high-side MOSFET(Q1) turns
on. Place the small ceramic capacitors physically close
IL
to the MOSFETs and between the drain of Q1 and the
IOU T
source of low-side MOSFET(Q2).
IQ1
The important parameters for the bulk input capacitor
I
IC OU T
are the voltage rating and the RMS current rating. For
reliable operation, select the bulk capacitor with voltage
V OU T
and current ratings above the maximum input voltage
and largest RMS current required by the circuit. The
V OU T
capacitor voltage rating should be at least 1.25 times
Figure 1 Buck Converter Waveforms
greater than the maximum input voltage and a voltage
rating of 1.5 times is a conservative guideline. The
Output Capacitor Selection
RMS current of the bulk input capacitor is calculated
An output capacitor is required to filter the output and
as the following equation :
supply the load transient current. The filtering requirements
IRMS = IOUT ⋅ D ⋅ (1 - D)
are the functions of the switching frequency and the
(A)
ripple current. The output ripple is the sum of the
For a through hole design, several electrolytic capacitors
voltages, having phase shift, across the ESR and the
may be needed. For surface mount designs, solid
ideal output capacitor. The peak-to-peak voltage of
tantalum capacitors can be used, but caution must
the ESR is calculated as the following equations :
be exercised with regard to the capacitor surge current
V OUT = D ⋅ V IN
V OUT ⋅ (1 - D)
∆I =
F OSC ⋅ L
V ESR = ∆ I ⋅ ESR
rating.
V IN
IQ1
UGATE
CIN
(V) .......... ..(3)
is calculated as the following equation :
IOUT
∆ V COUT =
V OUT
L
Q2
(A) .......... .(2)
The peak-to-peak voltage of the ideal output capacitor
Q1
IL
LGATE
(V) .......... . (1)
ICOUT
ESR
∆I
(V) ....... (4)
8 ⋅ F OSC ⋅ C OUT
For general applications using bulk capacitors, the
∆V COUT is much smaller than the VESR and can be
COUT
ignored. Therefore, the AC peak-to-peak output voltage is shown below:
∆ V OUT = ∆ I ⋅ ESR
(V) .......... .(5)
The load transient requirements are the functions of
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
14
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APW7120
Application Information (Cont.)
Output Capacitor Selection (Cont.)
to a load transient is the time required to change the
the slew rate (di/dt) and the magnitude of the transient
inductor current. Given a sufficiently fast control loop
load current. These requirements are generally met
design, the APW7120 will provide either 0% or 85%
with a mix of capacitors and careful layout. Modern
(Average) duty cycle in response to a load transient.
components and loads are capable of producing
The response time is the time required to slew the
transient load rates above 1A/ns. High frequency
inductor current from an initial current value to the
capacitors initially supply the transient and slow the
transient current level. During this interval, the difference
current load rate seen by the bulk capacitors. The bulk
between the inductor current and the transient current
filter capacitor values are generally determined by the
level must be supplied by the output capacitor.
ESR (Effective Series Resistance) and voltage rating
Minimizing the response time can minimize the output
requirements rather than actual capacitance
capacitance required.
requirements.
The response time to a transient is different for the
High frequency decoupling capacitors should be placed
application of load and the removal of load. The fol-
as close to the power pins of the load as physically
lowing equations give the approximate response time
possible. Be careful not to add inductance in the
interval for application and removal of a transient load:
circuit board wiring that could cancel the usefulness
size perform better than a single large case capacitor.
L ⋅ ITRAN
L ⋅ ITRAN
, tFALL =
V IN − V OUT
V OUT
where: ITRAN is the transient load current step, tRISE is
the response time to the application of load, and tFALL
is the response time to the removal of load. The worst
case response time can be either at the application or
removal of load. Be sure to check both of these
equations at the transient load current. These requirements
are minimum and maximum output levels for the worst
case response time.
Output Inductor Selection
MOSFET Selection
The output inductor is selected to meet the output
The APW 7120 requires two N-Channel power
voltage ripple requirements and minimize the
MOSFETs. These should be selected based upon
converter’s response time to the load transient. The
R DS(ON), gate supply requirements, and thermal
inductor value determines the converter’s ripple
management requirements.
current and the ripple voltage, see equations (2) and
In high-current applications, the MOSFET power
(5). Increasing the value of inductance reduces the
dissipation, package selection, and heatsink are the
ripple current and voltage. However, the large inductance
dominant design factors. The power dissipation includes
values reduce the converter’s response time to a load
two loss components, conduction loss, and switching
transient.
loss. The conduction losses are the largest component
One of the parameters limiting the converter’s response
of power dissipation for both the high-side and the
tRISE =
of these low inductance components.
An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in
larger case sizes. However, the Equivalent Series
Inductance (ESL) of these capacitors increases with
case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. In most
cases, multiple electrolytic capacitors of small case
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
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APW7120
Application Information (Cont.)
VIN
MOSFET Selection (Cont.)
low-side MOSFETs. These losses are distributed
APW7120
between the two MOSFETs according to duty factor
UGATE
L
VOSC=1.6V
VOUT
VPHASE
(see the equations below). Only the high-side MOSFET
has switching losses, since the low-side MOSFETs
R VO
Driver
body diode or an external Schottky rectifier across
LGATE
the lower MOSFET clamps the switching node before
C
VCOMP
the synchronous rectifier turns on. These equations
VFB
FB
assume linear voltage-current transitions and do not
Internal
Compensation
Network
adequately model power loss due the reverse-recovery
R1
R2
0.8V
of the low-side MOSFET’s body diode. The gatecharge losses are dissipated by the APW7120 and
Figure 2. APW7120 Control System
don’t heat the MOSFETs. However, large gate-charge
The transfer functions are defined as following :
increases the switching interval, tSW which increases
the high-side MOSFET switching losses. Ensure that
both MOSFETs are within their maximum junction
A1(S) =
VFB(S)
R2
=
VO(S) R1 + R2
A2(S) =
VCOMP(S)
(Internal Compensation)
VFB(S)
A3(S) =
VPHASE(S)
VIN
=
VCOMP(S) ∆VOSC
A4(S) =
VOUT(S)
R ⋅C⋅S +1
=
VPHASE(S) L ⋅ C ⋅ S2 + R ⋅ C ⋅ S + 1
temperature at high ambient temperature by calculating
the temperature rise according to package thermalresistance specifications. A separate heatsink may
be necessary depending upon MOSFET power,
package type, ambient temperature, and air flow.
1
PHigh - Side = IOUT ⋅ RDSON ⋅ D + ⋅ IOUT ⋅ VIN ⋅ tSW ⋅ FOSC
2
2
PLow - Side = IOUT ⋅ RDSON ⋅ (1 - D)
2
VOUT(S)
VO(S)
VFB(S) VCOMP(S) VPHASE(S) VOUT(S)
=
⋅
⋅
⋅
VO(S)
VFB(S)
VCOMP(S) VPHASE(S)
= A1(S) ⋅ A2(S) ⋅ A3(S) ⋅ A4(S)
ACL(S) =
Where : tSW is the switching interval
Feedback Compensation
The figure 2 shows the control system of the
where A1(S) is the transfer function of the resistor-
APW7120, which consists of an internal voltage-mode
divider, A2(S) is the transfer function of the feedback
PWM modulator, an output L-C filter, a resistor-divider
compensation network, A3(S) is the transfer function
and an internal compensation network. The R and C
of the PWM modulator, A4(S) is the transfer function
are the equivalent series resistance(ESR) and capaci-
of the output LC filter, and ACL(S) is the transfer func-
tance of the output capacitor; the L is the inductance
tion of the closed-loop control system. Refer to figure
of the output inductor.
3. The Pole and Zero frequencies of the A1(S), A2(S),
A3(S) and ACL(S) are shown or calculated as the following equations:
FZA21 = 0.4kHz
F PA41,2 =
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
16
(FZ)
1
2 π x LC
FPA21 = 430kHz
F ZA41
(FP2)
1
=
2 π xRxC
www.anpec.com.tw
APW7120
Application Information (Cont.)
Feedback Compensation (Cont.)
Layout Consideration
where the FPA21 (or FP2) and FZA21 (or Fz) are the Pole
In high power switching regulator, a correct layout is
and Zero frequencies of the A2(S), the FPA41,2, and FZA41
are the double-Pole and Zero frequencies of the A4
important to ensure proper operation of the regulator.
In general, interconnecting impedances should be
(S), the VIN is the input voltage of the PWM converter
minimized by using short and wide printed circuit
and the load resistance of the converter is very large.
traces. Signal and power grounds are to be kept sepa-
For good converter stability, the values of the L, C,
rating and finally combined using ground plane con-
and R must be selected to meet the following criteria:
struction or single point grounding. Figure 4 illustrates
1.Make sure the double-pole frequency(FPA41,2) of
the layout, with bold lines indicating high current
the output filter is bigger than the zero frequency
paths. Components along the bold lines should be
(FZA21) of the internal compensation network.
placed close together. Below is a checklist for your
2. The following equation must be true:
layout:
log(
1. Begin the layout by placing the power components
VIN
R2
1 L
) + log(
) − 2 ⋅ log( ⋅
) + 1.2 > 0
∆VOSC
R1 + R2
R C
first. Orient the power circuitry to chieve a clean
power flow path. If possible, make all the connections
3. The converter crossover frequency (FCO) must
on one side of the PCB with wide, copper filled
be in the range of 10%~30% of minimum FOSC of
areas.
2. Connect the ground of feedback divider directly
the converter. The FCO is calculated by using the
following equations:
to the GND pin of the IC using a dedicated ground
trace.
3. The VCC decoupling capacitor should be right
Gain at FZA41
20
10% FOSC_MIN ≤ FCO = 10
⋅ FZA41 ≤ 30% FOSC_MIN
VIN
R2
Gain at FZA41 = 20 ⋅ log(
) + 20 ⋅ log(
)
∆VOSC
R1 + R2
− 40 ⋅ log(
next to the VCC and GND pins. Capacitor CBOOT
should be connected as close to the BOOT and
PHASE pins as possible.
4. Minimize the length and increase the width of
1 L
⋅
) + 27
R C
4. The values of L, C, and R selected must meet
the trace between UGATE/LGATE and the gates of
the equations above over the operaing temperatu-
the MOSFETs to reduce the impedance driving the
re, voltage, and current ranges.
MOSFETs.
5. Use an dedicated trace to connect the R OCSET
100
and the Drain pad of the low-side MOSFET, Kevin
80
Gain (dB)
60
FZA21
connection , for accurate current sensing.
6. Keep the switching nodes (UGATE, LGATE, and
Compensation Gain
40
PHASE) away from sensitive small signal nodes
20
FPA21
0
F PA41,2
-20
FCO
since these nodes are fast moving signals. Therefore,
Converter Gain
keep tracing to these nodes as short as possible.
7. Place the decoupling ceramic capacitor CHF near
FZA41
-40
PWM &Filter Gain
-60
100
1K
10K
100K
1M
the Drain of the high-side MOSFET as close as
10M
possible. The bulk capacitors CIN are also placed
Frequency (f , Hz)
Figure 3. Converter Gain vs. Frequency
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
near the Drain.
17
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APW7120
Application Information (Cont.)
Layout Consideration (Cont.)
8. Place the Source of the high-side MOSFET and
the Drain of the low-side MOSFET as close as
possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.
9. Use a wide power ground plane, with low
impedance, to connect the CHF, CIN, COUT, Schottky
diode, and the Source of the low-side MOSFET
and to provide a low impedance path between the
components for large and high frequency switching currents.
C HF
VCC
BOOT
LGATE
5
1
VIN
CIN
+
4
APW7120
U
2
1UGATE
Q1
C OUT
Q2
PHASE 8
+
L1
VOUT
Figure 4. Recommended Layout Diagram
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
18
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APW7120
Package Information
SOP-8
D
E
E1
SEE VIEW A
h X 45
°
c
A
0.25
b
GAUGE PLANE
SEATING PLANE
A1
A2
e
L
VIEW A
S
Y
M
B
O
L
SOP-8
MILLIMETERS
MIN.
INCHES
MAX.
A
MIN.
MAX.
1.75
0.069
0.004
0.25
0.010
A1
0.10
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
e
0.049
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MS-012 AA.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
19
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APW7120
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
330.0±2.00 50 MIN.
SOP-8
T1
C
d
D
12.4+2.00 13.0+0.50 1.5 MIN.
-0.00
-0.20
P0
P1
P2
D0
D1
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
W
E1
20.2 MIN. 12.0±0.30 1.75±0.10
T
A0
B0
F
5.5±0.05
K0
0.6+0.00 6.40±0.20 5.20±0.20 2.10±0.20
-0.40
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOP-8
Tape & Reel
2500
Copyright ANPEC Electronics Corp.
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APW7120
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
Temperature
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 sec
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Time 25°C to Peak Temperature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
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APW7120
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
3
3
Package Thickness
Volume mm
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