APW7142

APW7142 3A, 12V, Synchronous-Rectified Buck Converter Features • • • • • • Wide Input Voltage from 4.3V to 14V Output Current up to 3A Adjustable Output Voltage from 0.8V to VIN - ± 2% System Accuracy 70mΩ Integrated Power MOSFETs High Efficiency up to 95% - Automatic Skip/PWM Mode Operation Current-Mode Operation - Easy Feedback Compensation - Stable with Low ESR Output Capacitors - Fast Load/Line Transient Response General Description The APW7142 is a 3A synchronous-rectified Buck converter with integrated 70m Ω p ower MOSFETs. The APW7142, designed with a current-mode control scheme, can convert wide input voltage of 4.3V to 14V to the output voltage adjustable from 0.8V to VIN to provide excellent output voltage regulation. For high efficiency over all load current range, the APW7142 is equipped with an automatic Skip/PWM mode operation. At light load, the IC operates in the Skip mode, which keeps a constant minimum inductor peak current, to reduce switching losses. At heavy load, the IC works in PWM mode, which inductor peak current is programmed by the COMP voltage, to provide high efficiency and excellent output voltage regulation. The APW7142 is also equipped with power-on-reset, soft-start, soft-stop, and whole protections (under-voltage, over-voltage, over-temperature, and current-limit) into a single package. In shutdown mode, the supply current drops below 3µA. This device, available in an 8-pin SOP-8 package, provides a very compact system solution with minimal external components and PCB area. 100 90 • • • • • • • • • • Power-On-Reset Monitoring Fixed 500kHz Switching Frequency in PWM Mode Built-In Digital Soft-Start and Soft-Stop Current-Limit Protection with Frequency Foldback 123% Over-Voltage Protection Hiccup-Mode 50% Under-Voltage Protection Over-Temperature Protection 100ns < 100ns -1 ~ VIN+1 - 5 ~ VIN+5 -0.3 ~ +0.3 -0.3 ~ VIN+0.3 -0.3 ~ 6 Internally Limited 150 -65 ~ 150 260 Unit V V V V V W o Parameter VIN Supply Voltage (VIN to AGND) LX to GND Voltage PGND to AGND Voltage EN to AGND Voltage FB, COMP to AGND Voltage PD TSTG TSDR Power Dissipation Maximum Junction Temperature Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds C C C o o Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Junction-to-Ambient Thermal Resistance in Free Air (Note 2) SOP-8 Typical Value 80 Unit o C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 2 www.anpec.com.tw APW7142 Recommended Operating Conditions (Note 3) Symbol VIN VOUT IOUT CIN COUT LOUT VIN Supply Voltage Converter Output Voltage Converter Output Current Converter Input Capacitor (MLCC) Converter Output Capacitor Effective Series Resistance Converter Output Inductor Resistance of the Feedback Resistor connected from FB to GND TA TJ Ambient Temperature Junction Temperature Parameter Range 4.3 ~ 14 0.8 ~ VIN 0~3 8 ~ 50 20 ~ 1000 0 ~ 60 1 ~ 22 1 ~ 20 -40 ~ 85 -40 ~ 125 Unit V V A µF µF mΩ µH kΩ o o C C Note 3: Refer to the Typical Application Circuits Electrical Characteristics Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol SUPPLY CURRENT IVIN IVIN_SD VIN Supply Current VIN Shutdown Supply Current VFB = VREF +50mV, VEN=3V, LX=NC VEN = 0V VIN rising 0.5 1.5 3 mA µA V V Parameter Test Conditions Min. APW7142 Typ. Max. Unit POWER-ON-RESET (POR) VOLTAGE THRESHOLD VIN POR Voltage Threshold VIN POR Hysteresis REFERENCE VOLTAGE VREF Reference Voltage Output Voltage Accuracy Line Regulation Load Regulation OSCILLATOR AND DUTY CYCLE FOSC Oscillator Frequency Foldback Frequency Maximum Converter’ Duty s TON_MIN Minimum Pulse Width of LX TJ = -40 ~ 125oC, VIN = 4.75 ~ 14V VOUT = 0V 450 500 80 99 150 550 kHz kHz % ns µA/V dB Regulated on FB pin TJ = 25 C, IOUT=10mA, VIN=12V IOUT=10mA~3A, VIN=4.75~14V VIN = 4.75V to 14V IOUT = 0.5A ~ 3A o 3.9 - 4.1 0.5 4.3 - -1.0 -2.0 - 0.8 +0.02 -0.04 +1.0 +2.0 - V % %/V %/A CURRENT-MODE PWM CONVERTER Gm Error Amplifier Transconductance VFB=VREF±50mV Error Amplifier DC Gain COMP = NC 200 80 - C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 3 www.anpec.com.tw APW7142 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter Test Conditions Min. CURRENT-MODE PWM CONVERTER (CONT.) Current-Sense to COMP Voltage Transresistance High-side Switch Resistance Low-side Switch Resistance PROTECTIONS ILIM VTH_UV VTH_OV High-Side Switch Current-Limit FB Under-Voltage Threshold FB Over-Voltage Threshold FB Under-Voltage Debounce TOTP Over-Temperature Trip Point Over-Temperature Hysteresis TD Dead-Time VLX = -0.7V Peak Current VFB falling VFB rising 4.0 45 118 5.5 50 123 1 150 40 20 7.0 55 128 A % % µs o APW7142 Typ. Max. Unit VIN = 5V, TJ=25°C VIN = 12V, TJ=25°C VIN = 5V, TJ=25°C VIN = 12V, TJ=25°C - 0.048 90 70 90 70 110 90 110 90 V/A mΩ mΩ C C o ns SOFT-START, SOFT-STOP, ENABLE AND INPUT CURRENTS TSS Soft-Start / Soft-Stop Interval EN Shutdown Voltage Threshold EN Enable Voltage Threshold High-Side Switch Leakage Current IFB IEN FB Pin Input Current EN Pin Input Current VEN = 0V ~ VIN VEN = 0V, VLX = 0V VEN falling 1.5 0.5 -100 -100 2 2.5 2.1 2 +100 +100 ms V V µA nA nA C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 4 www.anpec.com.tw APW7142 Typical Operating Characteristics (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH) Output Current vs. Efficiency 100 3.4 Output Voltage vs. Output Current Output Voltage, VOUT (V) 10 90 3.38 3.36 3.34 3.32 3.3 3.28 3.26 3.24 3.22 3.2 0 1 2 3 Efficiency (%) 80 70 60 50 40 30 20 10 0 0.001 VIN=12V, VOUT=5V, L1=6.8µF VIN=12V, VOUT=3.3V, L1=4.7µF VIN=5V, VOUT=3.3V, L1=2.2µF 0.01 0.1 1 Output Current, IOUT(A) Output Current, IOUT(A) Current Limit Level (Peak Current) vs. Junction Temperature 7 3.4 3.38 Output Voltage vs. Supply Voltage IOUT=500mA Current Limit Level, ILIM(A) Output Voltage, VOUT (V) -20 0 20 40 60 80 o 6.5 3.36 3.34 3.32 3.3 3.28 3.26 3.24 3.22 6 5.5 5 4.5 -40 3.2 100 120 140 4 6 8 10 12 14 Junction Temperature, TJ ( C) Supply Voltage, VIN (V) VIN Input Current vs. Supply Voltage 2.0 Reference Voltage vs. Junction Temperature 0.816 VFB=0.85V 1.5 0.812 Reference Voltage, VREF (V) VIN Input Current, I VIN(mA) 0.808 0.804 0.800 0.796 0.792 0.788 0.784 -50 -25 0 25 50 75 100 125 150 1.0 0.5 0.0 0 2 4 6 8 10 12 14 Supply Voltage, VIN (V) C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 5 Junction Temperature, TJ (oC) www.anpec.com.tw APW7142 Typical Operating Characteristics (Cont.) (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH) Oscillator Frequency vs. Junction Temperature 550 540 Oscillator Frequency, FOSC(kHz) 530 520 510 500 490 480 470 460 450 -50 -25 0 25 50 75 100 o 125 150 Junction Temperature, TJ ( C) C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 6 www.anpec.com.tw APW7142 Operating Waveforms (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH) Power On Power Off IOUT=3A VIN 1 IOUT=3A VIN 1 VOUT 2 IL1 3 CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 1ms/div VOUT 2 IL1 3 CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 10ms/div Enable IOUT=3A IOUT=3A Shutdown 1 VEN VEN 1 VOUT 2 IL1 3 3 2 VOUT IL1 CH1 : VEN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 1ms/div CH1 : VEN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1, 2A/div Time : 100µs/div C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 7 www.anpec.com.tw APW7142 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH) Short Circuit IOUT =3~7A 1 VLx Short Circuit VOUT is shorted to GND by a short wire VLX 1 VOUT 2 IL1 3 2 VOUT 3 IL1 CH1 : VLX , 10V/div CH2 : VOUT , 2V/div CH3 : IL1 , 5A/div Time : 20µs/div CH1 : VLX , 5V/div CH2 : VOUT , 200mV/div CH3 : IL1 , 5A/div Time : 5ms/div Load Transient Response IOUT= 50mA-> 3A ->50mA IOUT rising/falling time=10µs VOUT Load Transient Response IOUT= 0.5A-> 3A ->0.5A IOUT rising/falling time=10µs 1 VOUT 1 IL1 IL1 2 2 CH1 : VOUT , 200mV/div CH2 : IL1 , 2A/div Time : 100µs/div CH1 : VOUT , 100mV/div CH2 : IL1 , 2A/div Time : 100µs/div C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 8 www.anpec.com.tw APW7142 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH) Switching Waveform IOUT=0.2A VLX Switching Waveform VLX IOUT=3A 1 1 IL1 IL1 2 2 CH1 : VLX , 5V/div CH2 : IL1 , 2A/div Time : 1µs/div CH1 : VLX , 5V/div CH2 : IL1 , 2A/div Time : 1µs/div Line Transient VIN= 5~12V VIN VIN rising/falling time=20µs VIN Over Voltage Protection VOUT 1 VOUT 2 IL1 1 2 3 4 IL1 VLX 3 IOUT=-1A CH1 : VIN , 5V/div CH2 : VOUT , 50mV/div (Voffset=3.3V) CH3 : IL1 , 2A/div Time : 100µs/div CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : VLX , 5V/div CH4 : IL1 , 5A/div Time : 20µs/div C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 9 www.anpec.com.tw APW7142 Pin Description PIN NO. 1 NAME PGND Power Ground of the APW7142, which is the source of the N-channel power MOSFET. Connect this pin to system ground with lowest impedance. Power Input. VIN supplies the power (4.3V to 14V) to the control circuitry, gate drivers and step-down converter switches. Connecting a ceramic bypass capacitor and a suitably large capacitor between VIN and both of AGND and PGND eliminates switching noise and voltage ripple on the input to the IC. Ground of MOSFET Gate Drivers and Control Circuitry. Output feedback Input. The APW7142 senses the feedback voltage via FB and regulates the voltage at 0.8V. Connecting FB with a resistor-divider from the converter’ s output sets the output voltage from 0.8V to VIN. Output of the error amplifier. Connect a series RC network from the COMP to the GND to compensate the regulation control loop. In some cases, an additional capacitor from the COMP to the GND is required. Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. Connect this pin to the VIN if it is not used. Power Switching Output. LX is the junction of the high-side and low-side power MOSFETs to supply power to the output LC filter. FUNCTION 2 3 4 VIN AGND FB 5 6 7, 8 COMP EN LX Block Diagram VIN Current Sense Amplifier Power-OnReset Current Limit Zero-Crossing Comparator VIN POR OVP 123%VREF 50%VREF UVP Soft-Start / Soft-Stop UG Soft-Start / Soft-Stop and Fault Logic Inhibit Gate Control VIN LG Current Compartor Slope Compensation Gate Driver Gate Driver LX FB VREF Gm Error Amplifier COMP PGND EN 1.5V Enable Over Temperature Protection FB Oscillator 500kHz AGND C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 10 www.anpec.com.tw APW7142 Typical Application Circuits 1. 4.3~14V Single Power Input Step-Down Converter (with a Ceramic Output Capacitor) VIN 2 VIN Enable 6 Shutdown C1 L1 EN VOUT C2 R1 ± 1% LX 8 U1 LX 7 APW7142 PGND 1 5 COMP FB AGND 3 4 R2 ± 1% R3 ± 5% C3 ± 30% C4 ± 30%, Optional a. Cost-effective Feedback Compensation (C4 is not connected) VIN(V) 12 12 12 12 12 12 12 12 5 5 5 5 VOUT(V) 5 5 3.3 3.3 2 2 1.2 1.2 3.3 3.3 1.2 1.2 L1(µH) 6.8 6.8 4.7 4.7 3.3 3.3 2.2 2.2 2.2 2.2 2.2 2.2 C2(µF) 22 44 22 44 22 44 22 44 22 44 22 44 C2 ESR(mΩ) 5 3 5 3 5 3 5 3 5 3 5 3 R1(kΩ) 63.0 63.0 46.9 46.9 30.0 30.0 7.5 7.5 46.9 46.9 7.5 7.5 R2(kΩ) 12 12 15 15 20 20 15 15 15 15 15 15 R3(kΩ) 10.0 20.0 10.0 22.0 10.0 20.0 8.2 16.0 8.2 20.0 3.0 7.5 C3(pF) 1500 1500 1500 1500 1500 1500 1800 1800 680 680 1800 1800 b. Fast-Transient-Response Feedback Compensation (C4 is connected) VIN(V) 12 12 12 12 12 12 12 12 5 5 5 5 VOUT(V) 5 5 3.3 3.3 2 2 1.2 1.2 3.3 3.3 1.2 1.2 L1(µH) 6.8 6.8 4.7 4.7 3.3 3.3 2.2 2.2 2.2 2.2 2.2 2.2 C2(µF) 22 44 22 44 22 44 22 44 22 44 22 44 C2 ESR(m Ω) 5 3 5 3 5 3 5 3 5 3 5 3 R1(kΩ ) 63.0 63.0 46.9 46.9 30.0 30.0 7.5 7.5 46.9 46.9 7.5 7.5 R2(kΩ ) 12 12 15 15 20 20 15 15 15 15 15 15 C4(pF) 47 47 47 47 47 47 150 150 56 56 330 330 R3(kΩ) 33.0 68.0 22.0 47.0 13.0 27.0 7.5 15.0 20.0 43.0 3.3 8.2 C3(pF) 470 470 680 680 1200 1200 2200 2200 220 220 1800 1500 C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 11 www.anpec.com.tw APW7142 Typical Application Circuits (Cont.) 2. +12V Single Power Input Step-Down Converter (with an Electrolytic Output Capacitor) 2 VIN Enable 6 Shutdown EN U1 APW7142 PGND 5 COMP FB AGND 3 8 LX LX 7 1 4 R2 15K ± 1% C1 2.2µF C5 470µF L1 4.7µH /3A VIN 12V VOUT 3.3V/3A C2 470µF (ESR=30mΩ) R3 62K ± 5% C3 680pF ± 30% R1 46.9K ± 1% C4 47pF ± 30% C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 12 www.anpec.com.tw APW7142 Function Description VIN Power-On-Reset (POR) The APW7142 keeps monitoring the voltage on VIN pin to prevent wrong logic operations which may occur when VIN voltage is not high enough for the internal control circuitry to operate. The VIN POR has a rising threshold of 4.1V (typical) with 0.5V of hysteresis. During startup, the VIN voltage must exceed the enable voltage threshold. Then, the IC starts a start-up process and ramps up the output voltage to the voltage target. Digital Soft-Start The APW7142 has a built-in digital soft-start to control the rise rate of the output voltage and limit the input current surge during start-up. During soft-start, an internal voltage ramp (VRAMP), connected to one of the positive inputs of the error amplifier, rises up from 0V to 0.95V to replace the reference voltage (0.8V) until the voltage ramp reaches the reference voltage. During soft-start without output over-voltage, the APW7142 converter’ sinking capability is disabled until the output s voltage reaches the voltage target. Digital Soft-Stop At the moment of shutdown controlled by EN signal, under-voltage event or over-temperature protection, the APW7142 initiates a digital soft-stop process to discharge the output voltage in the output capacitors. Certainly, the load current also discharges the output voltage. During soft-stop, the internal voltage ramp (VRAMP) falls down rises from 0.95V to 0V to replace the reference voltage. Therefore, the output voltage falls down slowly at the light load. After the soft-stop interval elapses, the softstop process ends and the the IC turns on the low-side power MOSFET. Output Under-Voltage Protection (UVP) In the operational process, if a short-circuit occurs, the output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the required regulation range. The under-voltage continually monitors the FB voltage after soft-start is completed. If a load step is strong enough to pull the output voltage lower than the under-voltage threshold, the IC shuts down converter’ output. s Enable/Shutdown Driving EN to the ground initiates a soft-stop process and then places the APW 7142 in shutdown. W hen in shutdown, after the soft-stop process is completed, the internal power MOSFETs turn off, all internal circuitry shuts down and the quiescent supply current reduces to less than 3µA. 13 www.anpec.com.tw The under-voltage threshold is 50% of the nominal output voltage. The under-voltage comparator has a built-in 2µs noise filter to prevent the chips from wrong UVP shutdown being caused by noise. The under-voltage protection works in a hiccup mode without latched shutdown. The IC will initiate a new soft-start process at the end of the preceding delay. Over-Voltage Protection (OVP) The over-voltage function monitors the output voltage by FB pin. When the FB voltage increases over 123% of the reference voltage due to the high-side MOSFET failure or for other reasons, the over-voltage protection comparator will force the low-side MOSFET gate driver high. This action actively pulls down the output voltage and eventually attempts to blow the internal bonding wires. As soon as the output voltage is within regulation, the OVP comparator is disengaged. The chip will restore its normal operation. This OVP scheme only clamps the voltage overshoot, and does not invert the output voltage when otherwise activated with a continuously high output from low-side MOSFET driver - a common problem for OVP schemes with a latch. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7142. When the junction temperature exceeds TJ = +150oC, a thermal sensor turns off the both power MOSFETs, allowing the devices to cool. The thermal sensor allows the converters to start a start-up process and to regulate the output voltage again after the junction temperature cools by 40oC. The OTP is designed with a 40 oC hysteresis to lower the average TJ d uring continuous thermal overload conditions, increasing lifetime of the APW7142. C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 APW7142 Function Description (Cont.) Current-Limit Protection The APW7142 monitors the output current, flows through the high-side power MOSFET, and limits the current peak at current-limit level to prevent loads and the IC from damaging during overload or short-circuit conditions. Frequency Foldback The foldback frequency is controlled by the FB voltage. When the output is shortened to the ground, the frequency of the oscillator will be reduced to 80kHz. This lower frequency allows the inductor current to safely discharge, thereby preventing current runaway. The oscillator’ fres quency will gradually increase to its designed rate when the feedback voltage on the FB again approaches 0.8V. C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 14 www.anpec.com.tw APW7142 Application Information Setting Output Voltage The regulated output voltage is determined by: VOUT = 0.8 × (1 + R1 ) R2 (V) T=1/FOSC VLX DT I Suggested R2 is in the range from 1k to 20kΩ . For portable applications, a 10k resistor is suggested for R2. To prevent stray pickup, please locate resistors R1 and R2 close to APW7142. Input Capacitor Selection Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed each time the P-channel power MOSFET (Q1) turns on. Place the small ceramic capacitors physically close to the VIN and between the VIN and the GND. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current (IRMS) of the bulk input capacitor is calculated as the following equation: IOUT IL IOUT IQ1 I ICOUT VOUT VOUT Figure 1 Converter Waveforms Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are the function of the switching frequency and the ripple current (∆I). The output ripple is the sum of the voltages, having phase shift, across the ESR, and the ideal output capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations: D= ∆I = VOUT VIN VOUT ·(1 - D) FOSC ·L IRMS= IOUT× D×(1- D) (A) ........... (1) where D is the duty cycle of the power MOSFET. For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. ........... (2) VESR = ∆I. ⋅ ESR ........... (3) The peak-to-peak voltage of the ideal output capacitor is VIN IQ1 Q1 VIN CIN calculated as the following equations: ∆VCOUT = ∆I (V) 8 ⋅ FOSC ⋅ COUT ........... (4) IL LX Q2 L IOUT VOUT ESR COUT For the applications using bulk capacitors, the ∆VCOUT is much smaller than the VESR and can be ignored. Therefore, the AC peak-to-peak output voltage (∆VOUT ) is shown as below: ∆VOUT = ∆ I ⋅ ESR (V) ICOUT ........... (5) C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 15 www.anpec.com.tw APW7142 Application Information (Cont.) Output Capacitor Selection (Cont.) For the applications using ceramic capacitors, the VESR is much smaller than the ∆ V COUT and can be ignored. Therefore, the AC peak-to-peak output voltage (∆VOUT ) is close to ∆VCOUT . The load transient requirements are the function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. An aluminum electrolytic capacitor’ ESR value is related to the case size with lower s ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to the high slew-rate transient loading. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies permit the use of a smaller inductor for the same amount of inductor ripple current. However, this is at the expense of efficiency due to an increase in MOSFET gate charge losses. The equation (2) shows that the inductance value has a direct effect on ripple current. Accepting larger values of ripple current allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆I ≤ 0.4x IOUT(MAX) . Remember, the maximum ripple current occurs at the maximum input voltage. The minimum inductance of the inductor is calculated by using the following equation: VOUT ·(VIN - VOUT) ≤ 1.2 500000 ·L ·VIN L≥ VOUT ·(VIN - VOUT ) 600000 ·VIN (H) Compensation Network + VIN - where VIN = VIN(MAX) Layout Consideration In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedance should be minimized by using short and wide printed circuit traces. Signal and power grounds are to be kept separating and finally combined using the ground plane construction or single point grounding. Figure 2 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: 1. Firstly, to initial the layout by placing the power components. Orient the power circuitry to achieve a clean power flow path. If possible, make all the connections on one side of the PCB with wide and copper filled areas. VIN LX LX 7 8 2 C1 L1 6 EN + C2 Load VOUT U1 APW7142 5 COMP PGND 1 4 R1 - R3 C3 AGND 3 FB R2 C4 (Optional) Feedback Divider 2. In Figure 2, the loops with same color bold lines conduct high slew rate current. These interconnecting impedances should be minimized by using wide and short printed circuit traces. 3. Keep the sensitive small signal nodes (FB, COMP) away from switching nodes (LX or others) on the PCB. Therefore place the feedback divider and the feedback compensation network close to the IC to avoid switching noise. Connect the ground of feedback divider directly to the AGND pin of the IC using a dedicated ground trace. ........... (6) 16 www.anpec.com.tw C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 APW7142 Application Information (Cont.) Layout Consideration (Cont.) 4. Place the decoupling ceramic capacitor C1 near the VIN as close as possible. Use a wide power ground plane to connect the C1 and C2 to provide a low impedance path between the components for large and high slew rate current. C2 C1 VIN 1 SOP-8 2 3 Ground 4 APW7142 Ground 8V LX 7 6 5 L1 VOUT Figure 3 Recommended Layout Diagram C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 17 www.anpec.com.tw APW7142 Package Information SOP-8 D SEE VIEW A E1 E e b h X 45 ° c A2 0.25 GAUGE PLANE SEATING PLANE L VIEW A SOP-8 INCHES MIN. MAX. S Y M B O L MILLIMETERS MIN. MAX. A A1 A2 b c D E E1 e h L 0 0.25 0.40 0° 0.10 1.25 0.31 0.17 4.80 5.80 3.80 1.27 BSC A1 A 1.75 0.25 0.004 0.049 0.51 0.25 5.00 6.20 4.00 0.012 0.007 0.189 0.228 0.150 0.050 BSC 0.50 1.27 8° 0.010 0.016 0° 0.069 0.010 0.020 0.010 0.197 0.244 0.157 0.020 0.050 8° Note: 1. Follow JEDEC MS-012 AA. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 18 www.anpec.com.tw APW7142 Carrier Tape & Reel Dimensions OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B d Application A 330.0± 2.00 H 50 MIN. P1 8.0± 0.10 H A T1 T1 12.4+2.00 -0.00 P2 2.0± 0.05 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 d 1.5 MIN. D1 1.5 MIN. D 20.2 MIN. T 0.6+0.00 -0.40 W 12.0± 0.30 A0 6.40± 0.20 E1 1.75± 0.10 B0 5.20± 0.20 W F 5.5± 0.05 K0 2.10± 0.20 (mm) SOP-8 P0 4.0± 0.10 Devices Per Unit Package Type SOP-8 Unit Tape & Reel Quantity 2500 C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 19 www.anpec.com.tw APW7142 Taping Direction Information SOP-8 USER DIRECTION OF FEED Classification Profile C opyright © A NPEC Electronics Corp. Rev. A.5 - Mar., 2009 20 www.anpec.com.tw APW7142 Classification Reflow Profiles Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time (tP)** within 5°C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25°C to peak temperature Sn-Pb Eutectic Assembly 100 °C 150 °C 60-120 seconds 3 °C/second max. 183 °C 60-150 seconds See Classification Temp in table 1 20** seconds 6 °C/second max. 6 minutes max. Pb-Free Assembly 150 °C 200 °C 60-120 seconds 3°C/second max. 217 °C 60-150 seconds See Classification Temp in table 2 30** seconds 6 °C/second max. 8 minutes max. * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness