APW7143KI-TRG

APW7143 3A, 12V, Asynchronous Buck Converter Features • • • • • • Wide Input Voltage from 4.3V to 14V Output Current up to 3A Adjustable Output Voltage from 0.8V to VIN - ± 2% System Accuracy 70mΩ Integrated Power MOSFET High Efficiency up to 92% - Automatic Skip/PWM Mode Operation Current-Mode Operation - Easy Feedback Compensation - Stable with Low ESR Output Capacitors - Fast Load/Line Transient Response General Description The APW7143 is a 3A asynchronous Buck converter with an integrated 70mΩ P -channel power MOSFET. The APW7143, designed with a current-mode control scheme, can convert wide input voltage of 4.3V to 14V to the output voltage adjustable from 0.8V to VIN to provide excellent output voltage regulation. For high efficiency over all load current range, the APW7143 is equipped with an automatic Skip/PWM mode operation. At light load, the IC operates in the Skip mode, which keeps a constant minimum inductor peak current, to reduce switching losses. At heavy load, the IC works in PWM mode, which inductor peak current is programmed by the COMP voltage, to provide high efficiency and excellent output voltage regulation. The APW7143 is also equipped with power-on-reset, soft-start, and whole protections (undervoltage, over temperature, and current-limit) into a single package. In shutdown mode, the supply current drops below 3µA. This device, available in an 8-pin SOP-8 package, provides a very compact system solution with minimal external components and PCB area. • • • • • • • • • Power-On-Reset Monitoring Fixed 500kHz Switching Frequency in PWM mode Built-in Digital Soft-Start Current-Limit Protection with Frequency Foldback Hiccup-Mode 50% Undervoltage Protection Over-Temperature Protection 100ns < 100ns -1 ~ VIN+1 - 5 ~ VIN+5 -0.3 ~ VIN+0.3 -0.3 ~ 6 150 -65 ~ 150 260 Unit V V V V o o o Parameter VIN Supply Voltage (VIN to AGND) LX to AGND Voltage EN to AGND Voltage FB, COMP to AGND Voltage Maximum Junction Temperature C TSTG TSDR Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds C C Note 2 : Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Thermal Characteristics Symbol θJA Parameter Junction-to-Ambient Thermal Resistance in Free Air (Note 3) o Value SOP-8 80 Unit C/W Note 3: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 2 www.anpec.com.tw APW7143 Recommended Operating Conditions (Note 4) Symbol VIN VOUT IOUT CIN COUT LOUT VIN Supply Voltage Converter Output Voltage Converter Output Current Converter Input Capacitor (MLCC) Converter Output Capacitor Effective Series Resistance Converter Output Inductor Resistance of the Feedback Resistor connected from FB to AGND TA TJ Ambient Temperature Junction Temperature Parameter Range 4.3 ~ 14 0.8 ~ VIN 0~3 8 ~ 50 20 ~ 1000 0 ~ 60 1 ~ 22 1 ~ 20 -40 ~ 85 -40 ~ 125 Unit V V A µF µF mΩ µH kΩ o o C C Note 4: Refer to the Typical Application Circuits Electrical Characteristics Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V, and TA= -40 ~ 85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol SUPPLY CURRENT IVIN IVIN_SD VIN Supply Current VIN Shutdown Supply Current VFB = VREF +50mV, VEN=3V, LX=NC VEN = 0V VIN rising 0.5 1.5 3 mA µA V V Parameter Test Conditions Min APW7143 Typ Max Unit POWER-ON-RESET (POR) VOLTAGE THRESHOLD VIN POR Voltage Threshold VIN POR Hysteresis REFERENCE VOLTAGE VREF Reference Voltage Output Voltage Accuracy Line Regulation Load Regulation OSCILLATOR AND DUTY CYCLE FOSC Oscillator Frequency Foldback Frequency Maximum Converter’ Duty s TON_MIN Minimum Pulse Width of LX TJ = -40 ~ 125oC, VIN = 4.75 ~ 14V VOUT = 0V 450 500 80 99 150 550 kHz kHz % ns µA/V dB Regulated on FB pin TJ = 25oC, IOUT=10mA, VIN=12V IOUT=10mA~3A, VIN=4.75~14V VIN = 4.75V to 14V IOUT = 0.5A ~ 3A -1.0 -2.0 0.8 +0.02 -0.04 +1.0 +2.0 V % %/V %/A 3.9 4.1 0.5 4.3 - CURRENT-MODE PWM CONVERTER Gm Error Amplifier Transconductance VFB=VREF±50mV Error Amplifier DC Gain COMP = NC 200 80 - C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 3 www.anpec.com.tw APW7143 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V, and TA= -40 ~ 85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter Current-Sense to COMP Voltage Transresistance P-Channel Switch Resistance PROTECTIONS ILIM VTH_UV P-Channel Switch Current-limit FB Under-Voltage Threshold FB Under-Voltage Debounce TOTP Over-Temperature Trip Point Over-Temperature Hysteresis SOFT-START, SOFTSTOP, ENABLE AND INPUT CURRENTS TSS Soft-Start LX Pull-Low Switch Resistance EN Shutdown Voltage Threshold EN Enable Voltage Threshold P-Channel Switch Leakage Current IFB IEN FB Pin Input Current EN Pin Input Current VEN = 0V ~ VIN VEN = 0V, VLX = 0V Switch is turned on for 2 ms (typ.) interval from the falling edge of enable signal. VEN falling 1.5 0.5 -100 -100 2 10 2.5 2.1 2 +100 +100 ms Ω V V µA nA nA Peak Current VFB falling 5.0 45 6.5 50 1 150 40 8.0 55 A % µs o Test Conditions Min VIN = 5V, TJ= 25°C VIN = 12V, TJ= 25°C - APW7143 Typ 0.06 90 70 Max 110 90 Unit V/A mΩ C C o C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 4 www.anpec.com.tw APW7143 Typical Operating Characteristics (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH ) Output Current vs. Efficiency 100 90 3.4 3.38 Output Voltage vs. Output Current Output Voltage, VOUT (V) Efficiency, (%) 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 10 VIN=12V, VOUT=3.3V, L1=4.7µH VIN=12V, VOUT=5V, L1=6.8µH VIN=5V, VOUT=3.3V, L1=2.2µH 3.36 3.34 3.32 3.3 3.28 3.26 3.24 3.22 3.2 0 1 2 3 Output Current, IOUT(A) Output Current, IOUT(A) Current-Limit Level (Peak Current) vs. Junction Temperature 7 Output Voltage vs. Input Voltage 3.4 3.38 Current Limit Level, ILIM(A) IOUT=500mA Output Voltage, VOUT (V) 6.5 3.36 3.34 3.32 3.3 3.28 3.26 3.24 3.22 6 5.5 5 4.5 -40 -20 0 20 40 60 80 o 3.2 100 120 140 4 6 8 10 12 14 Junction Temperature, TJ ( C) Input Voltage, VIN (V) VIN Input Current vs. Supply Voltage 2.0 Reference Voltage vs. Junction Temperature 0.816 VFB=0.85V 1.5 0.812 Reference Voltage, VREF (V) VIN Input Current, I VIN(mA) 0.808 0.804 0.800 0.796 0.792 0.788 0.784 -50 1.0 0.5 0.0 0 2 4 6 8 10 12 14 -25 0 25 50 75 100 125 150 Supply Voltage, VIN (V) C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 5 Junction Temperature, TJ (oC) www.anpec.com.tw APW7143 Typical Operating Characteristics (Cont.) (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH ) Oscillator Frequency vs. Junction Temperature 550 Oscillator Frequency, FOSC(KHz) 540 530 520 510 500 490 480 470 460 450 -50 -25 0 25 50 75 100 o 125 150 Junction Temperature, TJ ( C) Operating Waveforms (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH ) Power On IOUT=3A VIN 1 VOUT 2 IL1 3 2 1 Power Off IOUT=3A VIN VOUT 3 IL1 CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 5ms/div CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 10ms/div C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 6 www.anpec.com.tw APW7143 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH ) Enable IOUT=3A VEN 1 Shutdown IOUT=3A VEN 1 2 VOUT 2 IL1 VOUT IL1 3 3 CH1 : VEN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 1ms/div CH1 : VEN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1, 2A/div Time : 100µs/div Over Current IOUT =3~7A VLx Short Circuit VOUT is shorted to ground by a short wire VLX 1 VOUT 1 VOUT 2 IL1 2 IL1 3 3 CH1 : VLX , 10V/div CH2 : VOUT , 2V/div CH3 : IL1 , 5A/div Time : 20µs/div CH1 : VLX , 5V/div CH2 : VOUT , 200mV/div CH3 : IL1 , 5A/div Time : 5ms/div C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 7 www.anpec.com.tw APW7143 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH ) Load Transient Response IOUT= 50mA-> 3A ->50mA IOUT rising/falling time=10µs 1 VOUT 1 Load Transient Response IOUT= 0.5A-> 3A ->0.5A IOUT rising/falling time=10µs VOUT IL1 IL1 2 2 CH1 : VOUT , 200mV/div CH2 : IL1 , 2A/div Time : 100µs/div CH1 : VOUT , 100mV/div CH2 : IL1 , 2A/div Time : 100µs/div Switching Waveform IOUT=0.2A VLX Switching Waveform VLX IOUT=3A 1 1 IL1 IL1 2 2 CH1 : VLX , 5V/div CH2 : IL1 , 2A/div Time : 1µs/div CH1 : VLX , 5V/div CH2 : IL1 , 2A/div Time : 1µs/div C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 8 www.anpec.com.tw APW7143 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH ) Line Transient VIN= 5~12V VIN VIN rising/falling time=20µs 1 VOUT 2 IL1 3 CH1 : VIN , 5V/div CH2 : VOUT , 50mV/div (Voffset=3.3V) CH3 : IL1 , 2A/div Time : 100µs/div Pin Description PIN No. NAME FUNCTION Power Input. VIN supplies the power (4.3V to 14V) to the control circuitry, gate driver, and step-down converter switch. Connecting a ceramic bypass capacitor and a suitably large capacitor between VIN and AGND eliminates switching noise and voltage ripple on the input to the IC. No Connection. Ground of MOSFET Gate Driver and Control Circuitry. Output feedback Input. The APW7143 senses the feedback voltage via FB and regulates the voltage at 0.8V. Connecting FB with a resistor-divider from the converter’ s output sets the output voltage from 0.8V to VIN. Output of the error amplifier. Connect a series RC network from COMP to AGND to compensate the regulation control loop. In some cases, an additional capacitor from COMP to AGND is required. Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. Connect this pin to VIN if it is not used. Power Switching Output. LX is the Drain of the P-Channel power MOSFET to supply power to the output LC filter. 1 VIN 2 3 4 NC AGND FB 5 COMP 6 7, 8 EN LX C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 9 www.anpec.com.tw APW7143 Block Diagram VIN Current Sense Amplifier Power-OnReset Current Limit POR 50%VREF Soft-Start / Soft-Stop and Fault Logic Inhibit Gate Control UG Gate Driver UVP Soft-Start FB VREF Gm Error Amplifier Current Compartor Slope Compensation LX COMP EN 1.5V Enable Over Temperature Protection FB Oscillator 500kHz AGND Typical Application Circuits 1. +12V Single Power Input Step-down Converter (with an Electrolytic Output Capacitor) 2 VIN Enable 6 Shutdown 5 R3 62K C3 680pF AGND 3 8 LX EN U1 LX 7 APW7143 COMP FB 4 R2 15K ± 1% C1 2.2µF C5 470µF VIN 12V L1 4.7µH /3A VOUT 3.3V/3A C2 470µF (ESR=30mΩ) D1 R1 46.9K ± 1% C4 47pF C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 10 www.anpec.com.tw APW7143 Typical Application Circuits (Cont.) 2. 4.3~14V Single Power Input Step-down Converter(with ceramic Input/Output Capacitor) VIN 1 VIN Enable 6 Shutdown 5 R3 C3 AGND 3 EN U1 APW7143 COMP FB 4 R2 ± 1% C4 Optional C2 ESR(mΩ) 5 3 5 3 5 3 5 3 5 3 5 3 R1(kΩ) 63.0 63.0 46.9 46.9 30.0 30.0 7.5 7.5 46.9 46.9 7.5 7.5 R2(kΩ) 12 12 15 15 20 20 15 15 15 15 15 15 R3(kΩ) 10.0 20.0 10.0 22.0 10.0 20.0 8.2 16.0 8.2 20.0 3.0 7.5 C1 L1 8 LX LX 7 D1 R1 ± 1% C2 VOUT a. Cost-effective Feedback Compensation (C4 is not connected) VIN(V) 12 12 12 12 12 12 12 12 5 5 5 5 VOUT(V) 5 5 3.3 3.3 2 2 1.2 1.2 3.3 3.3 1.2 1.2 L1(µH) 6.8 6.8 4.7 4.7 3.3 3.3 2.2 2.2 2.2 2.2 2.2 2.2 C2(µF) 22 44 22 44 22 44 22 44 22 44 22 44 C3(pF) 1500 1500 1500 1500 1500 1500 1800 1800 680 680 1800 1800 b. Fast-Transient-Response Feedback Compensation (C4 is connected) VIN(V) 12 12 12 12 12 12 12 12 5 5 5 5 VOUT(V) 5 5 3.3 3.3 2 2 1.2 1.2 3.3 3.3 1.2 1.2 L1(µH) 6.8 6.8 4.7 4.7 3.3 3.3 2.2 2.2 2.2 2.2 2.2 2.2 C2(µF) 22 44 22 44 22 44 22 44 22 44 22 44 C2 ESR(m Ω) 5 3 5 3 5 3 5 3 5 3 5 3 R1(kΩ) 63.0 63.0 46.9 46.9 30.0 30.0 7.5 7.5 46.9 46.9 7.5 7.5 R2(kΩ) 12 12 15 15 20 20 15 15 15 15 15 15 C4(pF) 47 47 47 47 47 47 150 150 56 56 330 330 R3(kΩ) 33.0 68.0 22.0 47.0 13.0 27.0 7.5 15.0 20.0 43.0 3.3 8.2 C3(pF) 470 470 680 680 1200 1200 2200 2200 220 220 1800 1500 C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 11 www.anpec.com.tw APW7143 Function Description VIN Power-On-Reset (POR) The APW7143 keeps monitoring the voltage on VIN pin to prevent wrong logic operations which may occur when VIN voltage is not high enough for the internal control circuitry to operate. The VIN POR has a rising threshold of 4.1V (typical) with 0.5V of hysteresis. During start-up, the VIN voltage must exceed the enable voltage threshold. Then the IC starts a start-up process and ramps up the output voltage to the voltage target. Digital Soft-Start The APW7143 has a built-in digital soft-start to control the rise rate of the output voltage and limit the input current surge during start-up. During soft-start, an internal voltage ramp (VRAMP), connected to one of the positive inputs of the error amplifier, rises up from 0V to 0.95V to replace the reference voltage (0.8V) until the voltage ramp reaches the reference voltage. Output Undervoltage Protection (UVP) In the process of operation, if a short-circuit occurs, the output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the required regulation range. The undervoltage continually monitors the FB voltage after soft-start is completed. If a load step is strong enough to pull the output voltage lower than the undervoltage threshold, the IC shuts down converter’ output. s The undervoltage threshold is 50% of the nominal output voltage. The undervoltage comparator has a built-in 2µs noise filter to prevent the chips from wrong UVP shutdown caused by noise. The undervoltage protection works in a hiccup mode without latched shutdown. The IC will initiate a new soft-start process at the end of the preceding delay. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7143. When the junction temperature exceeds TJ = +150οC, a thermal sensor turns off the power MOSFET, allowing the devices to cool. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 40οC. The OTP is designed with a 40oC hysteresis to lower the average TJ during continuous therC opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 12 www.anpec.com.tw mal overload conditions, increasing lifetime of the APW7143. Enable/Shutdown Driving EN to ground places the APW7143 in shutdown. When in shutdown, the internal P-Channel power MOSFET turns off, all internal circuitry shuts down and the quiescent supply current reduces to less than 3µA. Current-Limit Protection The APW7143 monitors the output current, flows through the P-Channel power MOSFET, and limits the current peak at current-limit level to prevent loads and the IC from damages during overload or short-circuit conditions. Frequency Foldback The foldback frequency is controlled by the FB voltage. When the output is shorted to ground, the frequency of the oscillator will be reduced to about 80kHz. This lower frequency allows the inductor current to discharge safely and thereby prevent current runaway. The oscillator’ fres quency will gradually increase to its designed rate when the feedback voltage on FB again approaches 0.8V. APW7143 Application Information Setting Output Voltage The regulated output voltage is determined by: VOUT = 0.8 ⋅ (1 + R1 ) R2 VLX T=1/FOSC (V) IL DT I IOUT Suggested R2 is in the range from 1K to 20k Ω . For portable applications, a 10kΩ resistor is suggested for R2. To prevent stray pickup, locate resistors R1 and R2 close to APW7143. Input Capacitor Selection Each time, when the P-channel power MOSFET (Q1) turns on, small ceramic capacitors for high frequency decoupling and bulk capacitors are required to supply the surge current. The small ceramic capacitors have to be placed physically close to the VIN and between the VIN and the anode of the Schottky diode (D1). The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current (IRMS) of the bulk input capacitor is calculated as the following equation: IOUT IQ1 I ICOUT VOUT VOUT Figure 1 Converter Waveforms Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are the functions of the switching frequency and the ripple current (∆I). The output ripple is the sum of the voltages, having phase shift, across the ESR and the ideal output capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations: D= ∆I = VOUT + VD VIN + VD VOUT ·(1 - D) FOSC ·L ........... (1) ........... (2) (V) ........... (3) IRMS = IOUT ⋅ D ⋅ (1- D) (A) where D is the duty cycle of the power MOSFET. For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. VIN IQ1 Q1 VESR = ∆I ·ESR where VD is the forward voltage drop of the diode. The peak-to-peak voltage of the ideal output capacitor is calculated as the following equation: ∆VCOUT = ∆I (V) 8 ⋅ FOSC ⋅ COUT VIN CIN ........... (4) For the applications, using bulk capacitors, the ∆VCOUT is much smaller than the V ESR a nd can be ignored. VOUT LX L D1 IL ICOUT IOUT ESR COUT Therefore, the AC peak-to-peak output voltage (∆VOUT ) is shown below: ∆VOUT = ∆ I ⋅ ESR (V) ........... (5) C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 13 www.anpec.com.tw APW7143 Application Information (Cont.) Output Capacitor Selection (Cont.) For the applications, using ceramic capacitors, the VESR is much smaller than the ∆ V COUT and can be ignored. Therefore, the AC peak-to-peak output voltage (∆VOUT ) is close to ∆VCOUT . The load transient requirements are the functions of the slew rate (di/dt) and the magnitude of the transient load current. These requirements generally met with a mix of capacitors and careful layout. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed physically as close to the power pins of the load as possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. An aluminum electrolytic capacitor’ ESR value is related to the case size with lower s ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies permit the use of a smaller inductor for the same amount of inductor ripple current. However, this is at the expense of efficiency due to an increase in MOSFET gate charge losses. The equation (2) shows that the inductance value has a direct effect on ripple current. Accepting larger values of ripple current allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆I ≤ 0.4 ⋅ IOUT(MAX) . Remember, the maximum ripple current occurs at the maximum input voltage. The minimum inductance of the inductor is calculated as the following equation: Output Diode Selection The Schottky diode carries load current during the off-time. The average diode current is therefore dependent on the P-channel power MOSFET duty cycle. At high input voltages the diode conducts most of the time. As VIN approaches VOUT, the diode conducts only a small fraction of the time. The most stressful condition for the diode is when the output is short-circuited. Therefore, it is important to adequately specify the diode peak current and average power dissipation so as not to exceed the diode ratings. Under normal load conditions, the average current conducted by the diode is: ID = VIN - VOUT ⋅ IOUT VIN + VD VOUT ·(VIN - VOUT) ≤ 1.2 500000 ·L ·VIN L≥ VOUT ·(VIN - VOUT ) 600000 ·VIN (H) ........... (6) where VIN = VIN(MAX) The APW7143 is equipped with whole protections to reduce the power dissipation during short-circuit condition. Therefore, the maximum power dissipation of the diode is calculated from the maximum output current as: PDIODE(MAX) = VD ·ID(MAX) where IOUT = IOUT(MAX) Remember to keep leading length short and observing proper grounding to avoid ringing and increasing dissipation. C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 14 www.anpec.com.tw APW7143 Layout Consideration In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedance should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally combined using ground plane construction or single point grounding. Figure 2 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: 1. Begin the layout by placing the power components first. Orient the power circuitry to achieve a clean power flow path. If possible, make all the connections on one side of the PCB with wide, copper filled areas. 2. In Figure 2, the loops with same color bold lines conduct high slew rate current. These interconnecting impedances should be minimized by using wide and short printed circuit traces. 3. Keep the sensitive small signal nodes (FB, COMP) away from switching nodes (LX or others) on the PCB. Therefore, place the feedback divider and the feedback compensation network close to the IC to avoid switching noise. Connect the ground of feedback divider directly to the AGND pin of the IC using a dedicated ground trace. + VIN - 4. Place the decoupling ceramic capacitor C1 near the VIN as close as possible. The bulk capacitors C5 are also placed near VIN. Use a wide power ground plane to connect the C1, C2, C5, and Schottky diode to provide a low impedance path between the components for large and high slew rate current. C2 D1 C1 VIN 1 8 2 3 7 6 5 VLX VOUT L1 SOP-8 APW7143 Ground 4 Ground Figure 3 Recommended Layout Diagram 1 VIN 6 Compensat ion Network LX 8 LX 7 C1 L1 + D1 C2 Load V OUT EN U1 APW 7143 5 COMP R3 C3 AGND 3 FB 4 R2 R1 (Optional) Feedback Divider Figure 2 Current Path Diagram C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 15 www.anpec.com.tw APW7143 Package Information SOP-8 D SEE VIEW A E1 E e b h X 45 ° c A2 0.25 GAUGE PLANE SEATING PLANE L VIEW A SOP-8 INCHES MIN. MAX. S Y M B O L MILLIMETERS MIN. MAX. A A1 A2 b c D E E1 e h L 0 0.25 0.40 0° 0.10 1.25 0.31 0.17 4.80 5.80 3.80 1.27 BSC A1 A 1.75 0.25 0.004 0.049 0.51 0.25 5.00 6.20 4.00 0.012 0.007 0.189 0.228 0.150 0.050 BSC 0.50 1.27 8° 0.010 0.016 0° 0.069 0.010 0.020 0.010 0.197 0.244 0.157 0.020 0.050 8° Note: 1. Follow JEDEC MS-012 AA. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 16 www.anpec.com.tw APW7143 Carrier Tape & Reel Dimensions OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B d Application A H H A T1 T1 C d D W E1 W F 5.5± 0.05 K0 330.0± 2.00 50 MIN. SOP-8(P) P0 4.0± 0.10 P1 8.0± 0.10 12.4+2.00 13.0+0.50 1.5 MIN. -0.00 -0.20 P2 2.0± 0.05 D0 1.5+0.10 -0.00 D1 1.5 MIN. 0.30 1.75± 0.10 20.2 MIN. 12.0± T A0 B0 0.6+0.00 6.40± 0.20 5.20± 0.20 2.10± 0.20 -0.40 (mm) Devices Per Unit Package Type SOP-8 Unit Tape & Reel Quantity 2500 C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 17 www.anpec.com.tw APW7143 Reflow Condition TP Ramp-up TL Tsmax (IR/Convection or VPR Reflow) tp Critical Zone TL to TP Temperature tL Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds See table 2 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package. Measured on the body surface. 18 www.anpec.com.tw C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2008 APW7143 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 Package Thickness Volume mm