APW7237BTI-TRG

APW7237 1.5MHz, High Efficiency, Step-Up Converter with Internal FET Switch Features General Description • Wide 2.7V to 6V Input Voltage Range • Built-in 0.2Ω N-Channel MOSFET The APW7237 is a fixed switching frequency (1.5MHz typical), current-mode, step-up regulator with an inte- • Built-in Soft-Start • High Efficiency up to 90% • 1A->500mA Normal Operation 1 3 1, 2 2 3 4 VIN=3.3V, VOUT=5V CH1: VEN (5V/div) CH2: VOUT (2V/div) CH3: VLX (5V/div) CH4: IL (1A/div) Time: 1µs/div CH1: VOUT (2V/div) CH2: VLX (5V/div) CH3: IL (1A/div) Time: 500µs/div Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 VIN=3.3V, VOUT=5V 7 www.anpec.com.tw APW7237 Operating Waveforms EN Goes Low - Shutdown , Io=500mA EN Goes High- Enable, No Load 1 1 2 2 3 3 VIN=5V, VOUT=12V VIN=5V, VOUT=12V CH1: V EN (5V/div) CH2: V LX (10V/div) CH3: V OUT (5V/div) Time: 200µs/div CH1: VEN (5V/div) CH2: VLX (10V/div) CH3: VOUT (5V/div) Time: 500µs/div Load Transient, Io= 100mA->500mA->100mA Normal Operation 1 1 VIN=5V, VOUT=12V 2 2 3 3,4 4 CH1: VEN (5V/div) CH2: VOUT (5V/div) CH3: VLX (10V/div) CH4: IL (1A/div) Time: 500µs/div Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 VIN=5V, VOUT=12V CH1: VEN (5V/div) CH2: VOUT (2V/div) CH3: VLX (5V/div) CH4: IL (1A/div) Time: 1µs/div 8 www.anpec.com.tw APW7237 Block Diagram VIN UVLO EN LX Gate Driver Control Logic Over-Temperature Protection Slop Compensation Current Limit Current Sense Amplifier Σ Oscillator Error Amplifier ICMP GND FB COMP EAMP VREF 1.23V Soft-Start Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 9 www.anpec.com.tw APW7237 Typical Application Circuits VIN L1 VOUT 4.7µH 5V C1 4.7µF 12V VIN LX R1 1.2MΩ C2 4.7µF GND APW7237 ON EN OFF FB R2 137kΩ Figure 1. Typical 5V to 12V Supply VIN VOUT L1 2.2µH 3.3V C1 4.7µF 5V VIN LX R1 430kΩ C2 10µF GND APW7237 ON EN OFF FB R2 140kΩ Figure 2. Standard 3.3V to 5V Supply +13V C6 0.47µF +9V C4 0.47µF C5 C9 0.1µF 0.1µF C3 C7 0.1µF 0.1µF -8V C10 0.47µF -4V C8 0.47µF L1 VOUT 4.7µH 5V VIN C1 4.7µF VIN LX R1 430kΩ C2 10µF GND ON OFF APW7237 EN FB R2 140kΩ Figure 3. Multiple Output for TFT-LCD Power Supply Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 10 www.anpec.com.tw APW7237 Function Description Main Control Loop Over-Temperature Protection (OTP) The APW7237 is a constant frequency and current-mode The over-temperature circuit limits the junction tempera- switching regulator. In normal operation, the internal Nchannel power MOSFET is turned on each cycle when the ture of the APW7237. When the junction temperature exceeds 150 oC, a thermal sensor turns off the power oscillator sets an internal RS latch, and then turned off when an internal comparator (ICMP) resets the latch. The MOSFET allowing the devices to cool. The thermal sensor allows the converters to start a soft-start process and peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the COMP node which is regulates the output voltage again after the junction temperature cools by 40oC. The OTP is designed with a 40oC the output of the error amplifier (EAMP). An external resistive divider connected between VOUT and ground allows hysteresis to lower the average Junction Temperature (TJ) during continuous thermal overload conditions in- the EAMP to receive an output feedback voltage VFB at FB pin. When the load current increases, it causes a slightly creasing the lifetime of the device. Enable/Shutdown to decrease in VFB associated with the 1.23V reference, which in turn, it causes the COMP voltage to increase Driving EN to the ground places the APW7237 in shutdown mode. When in shutdown, the internal power MOSFET turns off, all internal circuitry shuts down, and until the average inductor current matches the new load current. the quiescent supply current reduces to 1µA maximum. VIN Under-Voltage Lockout (UVLO) The Under-Voltage Lockout (UVLO) circuit compares the input voltage at VIN with the UVLO threshold to ensure the input voltage is high enough for reliable operation. The 100mV (typ) hysteresis prevents supply transients from causing a restart. Once the input voltage exceeds the UVLO rising threshold, startup begins. When the input voltage falls below the UVLO falling threshold, the controller turns off the converter. Soft-Start The APW7237 has a built-in soft-start to control the output voltage rise during start-up. During soft-start, an internal ramp voltage, connected to the one of the positive inputs of the error amplifier, raises up to replace the reference voltage (1.23V typical) until the ramp voltage reaches the reference voltage. Current-Limit Protection The APW7237 monitors the inductor current, flows through the N-channel MOSFET, and limits the current peak at current-limit level to prevent loads and the APW7237 from damaging during overload or short-circuit conditions. Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 11 www.anpec.com.tw APW7237 Application Information Input Capacitor Selection The peak inductor current is calculated as the following equation: 1 V ⋅ (VOUT − VIN ) IPEAK = IIN(MAX ) + ⋅ IN 2 VOUT ⋅ L ⋅ FSW The input capacitor (CIN) reduces the ripple of the input current drawn from the input supply and reduces noise injection into the IC. The reflected ripple voltage will be smaller when an input capacitor with larger capacitance is used. For reliable operation, it is recommended to VIN select the capacitor with maximum voltage rating at least 1.2 times of the maximum input voltage. The capacitors IL IIN LX N-FET CIN IOUT D1 VOUT ESR ISW should be placed close to the VIN and the GND. COUT Inductor Selection IL Selecting an inductor with low dc resistance reduces conduction losses and achieves high efficiency. The efficiency ILIM is moderated whilst using small chip inductor which op- IPEAK ∆IL erates with higher inductor core losses. Therefore, it is necessary to take further consideration while choosing IIN an adequate inductor. Mainly, the inductor value determines the inductor ripple current: larger inductor value ISW results in smaller inductor ripple current and lower conduction losses of the converter. However, larger inductor value generates slower load transient response. A reasonable design rule is to set the ripple current, ∆IL, to be 30% to 50% of the maximum average inductor current, IL(AVG). The inductor value can be obtained as below, ID 2  V  VOUT − VIN η L ≥  IN  × ×  VOUT  FSW ⋅ IOUT(MAX )  ∆IL   IL (AVG )    where IOUT Output Capacitor Selection The current-mode control scheme of the APW7237 al- VIN = input voltage lows the usage of tiny ceramic capacitors. The higher capacitor value provides good load transients response. VOUT = output voltage FSW = switching frequency in MHz Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. If required, IOUT = maximum output current in amp. η = Efficiency tantalum capacitors may be used as well. The output ripple is the sum of the voltages across the ESR and the ideal ∆IL /IL(AVG) = inductor ripple current/average current output capacitor. (0.3 to 0.5 typical) To avoid the saturation of the inductor, the inductor should be rated at least for the maximum input current of the Δ VOUT = ΔVESR + ΔVCOUT ∆VCOUT ≈ converter plus the inductor ripple current. The maximum input current is calculated as below: IIN(MAX ) = V − VIN   ⋅  OUT   VOUT ⋅ FSW  ∆VESR ≈ IPEAK ⋅ RESR IOUT (MAX ) ⋅ VOUT VIN ⋅ η Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 IOUT COUT where IPEAK is the peak inductor current. 12 www.anpec.com.tw APW7237 Application Information (Cont.) Output Capacitor Selection (Cont.) 4. A star ground connection or ground plane minimizes ground shifts and noise is recommended. For ceramic capacitor application, the output voltage ripple is dominated by the ∆VCOUT. When choosing the input and output ceramic capacitors, the X5R or X7R with their good VOUT L1 D1 t e m p e r a t u r e an d v o l t a g e c h a r ac t e r i s t i c s a r e recommended. LX C1 C2 VIN The output voltage is set by a resistive divider. The external resistive divider is connected to the output which allows remote voltage sensing as shown in “Typical Application Circuits”. A suggestion of the maximum value of R2 R1 Output Voltage Setting VEN Optimized APW7237 Layout R1 is 2MΩ and R2 is 200kΩ for keeping the minimum current that provides enough noise rejection ability through the resistor divider. The output voltage can be calculated as below: R1  R1    VOUT = VREF ⋅ 1 +   = 1.23 ⋅ 1 + R2    R2  Diode Selection To achieve the high efficiency, a Schottky diode must be used. The current rating of the diode must meet the peak current rating of the converter. Layout Consideration For all switching power supplies, the layout is an important step in the design especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. The input capacitor should be placed close to the VIN and the GND without any via holes for good input voltage filtering. 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the LX pin to minimize the noise coupling into other circuits. 3. Since the feedback pin and network is a high impedance circuit the feedback network should be routed away from the inductor. The feedback pin and feedback network should be shielded with a ground plane or trace to minimize noise coupling into this circuit. Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 13 www.anpec.com.tw APW7237 Package Information TSOT-23-5A D e E E1 SEE VIEW A b c 0.25 A GAUGE PLANE SEATING PLANE A1 A2 e1 L VIEW A TSOT-23-5A S Y M B O L MIN. MAX. MIN. MAX. A 0.70 1.00 0.028 0.039 MILLIMETERS INCHES A1 0.01 0.10 0.000 0.004 A2 0.70 0.90 0.028 0.035 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 0.071 e 0.95 BSC 0.037 BSC e1 1.90BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Followed from JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 14 www.anpec.com.tw APW7237 Package Information TDFN2x2-6 A b E D D2 A1 A3 L K E2 Pin 1 Corner e TDFN2x2-6 S Y M B O L MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 MILLIMETERS A3 INCHES 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 1.90 2.10 0.075 0.083 D2 1.00 1.60 0.039 0.063 0.083 0.039 E 1.90 2.10 0.075 E2 0.60 1.00 0.024 0.45 0.012 e 0.65 BSC L 0.30 K 0.20 0.026 BSC 0.018 0.008 Note : 1. Followed from JEDEC MO-229 WCCC. Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 15 www.anpec.com.tw APW7237 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TSOT-23-5A Application TDFN2x2-6 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.20±0.20 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 2.35±0.20 2.35±0.20 1.00±0.20 4.0±0.10 4.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity TSOT-23-5A Tape & Reel 3000 TDFN2x2-6 Tape & Reel 3000 Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 16 www.anpec.com.tw APW7237 Taping Direction Information TSOT-23-5A USER DIRECTION OF FEED TDFN2x2-6 USER DIRECTION OF FEED Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 17 www.anpec.com.tw APW7237 Classification Profile Copyright  ANPEC Electronics Corp. Rev. A.4 - Dec., 2018 18 www.anpec.com.tw APW7237 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Volume mm Thickness