APW7261
3MHz Synchronous Switch-Mode Battery Charger with Full USB Compliance and USB-OTG Boost Regulator
Features
General Description
•
Charge Faster Than Linear Charger
The APW7261 combine switch-mode battery charger and
•
3MHz with Wide Duty Cycle Synchronous Switch-
a boost regulator with fixed 3MHz switching frequency,
which drives two integrated N-channel power MOSFETs.
Mode Charger with 1.5A Integrated N-MOSFETs
In battery charging, the high-efficiency step-down DC/DC
converter is capable of delivering 1.5A output current over
•
4V-6V Input Operating Range
•
20V Absolute Maximum Input Voltage
•
Safety
a wide input voltage range from 4V to 6V for APW7261, the
step-down DC/DC converter is ideally suited for portable
-Reverse leakage protection to prevent battery
drainage
electronic devices that are powered from 1-cell Li-ion
battery. The Charging parameters and operating modes
•
-Thermal regulation and protection
-Input/output over-voltage protection
can be programmed through an I 2C interface. The
APW7261 has high accuracy regulation of input current,
-Cycle-by-cycle current limit
Accuracy
charge current and charge voltage. It equipped with charge
termination, and charge status monitoring for battery
-+1% charge voltage regulation (0 to 85oC)
-+5% charge current regulation
detection.
The APW7261 charge the battery in three phases:
-+5% input current regulation (100mA and 500mA)
conditioning, constant current and constant voltage. The
APW7261 features Dynamic Power Management (DPM)
•
Built-In Input Current Sensing and Limiting
•
Automatic Charging
•
mode to accomplish input power limiting. The input current is limited to the value set by the I2C host. This feature
2
Programmable Through High-Speed I C Interface
reduces battery charge current when the input power limit
is reached to avoid overloading the AC adapter when sup-
(3.4Mb/s)
-Input Current Limit
-Fast-Charge and Termination Current
plying the load and the battery charger simultaneously.
The charge termination is based on battery voltage, a
-Charge Regulation Voltage
-VIN DPM Threshold
programmed minimum current level and charge current
termination bit set by the I2C host.
-Termination Enable/Disable
-OTG Enable/Disable
If the battery voltage falls below an internal threshold, the
APW7261 automatically restarts the charge cycle, and
-Reset All Parameter Control
-Safety Timer with Reset Control
•
when the input voltage falls below the battery voltage, it
will enter a low-quiescent current sleep mode. The
5V, 500mA Boost Mode for USB OTG for 2.5V to 4.
APW7261 supports the thermal regulation and over temperature protection to maintain the junction temperature
5V Battery Input
•
Available in 1.73mmx2.0mm WLCSP-20 Package
of 120oC by reducing charge current.
The APW7261 can operate as a boost regulator. To support USB OTG device, APW7261 can provide VBUS
(5.05V) by boosting the battery voltage.
The APW7261 is available in1.73mmx2.0mm WLCSP20 package.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
1
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APW7261
Applications
•
Cell Phones, Smart Phones and PDAs
•
Tablet PC
•
Portable Media Players, Handheld Device
Simplified Application Circuit
APW7261
To
SYSTEM
ADAPTER or USB
VBUS
CVBUS
LOUT
VBAT
RSNS
SW
PMID
CSNS
VAUX
REGN
BOOT
COUT1
10k
COUT2
PACK-
CSIN
CPMID
10k
PACK+
CBOOT
CPMID
10k
CSIN
SDA
CSOUT
SCL
CSOUT
STAT
OTG
CD
PGND
Ordering and Marking Information
Package Code
HA : WLCSP1.73x2.0-20
APW7261
Assembly Material
Operating Ambient Temperature Range
I : -40 to 85oC
Handling Code
Temperature Range
Handling Code
TR : Tape & Reel
Package Code
Assembly Material
G : Halogen and Lead Free Device
APW7261HA:
7261
• X
X - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
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APW7261
Pin Configuration
APW7261 Top View
VBUS
(A1)
VBUS
(A2)
BOOT
(A3)
SCL
(A4)
PMID
(B1)
PMID
(B2)
PMID
(B3)
SDA
(B4)
SW
(C1)
SW
(C2)
SW
(C3)
STAT
(C4)
PGND
(D1)
PGND
(D2)
PGND
(D3)
OTG
(D4)
CSIN
(E1)
CD
(E2)
REGN
(E3)
CSOUT
(E4)
1.73X2.0mm 20-pin WLCSP-20
Absolute Maximum Ratings (Note 1,2)
Symbol
VI/O
VBOOT
TJ
TSTG
TSDR
Rating
Unit
VBUS, PMID and STAT to PGND Voltage
Parameter
-0.3 to 20
V
BOOT and SW to PGND Voltage
-0.3 to 20
V
SCL, SDA, OTG, REGN, CSIN, CSOUT and CD to PGND Voltage
-0.3 to 7
V
BOOT Supply Voltage (BOOT to SW)
-0.3 ~ 7
Maximum Junction Temperature
Storage Temperature
Maximum Lead Soldering Temperature (10 Seconds)
V
150
o
-65 to 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Note 2: The device is ESD sensitive. Handling precautions are recommended.
Thermal Characteristics (Note 3)
Sym bol
θ JA
θ JC
P arame ter
Typical Value
Junction-to- Ambien t Resistance in free air
Junction-to- Ca se Resista nce i n free ai r
Unit
85
o
25
o
C/W
C/W
Note 3: θJA is measured with the component mounted on a high effective the thermal conductivity test board in free air.
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
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APW7261
Recommended Operating Conditions (Note 4)
S ymbol
VBUS
Parameter
Supply Voltage (VBUS to GND)
Range
Unit
4 to 6
V
VOUT
Converter Output Voltage
3.5 to 4.44
V
I OUT
Output Curren t (R SNS=68mΩ)
0.55~1.55
A
TA
Ambient Temperatu re
Junction Temperature
TJ
-40 to 85
o
-40 to 125
o
C
C
Note 4: Refer to the typical application circuit.
Electrical Characteristics
Unless otherwise specified, these specifications apply over VBUS=5V, CD=0, HZ_MODE=0, OPA_MODE=0 and TA= -40 to 85 oC.
Typical values are at TA=25oC.
APW7 261
Symbol
Pa ra mete r
Test Conditions
Min
Typ
M ax
Unit
-
10
-
mA
INPUT CURRENT
I VBUS
VBUS supp ly curre nt control
VBU S > V BUS(min), PWM switch ing
VBU S > V BUS(min), PWM n o switch ing
o
o
o
o
0 C < T J < 85 C, CD=1 or HZ_ MODE=1
I LKG
Leakag e cu rrent from batte ry to 0 C < T J < 85 C, VCSOUT =4.2V, High
VBUS pi n
Impeda nce Mo de, V BUS=0 V
o
-
-
5
mA
-
14 0
260
µA
-
0 .2
5
µA
-
23
50
µA
3.5
-
4 .4 4
V
-0.5
-
0.5
-1
-
1
55 0
-
15 00
mA
-
32 5
350
mA
o
Battery discharge cu rrent in High 0 C < T J < 85 C, VCSOUT =4.2V, High
Imp edan ce Mode , ( CSIN, CSOUT, Impeda nce Mo de, S CL, SDA, OTG=0V or
SW pins)
1.8V
VOLTAGE REGULATIO N
VOREG
Output Regul atio n vo lta ge
prog rammabl e ra nge
Op erating in voltage re gula tio n
o
Voltag e regul atio n accu racy
T A = 25 C
o
T A = -40 ~ 85 C
%
CURRENT REGULATION (FAS T CHARGE)
I O(CHARGE)
Output charge curre nt
VL OWV≦V CSOUTVSLP,
prog rammabl e ra nge
R SNS=68mΩ, LOW_CHG=0
Low ch arge curre nt
VL OWV≦V CSOUTVSLP,
R SNS=68mΩ, LOW_CHG=1
Charge Curr ent A ccu racy Across
20 mV < VIREG < 40m V
-8
-
2
%
R SN S
40 mV < VIREG
-6
-
0
%
-3.5
-
3.5
-3
-
3
-
-
3.7
Regula tio n accu racy of the voltag e 37 .4mV≦VIREG VOREG-V REGH, VBU S>VSL P, RSN S=68 mΩ
Deglitch time for ch arge
Bo th rising an d fallin g, 2mV overdrive, tRISE,
te rmination
t FALL =10 0ns
Regula tio n accu racy for
3.4mV≦ VIREG_TERM≦6.8mV
-2 5
-
25
te rmination curre nt across RS NS
6.8mV≦ VIREG_TERM≦17 mV
-2 5
-
25
VIREG_TER M=I OTERM x R SNS
17 mV≦V IR EG_TERM≦ 27.2mV
-5
-
5
4.2
-
4 .7 6
V
-3
-
3
%
88
93
98
%
INPUT BASED DYNAMIC P OWER MANAGEMENT
V IN _DPM
In put vol tag e DPM thresho ld
prog rammabl e ra nge
VIN DPM th reshold a ccura cy
INPUT CURRENT LIMIT
o
I IN=1 00mA
I IN_LIMIT
T A=25 C
In put cur rent lim itin g thre sh old
mA
o
I IN=5 00mA
T A=25 C
45 0
47 5
500
-
-
6.5
V
-
30
-
mA
-
12 0
-
mV
-
13 0
-
ms
I O=10mA , sink curr ent
-
-
0 .5 5
V
Voltage on S TAT pin is 5V
-
-
1
µA
-
0.4
V
0.4
V
VREF BIAS REGULATO R
VR EGN
In put bias r egula tor voltage
VBU S>VIN(mi n) or V CSOUT>VBUS(mi n), I REGN =1mA,
C REGN=1µF
VREGN output sh ort curre nt limit
BATTERY RECHARGE THRES HOLD
V RCH
Recharge thre sh old voltage
Deglitch time
Be low V OR EG
VC SOUT
decreasin g
be low
t FALL =10 0ns, 10m V o ve rdrive
thresho ld,
STAT OUTPUT
Low-level ou tp ut saturation
VOL(STAT)
vo lta ge, STAT p in
High-le ve l le akage curre nt for
STAT
2
I C BUS LOGIC LEVELS AND TIMING CHARACTERISTIC
VOL
Output low thre shold level
I O=10mA , sink curr ent
-
VIL
In put low thre sh old level
VPU LL_U P=1.8V, SDA and SCL
-
VIH
In put high threshol d l eve l
VPU LL_U P=1.8V, SDA and SCL
1.2
-
-
V
IBIAS
In put bias cur rent
VPU LL_U P=1.8V, SDA and SCL
-
-
1
µA
fSCL
SCL cl ock freque ncy
VPU LL_U P=1.8V, SDA and SCL
-
-
3.4
MHz
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
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APW7261
Electrical Characteristics
Unless otherwise specified, these specifications apply over VBUS=5V, CD=0, HZ_MODE=0, OPA_MODE=0 and TA= -40 to 85 oC.
Typical values are at TA=25oC.
APW7 261
Symbol
Param eter
Test Conditions
Unit
Min
Typ
M ax
-
-0.8
-
mA
-
26 2
-
ms
0
40
100
mV
14 0
20 0
260
mV
-
30
-
ms
3.6
3 .8
4
V
-
15 0
-
mV
-
90
135
Measur ed fr om P MID to SW, V BOOT -VSW =4V
-
13 0
225
Measur ed fr om SW to PGND
-
12 0
180
2.7
3
3.3
MHz
6.3
6 .5
6.7
V
-
17 0
-
mV
11 0
11 7
121
%
Lo we r l imit for VCSOUT fallin g from abo ve V OVP
-
11
-
%
Char ge mode op eration
3
4
5
A
1.9
2 .1
2.3
V
-
10 0
-
mV
BATTERY DETECTION (In Te rm ination)
I DETECT
t DETECT
B atte ry
de tection
curre nt
be fo re Be gins after termina tio n detected ,
cha rge don e (sink curre nt)
VC SOUT ≦ VOREG
B atte ry detection time
SLEE P COMPARATOR
V SLP
VSL P_EXIT
S LEE P mo de entry thre shold,
V BUS-VC SOUT
S leep mod e exit hyster esi s
Deg litch time fo r V BUS r isi ng above
V SLP+VSLP_EXIT
2.3V ≦VC SOUT ≦V OR EG, V BUS fall ing
2.3V ≦VC SOUT ≦V OR EG
Rising voltage, 2mV overdrive, tR ISE=100n s
UNDE RVOLTAG E LOCKOUT (UVLO)
UVL O
IC active th reshold voltage
UVLO_ HYS IC active hyster esis
VBU S risin g, E xit UVLO
VBU S falli ng below UVLO , Enter UVLO
PWM
Intern al top r eve rse blocki ng MOSFET I IN_LIMIT =500mA, Measure d from VBUS to
o n-resistance
PMID
Intern al top N-Cha nnel S witching
MOSFET o n-resistance
Intern al bottom N- Ch anne l MO SFET
o n-resistance
f OSC
O scil lator fre quency
mΩ
CHARGE M ODE PROTECTION
V OVP_IN_U SB
Inp ut VBUS OVP threshol d vol ta ge
V OVP_ IN_ USB hysteresis
VOVP
O utput OVP thresho ld vo lta ge
V OVP hyster esis
I ILIMIT
Cycle-by-cycle cur rent limit for
cha rge
VBU S thre sh old to turn off converter dur ing
char ge VOVP_IN_USB
VBUS fal ling fr om a bove VOVP_ IN _USB
VC SOUT th reshold over VOREG to turn off ch arger
du ring charg e
Trickle to fast char ge th reshold
VC SOUT rising
V SHORT hyste resis
VC SOU T fa lling be low V SHORT
V SHORT
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
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APW7261
Electrical Characteristics
Unless otherwise specified, these specifications apply over VBUS=5V, CD=0, HZ_MODE=0, OPA_MODE=0 and TA= -40 to 85 oC.
Typical values are at TA=25oC.
APW7 261
Symbol
Pa ra mete r
Test Conditions
Unit
Min
Typ
M ax
25
35
45
mA
4.9
5.05
5.2
V
Includi ng line an d lo ad regu lation
-3
-
3
%
Maxi mum o utput curr ent for boo st
VBU S_B=5 .0 5V, 2 .5V VSHORT.
loss and improve the converter efficiency.
In PFM Mode, the on-time pulse width is constant and
Cycle-by-Cycle Charge Mode Current Limit
The APW7261 monitors internal high-side MOSFET for
regulates off-time by zero crossing sensing.
current sensing. If the peak current exceeds the highside MOSFET limit threshold, it will turn off the high-side
VBUS Over-Voltage Protection
The IC provides a built-in over voltage protection to pro-
MOSFET until the next cycle. When the current is below
the over-current threshold, the high-side driver automati-
tect the device and other components against damage if
the VBUS voltage goes too high. When the VBUS OVP con-
cally resumes.
dition is detected, the IC turns off the PWM converter, sets
the STAT bit to “11”, FAULT bits to “001” and resets
BOOST MODE
BOOST mode can be enabled if OTG pin and OPA_MODE
bits as indicated in below table.
OTG _EN
OTG
PIN
OTG_PL
OPA_MO DE
BOO ST
1
HIG H
1
X
ENABLE
1
LOW
0
X
ENABLE
X
X
X
1
ENABLE
1
HIG H
0
0
DISABLE
1
LOW
1
0
DISABLE
0
X
X
0
DISABLE
OPA_MODE bit to 0. And then, APW7261 will return to
charge mode.
Battery Over-Voltage Protection
In Boost mode, the IC provides a built-in input over voltage protection to protect the device and other components against damage if the VBAT voltage goes too high.
When the VBAT OVP condition is detected, the IC turns off
the PWM converter, sets the STAT bit to “11” and resets
OPA_MODE bit to 0. And then, APW7261 will return to
charge mode.
The APW7261 operates in boost mode and delivers
power to VBUS from the battery. In normal boost mode,
Layout Consideration
the APW7261 converts the battery voltage (2.5V to 4.5V) to
VBUS (5V) and delivers a current IBO 500mA at lowest to
out is important to ensure proper operation of the
regulator. W ith power devices switching at higher
support other USB OTG devices connected to the USB
connector.
frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and
PWM Controller in BOOST Mode
parasitic circuit elements. As an example, consider the
turn-off transition of the PWM MOSFET. Before turn-off
In any high switching frequency converter, a correct lay-
In boost mode, the APW7261 provides an integrated, fixed
condition, the MOSFET is carrying the full load current.
During turn-off, current stops flowing in the MOSFET and
3-MHz frequency voltage-mode controller to regulate output voltage VBUS as the same as charge mode
is freewheeling by the lower MOSFET and parasitic diode.
Any parasitic inductance of the circuit generates a large
operation.
In boost mode, cycle-by-cycle current limit is sensed
voltage spike during the switching interval. In general,
using short and wide printed circuit traces should mini-
through the RSNS from CSIN to CSOUT. The peak current
limit threshold is equal to (0.12V/RSNS). For Example, if
mize interconnecting impedances and the magnitude of
voltage spike. And signal and power grounds are to be
RSNS=68mΩ, the peak current limit is about 1.76A. When
current limit event is triggered, IC will turn off Q3 driver. If
kept separating and finally combined to use the ground
plane construction or single point grounding if the above
current limit event is released, it will re-back normal
operation.
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
seperated pinout ground condirtions are satisfied.
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APW7261
Function Description (Cont.)
Layout Consideration (Cont.)
Top Layer
Below are Layout consideration checklist, recommended
layout Schematic diagram and demoboard layout for your
reference:
- Keep the switching nodes (BOOT and SW) away from
sensitive small signal nodes since these nodes are fast
moving signals. Therefore, keep traces to these nodes
as short as possible and there should be no other weak
signal traces in parallel with theses traces on any layer.
- The large layout plane between the drain of the MOSFETs
(VIN and SW nodes) can get better heat sinking.
- The sense resistor should be adjacent to the junction of
the inductor and output capacitor. Route the sense leads
connected across the RSNS back to the IC, close to each
other (minimize loop area) or on top of each other on
adjacent layers (do not route the sense leads through a
high-current path).
- The high-current charge paths into VBUS, PMID and
from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops
in these traces.
- Place all decoupling capacitors close to their respective
Bottom Layer
IC pins and close to PGND (do not place components
such that routing interrupts power stage currents). All
small control signals should be routed away from the
high current paths.
- The output bulk capacitors should be close to the loads.
The input capacitor’s ground should be close to the
grounds of the output capacitors.
APW7261
ADAPTER or USB
To
SYSTEM
40mil
VBUS
1µF
SW
PMID
40mil
1µH
68mΩ
PACK+
0.1µF
4.7µF
0.1µF
VAUX
VBAT
40mil
0.1µF
BOOT
CSIN
22µF
22µF
PACK-
0.1µF
10kΩ 10kΩ 10kΩ
CSOUT
SDA
SCL
VREF
STAT
SLRST
CD
1µF
PGND
Copyright ANPEC Electronics Corp.
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APW7261
I2C Introduction
I2C SERIAL CONTROL INTERFACE
The APW7261 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and supports
standard mode (100-kHz), fast mode (400-kHz) and the high-speed mode (up to 3.4Mbps in wire mode) data
transfer rates for single byte write and read operations. This is a slave only device that does not support a multimaster bus environment or wait state insertion. The control interface is used to program the registers of the device
and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum), the fast I2C bus operation (400 kHz
maximum) and the high-speed mode (up to 3.4Mbps in wire mode). The DAP performs all I2C operations without
I2C wait cycles.
General I2C Operation
The I2C bus uses two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system.
Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte (8-bit)
format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device
driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate a start and stop conditions. A highto-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions
must occur within the low time of the clock period. These conditions are shown in Figure 10. The master generates
the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for
an acknowledge condition. The APW7261 holds SDA low during the acknowledge clock period to indicate an
acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for
the SDA and SCL signals to set the high level for the bus.
SDA
7-Bit Slave Address
R/ A
W
7 6 5 4 3 2 1 0
8-Bit Register Address (N)
A
7 6 5 4 3 2 1 0
8-Bit Register Data for
Address (N)
7 6 5 4 3 2 1 0
A
8-Bit Register Data for
Address (N)
A
7 6 5 4 3 2 1 0
SCL
Start
Stop
2
Figure 10. Typical I C sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 10. Pin A_SEL defines the I2C device address. The device 7-bit address is defined as “1101010”
(6AH) for APW7261.
Copyright ANPEC Electronics Corp.
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APW7261
I2C Introduction
Single-Byte Transfer
The serial control interface supports single-byte read/write operations for sub-addresses 0x00 to 0xFF.
Supplying a sub-address for each sub-address transaction is referred to as random I2C addressing. The APW7261
also supports sequential I2C addressing. For write transactions, if a sub-address is issued followed by data for that
sub-address and the 15 sub-addresses that follow, a sequential I2C write transaction has taken place, and the data
for all 16 sub-addresses is successfully received by the APW7261. For I2C sequential write transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or start
is transmitted, determines how many sub-addresses are written. As was true for random addressing, sequential
addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last sub-address is discarded. However, all other data written is accepted; only the
incomplete data is discarded.
Single-Byte Write
As shown in Figure 11, a single-byte data write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I 2C device address and the
read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes
corresponding to the APW7261 internal memory address being accessed. After receiving the address byte, the
APW7261 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to
the memory address being accessed. After receiving the data byte, the APW7261 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0 R/W ACK A7
I2C Device Address and
Read/ Write Bit
Acknowledge
A6
A5
A4
A3
A2
A1
A0 ACK D7
Sub-address
Acknowledge
D6
D5
D4
D3
Data Byte
D2
D1
D0 ACK
Stop
Condition
Figure 11. Single-Byte Write Transfer
Single-Byte Read
As shown in Figure 12, a single-byte data read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read
are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be
read. As a result, the read/write bit becomes a 0. After receiving the APW7261 address and the read/write bit,
APW7261 responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes,
the master device transmits another start condition followed by the APW7261 address and the read/write bit again.
This time the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit,
the APW7261 again responds with an acknowledge bit. Next, the APW7261 transmits the data byte from the memory
address being read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop
condition to complete the single byte data read transfer.
Copyright ANPEC Electronics Corp.
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APW7261
I2C Introduction
Single-Byte Read (Cont.)
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
I2C Device Address and
Read/ Write Bit
Acknowledge
Acknowledge
A6
A1
A0 ACK
Sub-address
A6
Repeat Start
Condition
A5
A1
A0 R/W ACK D7
I2C Device Address and
Read/ Write Bit
Not Acknowledge
D6
D1
D0 ACK
Stop
Condition
Data Byte
Figure 12. Single-Byte Read Transfer
Register Description
The APW7261 has seven user-accessible registers. It is as defined as below table.
Re gist er Address
Nam e
Rea d/Write /Rea d Only Sta te
Default Va lue
00
Co ntrol/Status
Re ad/Write
X1 XX 0XXX
01
Control/Input Cu rrent Limit
Re ad/Write
0111 00 00
02
Control/Ba ttery Vo ltag e
Re ad/Write
00 00 101 0
03
Vende r/P art/Re vision
Read On ly
010X XXXX
04
Te rmination/Fast Charg e Cu rrent
Re ad/Write
00 00 000 1
05
Enab le/Sp ecial Charge r Vol tag e
Read/Write/Read Onl y
00 1X X10 0
06
Safety Limit
Re ad/Write
110 0 0000
The below tables define the operation of each register bit. Default values are in bold text.
Table1. Register Address: 00
Bit
Name
Data
Read/Write
Write
7
TMR_RST/OTG
Read
6
[5:4]
3
[2:0]
EN_STAT
S TAT
BOOS T
Description
Default Conditio n, write “0 ” or “ 1” has no effect ; If ca ll out 32sec timer,
Writing a 1 resets th e t 32 s timer
OTG pin sta tus. “0”=> OTG=Low; “1 ”=> O TG=Hig h
0
Read/Write
Disable STAT p in fun ction
1
Read/Write
Enable STAT pin function
00
Read
Ready
01
Read
Charge i n p rocess
10
Read
Charge d one
11
Read
Fault
0
Read
Not in boost mode
1
Read
In b oost mod e
00 0
Read
00 1
Read
01 0
Read
011
Read
FAULT
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
Charge mo de : Normal
Boo st mode : Norma l
Charge mo de : VBUS O VP
Boo st mode : VB US OVP
Charge mo de : Sle ep mode
Boo st mode : Over lo ad
Charge mo de : VBUS < UVLO
Boo st mode : VB AT < UVLO BST
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APW7261
Register Description
Bit
[2:0]
Name
Data
Read/Write
10 0
Read
10 1
Read
110
Read
111
Read
FAULT
Description
Charge mo de : Ba ttery OVP
Boo st mode : N/A
Charge mo de : Thermal Sh utd own
Boo st mode : Therma l Shutdown
Charge mo de : Time r fault
Boo st mode : Time r fau lt
Charge mo de : No batte ry
Boo st mode : N/A
Table2. Register Address: 01
Bit
[7:6]
[5:4]
3
2
1
0
Name
I IN_LIMIT
VLOWV
TE
CE
Data
Read/Write
De script ion
00
Read/Write
100mA
01
Read/Write
500mA
10
Read/Write
800mA
11
Read/Write
No Cur rent Limit
00
Read/Write
3.4V
01
Read/Write
3.5V
10
Read/Write
3.6V
11
Read/Write
3.7V
0
Read/Write
Disa ble charge current termination
1
Read/Write
Ena ble charge curr ent termin ati on
0
Read/Write
Cha rge enabled
1
Read/Write
Ch arge di sa bled
0
Read/Write
Not High-Impedance Mode
1
Read/Write
Hi gh-Imped ance Mode
0
Read/Write
Cha rge Mode
1
Read/Write
Boo st Mo de
HZ_MO DE
O PA_MODE
Copyright ANPEC Electronics Corp.
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APW7261
Register Description
Table3. Register Address: 02
Bit
[7:2]
Name
OREG
Data
Read/Write
Description
000000
Read/Write
3.5V
000001
Read/Write
3.52V
000010
Read/Write
3.54V
000011
Read/Write
3.56V
000100
Read/Write
3.58V
000101
Read/Write
3.6V
000110
Read/Write
3.62V
000111
Read/Write
3.64V
001000
Read/Write
3.66V
001001
Read/Write
3.68V
001010
Read/Write
3.7V
001011
Read/Write
3.72V
001100
Read/Write
3.74V
001101
Read/Write
3.76V
001110
Read/Write
3.78V
001111
Read/Write
3.8V
010000
Read/Write
3.82V
010001
Read/Write
3.84V
010010
Read/Write
3.86V
010011
Read/Write
3.88V
010100
Read/Write
3.9V
010101
Read/Write
3.92V
010110
Read/Write
3.94V
010111
Read/Write
3.96V
011000
Read/Write
3.98V
011001
Read/Write
4V
011010
Read/Write
4.02V
011011
Read/Write
4.04V
011100
Read/Write
4.06V
011101
Read/Write
4.08V
011110
Read/Write
4.1V
011111
Read/Write
4.12V
100000
Read/Write
4.14V
100001
Read/Write
4.16V
100010
Read/Write
4.18V
100011
Read/Write
4.2V
100100
Read/Write
4.22V
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APW7261
Register Description
Table3. Register Address: 02
Bit
[7:2]
1
0
Name
OREG
OTG_PL
OTG_EN
Data
Read/Write
Description
100100
Read/Write
4.22V
100101
Read/Write
4.24V
100110
Read/Write
4.26V
100111
Read/Write
4.28V
101000
Read/Write
4.3V
101001
Read/Write
4.32V
101010
Read/Write
4.34V
101011
Read/Write
4.36V
101100
Read/Write
4.38V
101101
Read/Write
4.4V
101110
Read/Write
4.42V
101111
Read/Write
4.44V
110000
Read/Write
4.44V
110001
Read/Write
4.44V
110010
Read/Write
4.44V
110011
Read/Write
4.44V
110100
Read/Write
4.44V
110101
Read/Write
4.44V
110110
Read/Write
4.44V
110111
Read/Write
4.44V
111000
Read/Write
4.44V
111001
Read/Write
4.44V
111010
Read/Write
4.44V
111011
Read/Write
4.44V
111100
Read/Write
4.44V
111101
Read/Write
4.44V
111110
Read/Write
4.44V
0
Read/Write
OTG pin active Low
1
Read/Write
OTG pin active High
0
Read/Write
OTG pin is disabled
1
Read/Write
OTG pin is enabled
Copyright ANPEC Electronics Corp.
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APW7261
Register Description
Table4. Register Address: 03
Read/Write
Des cription
Bit
Nam e
Data
[7 :5 ]
Ven der code
01 0
Re ad Only
[4 :3 ]
PN
XX
Re ad Only
For I C Ad dress
[2 :0 ]
REV
XXX
Re ad Only
IC Re visio n
2
Table5. Register Address: 04
Read/Write
Descripti on
Bit
Name
Data
7
Reserved
0
Read On ly
Unused
000
Read/Write
R SNS: 56mΩ=>668mA; RSNS: 68mΩ =>550mA ; RSNS: 100mΩ=>374mA
001
Read/Write
R SNS: 56mΩ=>789mA; RSNS: 68mΩ=>650mA ; RSNS: 100mΩ=>442mA
010
Read/Write
R SNS: 56mΩ=>911mA; R SNS: 68mΩ=>750mA ; RSNS: 100mΩ=>510mA
011
Read/Write
R SNS: 56mΩ=>1032mA; RSNS: 68mΩ=>850mA ; RSNS: 100mΩ =>578mA
100
Read/Write
R SNS:56mΩ=>1275mA; R SNS: 68mΩ=>1050mA ; R SNS: 100mΩ=>714mA
101
Read/Write
R SNS: 56mΩ=>1396mA; RSNS: 68mΩ=>1150mA ; RSNS: 100mΩ=>782mA
110
Read/Write
111
Read/Write
0
Read Only
Unused
000
Read/Write
R SNS: 56mΩ=>59mA; RSNS: 68mΩ=>49mA; R SNS: 100mΩ=>33mA
001
Read/Write
R SNS: 56mΩ=>118mA; R SNS: 68mΩ=>97mA; RSNS: 100mΩ=>66m A
010
Read/Write
R SNS: 56mΩ=>177mA; RSNS: 68mΩ=>146mA; R SNS: 100mΩ=>99mA
011
Read/Write
R SNS: 56mΩ=>236mA; RSNS: 68mΩ=>194mA; R SNS: 100mΩ=>132mA
100
Read/Write
R SNS: 56mΩ=>295mA; RSNS: 68mΩ=>243mA; R SNS: 100mΩ=>165mA
101
Read/Write
R SNS: 56mΩ=>353mA; RSNS: 68mΩ=>291mA; R SNS: 100mΩ=>198mA
110
Read/Write
R SNS: 56mΩ=>412mA; RSNS: 68mΩ=>340mA; R SNS: 100mΩ=>231mA
111
Read/Write
R SNS: 56mΩ=>471mA; RSNS: 68mΩ=>388mA; R SNS: 100mΩ=>264mA
[6:4]
3
[2:0]
IOCHARGE
Reserved
ITERM
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
R SNS: 56mΩ=>1639mA; RSNS: 68mΩ=>1350mA ; RSNS:
100mΩ=>918mA
R SNS:56mΩ=>1882mA; R SNS: 68mΩ=>1550mA ;
R SNS: 100mΩ=>1054mA
33
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APW7261
Register Description
Table6. Register Address: 05
Read/Write
Description
Bit
Name
Da ta
7
Reser ve d
0
Read Only
Unus ed
6
Reser ve d
0
Read/Write
Unus ed
0
Read/Write
Charge cur rent is controll ed by I OCH ARGE b its
5
IO_L EVEL
1
Read/Write
0
Read O nly
Special charg er is no t active
1
Read O nly
Special charg er is active and VBUS is b eing reg ulated to V SP
0
Read O nly
CD pi n is Low
1
Read O nly
CD pi n is High
000
Read/Write
VSP=4.213V
001
Read/Write
VSP=4.29V
010
Read/Write
VSP=4.373V
011
Read/Write
VSP=4.453V
100
Read/Write
VSP=4.533V
101
Read/Write
VSP=4.613V
110
Read/Write
VSP=4.693V
111
Read/Write
VSP=4.773V
4
3
[2:0]
SP
EN_LEVEL
VSP
Cha rge current is set to 395m A for R SNS: 56m Ω, 3 25m A for
R SNS: 68mΩ , 22 1mA for R SNS: 1 00mΩ
Table7. Register Address: 06
Bit
Name
7
Timer
Data
0
Re ad/Write
Call o ut 32sec tim er fun ction
Rea d/Write
1
[6:4]
Description
No 32se c t im er function
000
Rea d/Write
R SNS: 56mΩ=>6 68mA; R SNS: 6 8mΩ=>550 mA ; R SNS: 1 00mΩ=>3 74mA
001
Rea d/Write
R SNS: 56mΩ=>7 89mA; R SNS: 6 8mΩ=>650 mA ; R SNS: 1 00mΩ=>4 42mA
010
Rea d/Write
R SNS: 56mΩ=>9 11mA; R SNS: 68mΩ=>75 0mA ; R SNS: 100mΩ =>510mA
0 11
Rea d/Write
R SNS: 56mΩ=>1 032mA; R SNS: 68mΩ=>85 0mA ; R SNS: 100mΩ =>578mA
100
Rea d/Write
101
Rea d/Write
110
Rea d/Write
111
Rea d/Write
ISAFE
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
R SNS: 56 mΩ=>1 275mA; R SNS: 68 mΩ=>1 050mA ;
R SNS: 10 0mΩ =>714mA
R SNS: 56mΩ=>1 396mA; R SNS: 68mΩ=>1150mA ; R SNS:
1 00mΩ=>7 82mA
R SNS: 56mΩ=>1 639mA; R SNS: 68mΩ=>13 50mA ; RSN S:
1 00mΩ=>9 18mA
R SNS: 56mΩ=>1 882mA; R SNS: 68mΩ=>15 50mA ;
R SNS: 100mΩ =>1054mA
34
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APW7261
Register Description
Table6. Register Address: 06 (cont.)
[3:0]
VSAFE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
4.2V
4.22V
4.24V
4.26V
4.28V
4.3V
4.32V
4.34V
4.36V
4.38V
4.4V
4.42V
4.44V
4.44V
4.44V
4.44V
35
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APW7261
Package Information
E
WLCSP1.73x2.0-20
Pin 1
A2
D
A1
A
NX
aaa
c
e
e/2
SEATING PLANE
e
b
S
Y
M
B
O
L
WLCSP1.73*2.00-20
MILLIMETERS
MIN.
INCHES
MAX.
A
MIN.
MAX.
0.63
0.025
A1
0.15
0.19
0.006
0.007
A2
0.37
0.44
0.015
0.017
b
0.20
0.30
0.008
0.012
D
2.00
2.06
0.079
0.081
E
1.73
1.79
0.068
0.070
e
aaa
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
0.40 BSC
0.016 BSC
0.05
0.002
36
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APW7261
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
WLCSP(1.73X2.0)
A
H
T1
C
d
D
W
E1
F
1 78.0±2.00
50 MIN.
8.4 +2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
4 .0±0 .10
2.0±0.05
1 .5 +0.10
-0 .0 0
0.5 MIN.
0.6+0.0 0
-0.40
1 .9 8±0.10
2.31±0 .10
0.71±0.10
(mm)
Devices Per Unit
P acka ge Type
Unit
Quantity
WLCSP1 .73 x2.0-20
Ta pe & Reel
30 00
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
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APW7261
Taping Direction Information
WLCSP1.73x2.0-20
USER DIRECTION OF FEED
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
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APW7261
Classification Profile
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jun., 2016
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APW7261
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
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