APW8861
DDR3 AND DDR4 SYNCHRONOUS BUCK CONTVERTER
WITH 1.5A LDO
Features
General Description
Buck Controller (VDDQ)
The APW8861 integrates a synchronous buck PWM converter to generate VDDQ, a sourcing and sinking LDO
•
High Input Voltages Range from 4.5V to 26V Input
linear regulator to generate VTT. It offers the lowest total
solution cost in system where space is at a premium.
Power
•
Provide Adjustable Output Voltage from 0.75V to
3.3V
•
The APW8861 provides excellent transient response and
accurate DC voltage output in either PFM or PWM Mode.
Integrated MOSFET Drivers and Bootstrap Forward
P-CH MOSFET
•
Low Quiescent Current (200uA)
•
Excellent Load Transient Responses
•
PFM Mode for Increased Light Load Efficiency
•
Constant On-Time Controller Scheme
•
In Pulse Frequency Mode (PFM), the APW8861 provides
very high efficiency over light to heavy loads with loadingmodulated switching frequencies. On TQFN-32 Package,
the Forced PWM Mode works nearly at constant frequency
for low-noise requirements.
- Switching Frequency Compensation for PWM
The APW8861 is equipped with accurate current-limit,
Mode
- Adjustable Switching Frequency from 400kHz to
output under-voltage, and output over-voltage protections.
A Power-On- Reset function monitors the voltage on VCC
550kHz in PWM Mode with DC Output Current
prevents wrong operation during power on.
S3 and S5 Pins Control The Device in S0, S3 or S4/
The LDO is designed to provide a regulated voltage with
S5 State
•
Power Good Monitoring
•
70% Under-Voltage Protection (UVP)
•
125% Over-Voltage Protection (OVP)
•
Adjustable Current-Limit Protection
bi-directional output current for DDR-SDRAM termination.
The device integrates two power transistors to source
and sink current up to 1.5A. It also incorporates currentlimit and thermal shutdown protection.
The output voltage of LDO tracks the voltage at VREF pin.
An internal resistor divider is used to provide a half volt-
- Using Sense Low-Side MOSFET’s RDS(ON)
•
TQFN-32 4mmx4mm Thin package
•
Lead Free Available (RoHS Compliant)
age of VREF for VTTREF and VTT Voltage. The VTT output
voltage is only requiring 20µF of ceramic output capacitance for stability and fast transient response. The S3
and S5 pins provide the sleep state for VTT (S3 state)
+1.5A LDO Section (VTT)
•
Sourcing and Sinking Current up to 1.5A
•
Fast Transient Response for Output Voltage
•
Output Ceramic Capacitors Support at least 10µF
and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF.
MLCC
•
VTT and VTTREF Track at Half the VDDQSNS by
internal divider
•
+20mV Accuracy for VTT and VTTREF
•
Independent Over-Current Limit (OCL)
•
Thermal Shutdown Protection
Applications
•
DDR3 and DDR4 Memory Power Supplies
•
SSTL-2 SSTL-18 and HSTL Termination
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
1
www.anpec.com.tw
APW8861
Simplified Application Circuit
5V
VIN
+4.5V~26V
VCC
RCS
VDDQ
Vcc
CS
LOUT
PWM
DDR
LDO
VTT
VDDQ/2
S3 S5
Ordering and Marking Information
APW8861
Package Code
QB : TQFN4x4-32
Operating Ambient Temperature Range
I : -40 to 85oC
Handling Code
TR : Tape & Reel
Lead Free Code
G : Halogen and Lead Free Device
Lead Free Code
Handling Code
Temperature Range
Package Code
APW8861 QB :
APW8861
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
2
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APW8861
PHASE
PHASE
PHASE
VIN
PHASE
VIN
VIN
VIN
Pin Configuration
24 23 22 21 20 19 18 17
PHASE
25
NC
26
BOOT
27
14 PGND
LDOIN
28
13 PGND
VTT
29
16 PGND
VIN
15 PGND
PHASE
12 PGND
VTTGND 30
11 PGND
VTTGND
VTTSNS 31
32
1
2
3
4
5
6
7
8
VDDQSNS
FB
VTTGND
S3
S5
TON
PGOOD
9
VTTREF
GND
10 CS
VCC
Absolute Maximum Ratings (Note 1.2)
Pa rameter
Symbol
VCC
V BOOT
VBOOT-GND
Rating
Unit
V CC Sup ply Voltage (V CC to G ND)
-0.3 ~ 7
V
B OOT S upp ly Voltage (BOOT to PHASE)
-0.3 ~ 7
V
-0.3 ~ 3 5
V
-5 ~ 3 5
-0.3 ~ 2 8
V
-0.3 ~ 0.3
V
-0.3 ~ 7
V
B OOT S upp ly Voltage (BOOT to GND)
P HA SE Voltage (PHAS E to G ND)
100n s pu lse width
PGND, VTTGND and CS_ GND to GND Vol tag e
A ll O th er Pins (CS, S3, S 5, V TTSNS , VDDQSNS, VL DOIN, FB,
PGOOD, VTT, V TTREF GND)
Tj
Maximum Juncti on Temp erature
T STG
Storag e Tempe rature
T SDR
Maximum Sold ering Tempe rature, 1 0 Seconds
15 0
o
-65 ~ 1 50
o
26 0
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Note 2: The device is ESD sensitive. Handling precautions are recommended
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
3
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APW8861
Thermal Characteristics(Note 3)
Symbol
Parameter
Typical Value
Unit
θJA
Thermal Resistance -Junction to Ambient
48
°C/W
θJC
Thermal Resistance -Junction to Case
7
°C/W
Note3: θJA and θJC are measured with the component mounted on a high effective the thermal conductivity test board in free air. The
exposed pad of package is soldered directly on the PCB.
Recommended Operating Conditions
S ymbol
Range
Unit
VC C
VCC Su pply Vo ltag e
4.5 ~ 5.5
V
V IN
Co nve rte r Inp ut Voltage
4.5 ~ 2 6
V
0.7 5 ~3.3V
V
0.37 5 ~ 1.6 5
V
0~8
A
-1.5 ~ +1.5
A
1~
µF
2 0~5 0
µF
0 .0 33~0.1
µF
VVDD Q
Parame ter
Co nve rte r Output Vo ltag e
VVTT
L DO Output Vol tag e
I OUT
Co nve rte r Output Cu rrent
IVTT
L DO Output Cu rrent
C VCC
VCC Capacitance
C VTT
VTT Outpu t Capacita nce
CVTTREF
TA
TJ
VTTREF Output Capacitance
Ambient Temp erature
Ju nction Temper ature
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
4
-40 ~ 85
o
C
-4 0 ~ 125
o
C
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APW8861
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless
otherwise specified. Typical values are at TA=25oC.
Sym bol
Param eter
AP W886 1
Test Conditions
Unit
Min
Typ
Max
-
160
2 80
µA
-
120
1 75
µA
-
0.1
1
µA
SUP PLY CURRENT
I VC C
o
VCC S upp ly Curre nt
T A = 2 5 C, VS3 = V S5 = 5V, no load , VCC Cu rrent
VCC Standb y Curre nt
T A = 2 5 C, VS3 = 0 V, V S5 = 5V, no load, VCC
Current
o
I VC CSTB
I VC CSDN
VCC S hutdown Current
o
T A =25 C, V S3 = VS5 = 0V, no loa d
o
-
1
10
o
-
0.1
10
o
-
0.1
1
3 .9 5
4.1
4.4
V
-
0.1
-
V
VLD OIN = VVDD QSNS = 1.5V
-
0.75
VLD OIN = VVDD QSNS = 1.35 V
-
0.6 75
-
VLD OIN = VVDD QSNS = 1.2V
-
0.6
-
-20
-
20
-30
-
30
-20
-
20
-30
-
30
I LDOIN
LDOIN S uppl y Curren t
T A = 2 5 C, VS3 = V S5 = 5V, no load
I LDOIN STB
LDOIN Standb y Curre nt
T A = 2 5 C, VS3 = 0 V, V S5 = 5V, no load,
I LDOIN SDN LDOIN S hutdown Cu rrent
T A = 2 5 C, VS3 = V S5 = 0V, no load
µA
POWER-ON-RESET
VCC P OR Thr eshold
VCC Rising
VCC P OR Hyste resis
VTT OUTP UT
V VTT
VTT O utp ut Voltage
VLD OIN = VVDD QSNS = 1.5V , VVDDQSNS/2 - VVTT,
IVTT = 0 A
VLD OIN = VVDD QSNS = 1.5V , VVDDQSNS/2 - VVTT,
IVTT = 1 A
VLD OIN = VVDD QSNS = 1.35 V, VVD DQSNS/2 - VVTT,
IVTT = 0 A
V VTT
V
VTT O utp ut Tolera nce
VLD OIN = VVDD QSNS = 1.35 V, VVD DQSNS/2 - VVTT,
IVTT = 1 A
mV
VLD OIN = VVDD QSNS = 1.2V , VVDDQSNS/2 - VVTT,
-20
-
20
-30
-
30
25
30
35
T J=2 5 C
1.5
1.8
2.6
o
1.1
-
-
T J=2 5 C
-1.6
-1 .8
-2 .6
T J=1 25oC
-1.1
-
-
1.35
1.8
2.6
IVTT = 0 A
VLD OIN = VVDD QSNS = 1.2V , VVDDQSNS/2 - VVTT,
IVTT = 1 A
T SSVTT
VTT S oft Start time
S3 is go high to 0.95*VTT Regu lation
o
Sour cin g Cu rrent
(VLD OIN=1.5V)
T J=1 25 C
o
Sinking Curr ent
(VLD OIN=1.5V)
I LIM
Curren t-L imit
T J=2 5 C
o
T J=1 25 C
o
T J=2 5 C
Sinking Curr ent
(VLD OIN=1.35V)
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
A
o
Sour cin g Cu rrent
(VLD OIN=1.35V)
o
T J=1 25 C
5
us
1.1
-
-
-1.45
-1 .8
-2 .6
-1.1
-
-
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APW8861
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless
otherwise specified. Typical values are at TA=25oC.
Sym bol
Param eter
AP W886 1
Test Conditions
Unit
Min
Typ
Max
1.15
1.8
2.6
1.1
-
-
T J=25 C
-1.3
-1.8
-2.6
o
-1.1
-
-
Upper MOS FE T
-
3 50
5 00
Lower MOS FE T
-
3 50
5 00
-1.0
-
1.0
µA
-1.00
0.01
1.00
µA
15
25
-
mA
VLD OIN = VVDD QSNS = 1.5V, VVD DQSN S/2
-
0.75
-
VLD OIN = VVDD QSNS = 1.35V, V VDDQSNS/2
-
0 .6 75
-
VLD OIN = VVDD QSNS = 1.2V, VVD DQSN S/2
-
0.6
-
--20
-
20
-20
-
20
VTT OUTP UT
o
T J=25 C
Sour cin g Cu rrent
(VLD OIN=1.2V)
I LIM
o
T J=125 C
Curren t-L imit
Sinking Curr ent
(VLD OIN=1.2V)
R DS(ON )
I VTTLK
VTT P owe r MO SFETs R DS(ON)
VTT Le akage Curre nt
I VTTSNSLK VTTSNS Leakag e Cu rrent
A
o
T J=125 C
mΩ
VVTT = 1.25V, VS3 = 0 V, V S5 = 5V,
o
TA = 2 5 C
o
VVTT = 1.25V, T A = 2 5 C
o
I VTTDIS
VTT Discharge Curr ent
VVTT = 0.5V, VS3 = VS5 = 0 V, T A = 25 C
VVREF = 0V
VTTRE F O UTPUT
VVTTR EF
VTTREF Outp ut Voltage
-10mA < IVTTREF < 10 mA, VVD DQSN S/2 - VVTTR EF
VLD OIN = VVTTR EF =1.5V
VTTREF Toler ance
-10mA < IVTTREF < 10 mA, VVD DQSN S/2 - VVTTR EF
VLD OIN = VVDD QSNS = 1.35 V
V
mV
-10mA < IVTTREF < 10 mA, VVD DQSN S/2 - VVTTR EF
VLD OIN = VVDD QSNS = 1.2V
-20
-
20
I VTTREF
VTTREF So urce Curren t
VVTTR EF = 0V
-10
-2 0
- 50
mA
I VTTREF
VTTREF Si nk Curre nt
VVTTR EF = 1.5V
10
20
60
mA
0.745
0.75
0.757
V
0 .7 425
0.75
0 .7 595
V
-0.1
-
+0.1
%
-1
-
+1
%
VDDQ OUTPUT
T A = 2 5oC
o
o
T A = - 40 C to 85 C
VFB
FB Re gula tion Voltage
T A = 2 5oC,
VVCC = 4 .5V to 5.5V, VIN = 3V to 2 8V
o
T A = 2 5 C,
Load = 0 to 10A , VVC C = 4.5 V to 5.5V
FB Inp ut Curr ent
VDDQ Discha rge Curren t
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
-0.1
VFB= 0.78V
VS3 = VS5 = 0 V, V VDDQSNS = 0.5 V,
6
15
25
+0.1
µA
-
mA
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APW8861
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless
otherwise specified. Typical values are at TA=25oC.
Sym bol
Param eter
AP W886 1
Test Conditions
Unit
Min
Typ
Max
PWM CONTROLLE RS
F SW
Ope rating Frequ ency
Adju stabl e Fre quen cy
400
-
550
KHz
T SS
Internal So ft Sta rt Time
S5 is Hi gh to 0.9*VOUT Reg ulation
0.77
1.1
1 .4
ms
175
2 05
235
ns
T ONF
Fast on time
TOFF(MIN)
Minimum off time
T ON (MIN)
Slo w on time
VPHASE =1 9V, VOUT=1.5V,
R TON =6 20KΩ
Zero-Crossing Thresh old
-
3 00
-
ns
80
11 0
140
ns
-9.5
0.5
10.5
mV
15
16
17
µA
VDDQ PROTECTIONS
CS Pin Sink Curren t
o
TA = 2 5 C
Tempera tur e Co efficient,
On The Basis of 25 oC
OCP Comparator Offset
(VVCC – V CS) – (V PHASE – PGND),
VVCC – VC S = 6 0mV
VDDQ Curren t Limit S ettin g Ran ge VVCC -VCS
-
450 0
-
ppm/ o
C
-18
0
+1 8
mV
30
-
200
mV
120
1 25
130
%
-
1.5
-
µs
60
70
80
%
-
10
-
µs
VDDQ PROTECTIONS
VDDQ OVP Tr ip Thre sh old
VVDD Q Risin g
VDDQ OVP Debo unce Delay
VFB Rising, DV=1 0mV
VDDQ UVP Trip Threshol d
VVDD Q Falling
VDDQ UVP Deboun ce
PG OOD
PG OOD in fr om Lo we r ( PGOOD Goes High)
87
90
93
%
PG OOD in fr om High er (PGOOD Goes High)
120
1 25
130
%
-
0.1
1 .0
µA
2.5
7.5
-
mA
VPGOOD
PG OOD Th reshold
I PGOOD
PG OOD Leakag e Cu rrent
VPGOOD=5V
PG OOD Sink Curren t
VPGOOD=0.3V
-
63
-
µs
S5 is Hi gh to POK Ready
1.4
2
2 .6
ms
-
15
17
mΩ
-
8
11
mΩ
-
20
-
ns
PG OOD Debou nce Time
TSSPOK
PO K Soft Star t tim e
GATE DRIVE RS
R ON (H )
High Sid e N- MO SFET R DS(ON)
R ON(L)
Low Side N-MOSFET R DS(ON)
TD
Dead Time
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
(Note 4)
7
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APW8861
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85oC, unless
otherwise specified. Typical values are at TA=25oC.
Sym bol
Param eter
AP W886 1
Test Conditions
Unit
Min
Typ
Max
-
0.3
0 .5
V
VBOOT = 30V, VPHASE = 25V, VVC C=5V, T A = 25 C
-
-
0 .5
µA
2
-
-
V
BOOTSTRAP DIO DE
Forward Voltage
Reve rse Leakag e
VVCC – VBOOT , I F = 1 0mA, T A = 25oC
o
LOG IC THRESHOLD
VIH
S3, S5 High Thresho ld V oltage
S3, S5 Risi ng
V IL
S3, S5 Low Threshol d V oltage
S3, S5 Falling
-
-
0 .8
V
Logi c Input Leakag e Cu rrent
VS3 = VS5 = 5 V, T A =25 C
-1
-
1
µA
T J Rising
-
1 60
-
o
-
25
-
o
I ILEAK
o
THE RMAL SHUTDOWN
TS D
Thermal Shutdown Te mperature
Thermal Shutdown Hysteresis
C
C
Note 4: Guaranteed by design.
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
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APW8861
Pin Description
NO.
NAME
FUNCTION
1
VTTREF
2
VDDQSNS
VTTREF buffered reference output.
VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge current sinking
terminal for VDDQ non-tracking discharge.
3
FB
4
VTTGND
5
S3
S3 signal input.
6
S5
S5 signal input.
7
TON
8
PGOOD
9
VCC
10
CS
11~16
PGND
17~20, 25
PHASE
21~24
VIN
26
NC
27
BOOT
28
LDOIN
29
VTT
30
VTTGND
31
VTTSNS
32
GND
VDDQ output voltage setting pin.
Power ground output for the VTT LDO.
This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor RTON = 100KΩ ~ 600KΩ from
TON pin to PHASE pin.
Power-good output pin. PGOOD is an open drain output used to Indicate the status of the output
voltage. When VDDQ output voltage is within the target range, it is in high state.
5V power supply voltage input pin for both internal control circuitry and low-side MOSFET gate driver.
Over-current trip voltage setting input for RDS(ON) current sense scheme if connected to VCC through the
voltage setting resistor.
Power ground of the low-side MOSFET driver. Connect the pin to the Source of the low-side MOSFET.
Junction point of the high-side MOSFET Source, output filter inductor and the low-side MOSFET Drain.
Connect this pin to the Source of the high-side MOSFET. PHASE serves as the lower supply rail for the
high-side gate driver.
The pin is supply input, its supplies current to VDDQSNS.
Supply Input for the High-Side Gate Driver and an internal level-shift circuit. Connect to an external
capacitor and diode to create a boosted voltage suitable to drive a logic-level N-channel MOSFET.
Supply voltage input for the VTT LDO.
Power output for the VTT LDO.
Power ground output for the VTT LDO.
Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor.
Signal Ground.
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
9
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APW8861
Typical Operating Characteristics
Supply Current In S3 VS Temperature
250
200
225
175
200
Supply Current (uA)
Supply Current (uA)
Supply Current In S0 VS Temperature
175
150
125
100
75
150
125
100
75
50
50
25
25
0
-60 -40 -20
0
0
-60 -40 -20
20 40 60 80 100 120 140 160
20 40 60 80 100 120 140 160
0
Temperature(oC)
Temperature(oC)
Shutdown Current VS Temperature
On-Time VS Temperature
1.6
240
1.4
235
1.2
225
On-Time (ns)
Shutdown Current (uA)
230
1.0
0.8
0.6
220
215
210
205
200
0.4
195
190
0.2
185
0
-60 -40 -20
0
180
-60 -40 -20
20 40 60 80 100 120 140 160
Temperature (oC)
Reference Voltage VS Temperature
Efficiency VS Loading
100
755
95
754
753
90
752
85
Efficiency (%)
Reference Voltage (mV)
20 40 60 80 100 120 140 160
0
Temperature (oC)
751
750
749
80
75
70
748
65
747
60
746
55
745
-60 -40 -20
VDDQ=1.5V,L=1uH
- VIN=6V
- VIN=19V
1
7
50
0
20 40 60 80 100 120 140 160
0
Temperature (oC)
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
2
3
4
5
6
8
9
10
Loading (A)
10
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APW8861
Operating Waveforms
Enable S3 – No Load
Enable VCC - No Load
CH2
CH2
CH3
CH3
CH1
CH1
CH4
CH4
CH1:VS3-5V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:IL-5A/div
Time:20us/div
CH1:VCC-5V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:IL-10A/div
Time:1ms/div
OTP
POK- Enable S3/S5
CH1
CH2
CH3
CH2
CH4
CH3
CH1
CH1:VDDQ-1V/div
CH2:VTT-500mV/div
CH3:IL-5A/div
Time:200ms/div
CH1:POK-5V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:VS3/S5-5V/div
Time:1ms/div
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
11
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APW8861
Operating Waveforms (Cont.)
UVP
Normal Operaion
CH2
CH3
CH1
CH2
CH4
CH1
CH3
CH1:POK-5V/div
CH2:VDDQ-1V/div
CH3:VTT-500mV/div
CH4:IL-10A/div
Time:50us/div
CH1:VDDQ-500mV/div
CH2:VTT-500mV/div
CH3:IL-5A/div
Time:2us/div
Load Transient-Load=0.8A8A
OCP
CH1
CH2
CH1
CH2
CH3
CH1:Phase-20V/div
CH2:VDDQ-1V/div
CH3:IL-10A/div
Time:50us/div
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
CH1:VDDQ-50mV/div
CH2:IL-5A/div
Time:50us/div
12
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APW8861
Block Diagram
0.5 x VDDQ
VDDQSNS
VTTREF
LDOIN
Thermal
Shutdown
S3
Current Limit
S3,S5 Control Logic
VTT
S5
0.5 x VDDQ
+5/10%
VTTSNS
0.5 x VDDQ 5/10%
VTTGND
Non-Tracking
Discharge
VCC
VREF
0.75V
FB
Soft
Start
Voltage
Selector
VCC
POR
0.75V
VREF
Current
Limit
CS
16uA
125% x
VREF
BOOT
OV
Error
Comparator
VIN
UV
PWM
Signal
Controller
70% x VREF
TON
PHASE
TON
Generator
PHASE
VCC
ZC
VREF x
125%/122%
PGOOD
PGND
Delay
GND
VREF x 90%/87%
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
13
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APW8861
Typical Application Circuit
VIN
4.5V~26V
CBOOT
CIN
0.1uF
10uF x 2
LOUT
1uH
VDDQ
VDDQ
8A
COUT
22uF x4
(MLCC)
VIN
PHASE
BOOT
GND
LDOIN
CVTT
10uF x 2 to 5
VTT
VTT
VDDQ/2
VTTGND
PGND
VTTSNS
CS
RCS
12K, 1%
APW8861
VCC
RVCC
TQFN4x4-32
VTTREF
VDDQ/2
VCC
VTTREF
2.2
CVCC
1uF
PGOOD
TON
S5
S3
VDDQSNS
FB
CVTTREF
0.033uF
CPVCC
4.7uF
RPGOOD
PGOOD
RTON
VDDQ
RTOP
75K, 1%
100k
VIN or PHASE
RGND
75K, 1%
620K
Note 5: The VTT output ceramic capacitors is just recommend.
Adjustable Output Voltage Regulator for VDDQ
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
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APW8861
Function Description
The APW8861 integrates a synchronous buck PWM con-
which senses input voltage on PHASE pin, provides very
fast on-time response to input line transients.
troller to generate VDDQ, a sourcing and sinking LDO
linear regulator to generate VTT. It provides a complete
Another one-shot sets a minimum off-time (typical:
300ns). The on-time one-shot is triggered if the error com-
power supply for DDR3 and DDR4 memory system in a
32-pin TQFN package. User defined output voltage is
parator is high, the low-side switch current is below the
current-limit threshold, and the minimum off-time one-
also possible and can be adjustable from 0.75V to 3.3V.
Input voltage range of the PWM converter is 4.5V to 26V.
shot has timed out.
The converter runs an adaptive on-time PWM operation
at high-load condition and automatically reduces fre-
Power-On-Reset
A Power-On-Reset (POR) function is designed to prevent
wrong logic controls when the VCC voltage is low. The
quency to keep excellent efficiency down to several mA.
The VTT LDO can source and sink up to 1.5A peak cur-
POR function continually monitors the bias supply voltage on the VCC pin if at least one of the enable pins is set
rent with only 10µF ceramic output capacitor. VTTREF
tracks VDDQ/2 within 1% of VDDQ. VTT output tracks
high. When the rising VCC voltage reaches the rising
POR voltage threshold (4.1V typical), the POR signal goes
VTTREF within 20 mV at no load condition while 40 mV at
full load. The LDO input can be separated from VDDQ
high and the chip initiates soft-start operations. Should
this voltage drop lower than 4V (typical), the POR dis-
and optionally connected to a lower voltage by using
VLDOIN pin. This helps reducing power dissipation in
ables the chip.
sourcing phase. The APW8861 is fully compatible to
JEDEC DDR3/DDR4 specifications at S3/S5 sleep state
Soft- Start
The APW8861 integrates digital soft-start circuits to ramp
(see Table 1). When both VTT and VDDQ are disabled,
the non-tracking discharge mode discharges outputs
up the output voltage of the converter to the programmed
regulation set point at a predictable slew rate. The slew
using internal discharge MOSFETs that are connected to
VDDQSNS and VTT.
rate of output voltage is internally controlled to limit the
inrush current through the output capacitors during
Constant-On-Time PWM Controller with Input Feed-
softstart process. In addition, the VTT LDO provides a
softstart function, using the current limit method to charge
Forward
The constant on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This ar-
the output capacitor that gives a rapid output voltage rise.
The figure 1 shows VDDQ soft-start sequence. When the
chitecture relies on the output filter capacitor’s effective
series resistance (ESR) to act as a current-sense resistor,
S5 pin is pulled above the rising S5 threshold voltage,
the device initiates a soft-start process to ramp up the
so the output ripple voltage provides the PWM ramp signal.
In PFM operation, the high-side switch on-time controlled
output voltage. The soft-start interval is 1.2ms (typical)
and independent of the PHASE switching frequency.
by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input
2ms
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
VCC and VPVCC
1.2ms
a switching frequency control circuit in the on-time generator block. The switching frequency control circuit
VOUT
senses the switching frequency of the high-side switch
and keeps regulating it at a constant frequency in PWM
S5
mode. The design improves the frequency variation and
be more outstanding than a conventional constant ontime controller which has large switching frequency variation over input voltage, output current and temperature.
VPGOOD
Both in PFM and PWM, the on-time generator,
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
Figure 1. Soft-Start Sequence.
15
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APW8861
Function Description (Cont.)
During soft-start stage before the PGOOD pin is ready,
the under voltage protection is prohibited. The over volt-
Over Voltage Protection (OVP)
age and current limit protection functions are enabled. If
the output capacitor has residue voltage before startup,
reference voltage due to the high-side MOSFET failure or
for other reasons, and the over voltage protection com-
both low-side and high-side MOSFETs are in off-state
until the internal digital soft start voltage equal the inter-
parator designed with a 1.5ms noise filter will force the
low-side MOSFET gate driver to be high. This action ac-
nal feedback voltage. This will ensure the output voltage
starts from its existing voltage level.
tively pulls down the output voltage and eventually attempts to blow the battery fuse.
The VTT LDO part monitors the output current, both sourcing and sinking current, and limits the maximum output
When the OVP occurs, the PGOOD pin will pull down and
latch-off the converter. This OVP scheme only clamps the
current to prevent damages during current overload or
short circuit (shorted from VTT to GND or VLDOIN)
voltage overshoot, and does not invert the output voltage
when otherwise activated with a continuously high output
conditions.
The VTT LDO provides a soft-start function, using the
from low-side MOSFET driver. It’s a common problem for
OVP schemes with a latch. Once an over-voltage fault
constant current to charge the output capacitor that gives
a rapid and linear output voltage rise. If the load current is
condition is set, toggling VCC power-on-reset signal can
only reset it.
above the current limit start-up, the VTT cannot start
successfully.
PWM Converter Current Limit
The feedback voltage should increase over 125% of the
The current-limit circuit employs a unique “valley” current
APW8861 has an independent counter for each output,
but the PGOOD signal indicates only the status of VDDQ
sensing algorithm (Figure 2). CS pin should be connected to VCC through the trip voltage-setting resistor,
and does not indicate VTT power good externally.
RCS. CS terminal sinks 16µA current, ICS, and the current
limit threshold is set to the voltage across the RCS. The
voltage between or CS_GND pin and PHASE pin moni-
Power-Good Output (PGOOD)
PGOOD is an open-drain output and the PGOOD com-
tors the inductor current so that PHASE pin should be
connected to the drain terminal of the low side MOSFET.
parator continuously monitors the output voltage. PGOOD
is actively held low in shutdown, and standby. When PWM
PGND is used as the positive current sensing node so
that PGND should be connected to the proper current
converter’s output voltage is greater than 95% of its target value, the internal open-drain device will be pulled
sensing device, i.e. the sense resistor or the source terminal of the low side MOSFET.
low. After 63µs debounce time, the PGOOD goes high.
The PGOOD goes low if VVDDQ output is 10% below or
above its nominal regulation point.
If the magnitude of the current-sense signal is above the
current-limit threshold, the PWM is not allowed to initiate
Under Voltage Protection
a new cycle. The actual peak current is greater than the
current-limit threshold by an amount equal to the induc-
In the process of operation, if a short-circuit occurs, the
tor ripple current. Therefore, the exact current- limit characteristic and maximum load capability are a function of
output voltage will drop quickly. When load current is bigger than current limit threshold value, the output voltage
the sense resistance, inductor value, and input voltage.
The equation for the current limit threshold is as follows:
will fall out of the required regulation range. The undervoltage continually monitors the setting output voltage
after 2ms of PWM operations to ensure startup. If a load
step is strong enough to pull the output voltage lower
ILIMIT =
R CS × 16 µA (VIN − VVDDQ ) VVDDQ
+
×
RDS(ON)
2 × L × fSW
VIN
than the under voltage threshold (70% of normal output
voltage), APW8861 shuts down the output gradually and
latches off both high and low side MOSFETs.
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
16
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APW8861
Function Description (Cont.)
on at S0 state. When S3 is low and S5 is high, the VDDQ
Where ILIMIT is the desired current limit threshold, RCS is
the value of the current sense resistor connected to CS
and VTTREF are kept on while the VTT voltage is disabled and left high impedance in S3 state. When both S3
and VCC pins VCS is the voltage across the RCS resistor
IRIPPLE is inductor peak to peak current FSW is the PWM
and S5 are low, the VDDQ, VTT and VTTREF are turned
off and discharged to the ground.
switching frequency
In a current limit condition, the current to the load ex-
Table1. The Truth Table of S3 and S5 pins
ceeds the current to the output capacitor thus the output
voltage tends to fall down. If the output voltage becomes
STATE S3 S5
less than power good level, the VCS is cut into half and the
output voltage tends to be even lower. Eventually, it
crosses the under voltage protection threshold and
shutdown.
S0
H
H
S3
L
H
S4/5
L
L
VDDQ
VTTREF
VTT
1
1
1
1
1
0 (high-Z)
0 (discharge) 0 (discharge) 0 (discharge)
INDUCTOR CURRENT
IPEAK
Thermal Shutdown
A thermal shutdown circuit limits the junction tempera-
ILIMIT
ture of APW8861. When the junction temperature exceeds
+160oC, PWM converter, VTTLDO and VTTREF are shut
IVALLEY
off, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft0
start cycle after the junction temperature cools by 25oC,
resulting in a pulsed output during continuous thermal
Time
overload conditions. The thermal shutdown designed with
a 25oC hysteresis lowers the average junction tempera-
Figure 2. Current Limit Algorithm.
VTT Sink/Source Regulator
The output voltage at VTT pin tracks the reference voltage
ture during continuous thermal overload conditions, extending life time of the device. For normal operation, de-
applied at VTTREF pin. Two internal N-channel MOSFETs
controlled by separate high bandwidth error amplifiers
vice power dissipation should be externally limited so
that junction temperatures will not exceed +125oC
regulate the output voltage by sourcing current from
VLDOIN pin or sinking current to GND pin. To prevent two
Programming the On-Time Control and PWM Switch-
pass transistors from shoot-through, a small voltage offset is created between the positive inputs of the two error
ing Frequency
amplifiers. The VTT with fast response feedback loop
keeps tracking to the VTTREF within +40 mV at all condi-
PWM. The device uses the constant on-time control architecture to produce pseudo-fixed frequency with input
tions including fast load transient.
voltage feed-forward. The on-time pulse width is proportional to output voltage VDDQ and inverse proportional to
The APW8861 does not use a clock signal to produce
S3, S5 Control
In the DDR3/DDR4 memory applications, it is important
input voltage VIN. In PWM, the on-time calculation is written as below equation.
to keep VDDQ always higher than VTT/VTTREF including
both start-up and shutdown. The S3 and S5 signals control the VDDQ, VTT, VTTREF states and these pins should
be c onnec te d to SLP_S3 and SLP_ S5 si gnals
TON = 6.3 × 10
respectively. The table1 shows the truth table of the S3
and S5 pins. When both S3 and S5 are above the logic
−12
2
3 × VVDDQ
× RTON
VIN
threshold voltage, the VDDQ, VTT and VTTREF are turned
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
17
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APW8861
Function Description (Cont.)
Where:
RTON is the resistor connected from TON pin to PHASE
pin. Furthermore, The approximate PWM switching frequency is written as:
TON =
D
= FSW
FSW
=
VOUT / VIN
TON
Where:
FSW is the PWM switching frequency APW8861 doesn’t
have VIN pin to calculate on-time pulse width. Therefore,
monitoring VPHASE voltage as input voltage to calculate ontime when the high-side MOSFET is turned on. And then,
use the relationship between on-time and duty cycle to
obtain the switching frequency.
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
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APW8861
Application Information
Output Voltage Selection
choose the ripple current to be approximately 30% of the
maximum output current. Once the inductance value has
PWM can be also adjusted from 0.75V to 3.3V with a resistor-driver at FB between VDDQSNS and GND. Using
been chosen, selecting an inductor is capable of carrying
the required peak current without going into saturation. In
1% or better resistors for the resistive divider is
recommended. The FB pin is the inverter input of the
some types of inductors, especially core that is made of
ferrite, the ripple current will increase abruptly whenit
error amplifier, and the reference voltage is 0.75V. Take
the example, the output voltage of PWM is determined by:
saturates. This will be result in a larger output ripple
voltage.
R
V OUT = 0.75 × 1 + TOP
R
GND
Output Capacitor Selection
Output voltage ripple and the transient voltage deviation
are factors that have to be taken into consideration when
selecting an output capacitor. Higher capacitor value and
Where RTOP is the resistor connected from VOUT to FB and
RGND is the resistor connected from FB to GND.
lower ESR reduce the output ripple and the load transient
drop. Therefore, selecting high performance low ESR
capacitors is intended for switching regulator applications.
In addition to high frequency noise related MOSFET turn-
Output Inductor Selection
The duty cycle of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
on and turn-off, the output voltage ripple includes the capacitance voltage drop and ESR voltage drop caused by
is fixed, it can be written as:
D=
the AC peak-to-peak current. These two voltages can be
represented by:
VOUT
VIN
∆VCOUT =
IRIPPLE
8C OUT FSW
The inductor value determines the inductor ripple current
∆VESR = IRIPPLE × RESR
and affects the load transient response. Higher inductor
value reduces the inductor’s ripple current and induces
These two components constitute a large portion of the
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
IRIPPLE =
total output voltage ripple. In some applications, multiple
capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
another load with high pulsating current, more capacitors
VIN − VOUT VOUT
×
FSW × L
VIN
are needed in order to reduce the equivalent ESR and
suppress the voltage ripple to a tolerable level. A small
Where FSW is the switching frequency of the regulator.
Although increase the inductor value and frequency re-
decoupling capacitor in parallel for bypassing the noise
is also recommended, and the voltage rating of the out-
duce the ripple current and voltage, there is a tradeoff
between the inductor’s ripple current and the regulator
put capacitors must also be considered.
To support a load transient that is faster than the switch-
load transient response time.
A smaller inductor will give the regulator a faster load
ing frequency, more capacitors have to be used to reduce
the voltage excursion during load step change. Another
transient response at the expense of higher ripple current.
Increasing the switching frequency (FSW) also reduces
aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the
the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipa-
rated RMS current specified on the capacitors to prevent
the capacitor from over-heating.
tion of the converter. The maximum ripple current occurs
at the maximum input voltage. A good starting point is to
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
19
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APW8861
Application Information (Cont.)
• The LDOIN is closed to VDDQ output, the connect
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating
LDOIN and VDDQ output is short and wide trace. If other
and the RMS current rating. For reliable operation, select
the capacitor voltage rating to be at least 1.3 times higher
power is used as LDOIN, the ceramic decoupling capacitor is closed to LDOIN.
than the maximum input voltage. The maximum RMS
current rating requirement is approximately IOUT/2, where
• Decoupling capacitor, the resistor dividers, boot
IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. In low-
close their pins. (For example, place the decoupling
ceramic capacitor near the drain of the high-side
duty notebook applications, ceramic capacitors are
recommended. The capacitors must be connected be-
MOSFET as close as possible. The bulk capacitors are
also placed near the drain).
tween the drain of high-side MOSFET and the source of
low-side MOSFET with very low-impedance PCB layout.
• The high quality ceramic decoupling capacitor can be
capacitors, and current limit stetting resistor should be
put close to the VCC and GND pins; the VTTREF
decoupling capacitor should be close to the VTTREF
pin and GND; the VDDQ and VTT output capacitors
Layout Consideration
In any high switching frequency converter, a correct layout
should be located right across their output pin as close
as possible to the part to minimize parasitic. The input
is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the
capacitor GND should be close to the output capacitor
GND.
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
• It (VIN and PHASE nodes) should be a large plane for
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the
heat sinking.
• The APW8861 used ripple mode control. Build the re-
MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling
sistor divider close to the FB pin so that the high impedance trace is shorter. And the FB pin and VOUT feed-
by the lower MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike
back traces can’t be close to or cross under the switching signal traces (BOOT, and PHASE).
during the switching interval. In general, using short and
wide printed circuit traces should minimize interconnect-
It is recommended to place the switching signal traces
on the top layer and the GND plane under the IC on the
ing impedances and the magnitude of voltage spike. And
signal and power grounds are to be kept separating and
inner1 layer to shield the switching signal traces noise.
finally combined to use the ground plane construction or
single point grounding. The best tie-point between the
0.5
0.2
signal ground and the power ground is at the negative
side of the output capacitor on each channel, where there
0.75
0.3
0.2
0.3
is less noise. Noisy traces beneath the IC are not
recommended. Below is a checklist for your layout:
0.29
1.41
4.0
3.4
• Keep the switching nodes (BOOT, and PHASE) away
from sensitive small signal nodes(FB, VTTREF, and
CS) since these nodes are fast moving signals.
0.39
1.06
1.6
2.9
0.32
0.36
1.45
1.13
Therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces
0.25
0.35
1.1
0.25
in parallel with theses traces on any layer.
PIN1
0.4
Figure 3. Recommended Minimum Footprint.
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
20
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APW8861
Application Information (Cont.)
Power-on Sequencing
The DDR memory applications should have a standard
power-up sequence to avoid system errors at startup.
It is recommended to provide the S3 and S5 signals
after all power inputs are ready. The recommended
power-on sequencing is shown in below figure.
VVCC
VS5 is high after VIN is ready
VIN
VIH_S5
VS5
VDDQ
VS3 is high after
VDDQ is ready
VVTTREF
VIH_S3
VS3
VTT
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
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APW8861
Package Information
TQFN4x4-32
D
E
b
A
Pin 1
D1
A1
A3
K
NX
E1
aaa C
D4
E2
E4
E3
E5
e
Pin 1 Corner
K
D5
D2
D3
K
TQFN4*4-32
S
Y
M
B
O
L
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
MILLIMETERS
A3
INCHES
0.20 REF
0.008 REF
b
0.15
0.25
0.006
0.010
D
3.90
4.10
0.154
0.161
D1
1.01
1.21
0.040
0.048
1.15
0.037
0.045
1.69
0.059
0.067
D2
0.95
D3
1.49
D4
0.25 REF
D5
0.010 REF
0.010 REF
0.26 REF
E
3.90
4.10
0.154
E1
1.03
1.23
0.041
0.161
0.048
E2
1.31
1.51
0.052
0.059
E3
3.20
3.40
0.126
0.134
E4
3.45 REF
E5
0.36 REF
0.014 REF
e
0.4 BSC
0.016 BSC
0.136 REF
L
0.25
0.35
0.010
0.014
K
0.24
0.26
0.009
0.010
aaa
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
0.08
0.003
22
www.anpec.com.tw
APW8861
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN4x4
A
H
T1
C
d
D
330.0±2.00
50 MIN.
12.4+2.00
-0.00
1 3.0+0 .50
-0.20
1.5 MIN.
20 .2 MIN.
P0
P1
P2
D0
D1
4.0±0.10
8 .0 ±0 .1 0
2.0±0.05
1.5+0.10
-0 .00
1.5 MIN.
T
0.6+0.00
-0.40
W
E1
1 2.0 ±0 .3 0 1 .7 5±0.10
F
5.5±0.05
A0
B0
K0
4 .30 ±0 .2 0
4.30±0.20
1 .0 0±0.2 0
(mm)
Devices Per Unit
Package Type
TQFN4x4
Unit
Quantity
Tape & Reel
3000
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
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APW8861
Taping Direction Information
TQFN4x4-32
USER DIRECTION OF FEED
Classification Profile
Copyright ANPEC Electronics Corp.
Rev. A.8 - Jun., 2020
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APW8861
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
20** seconds
30** seconds
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax )
Time (T smin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time (tP)** within 5°C of the specified
classification temperature (Tc )
Average ramp-down rate (T p to Tsma x)
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
≥350
220 °C
220 °C
Volume mm3
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