AO4296

AO4296 100V N-Channel AlphaSGT TM General Description Product Summary VDS • Trench Power AlphaSGTTM technology • Low RDS(ON) • Low Gate Charge • RoHS and Halogen-Free Compliant Applications ID (at VGS=10V) 100V 13.5A RDS(ON) (at VGS=10V) < 8.3mΩ RDS(ON) (at VGS=4.5V) < 10.6mΩ 100% UIS Tested 100% Rg Tested • Synchronous Rectification for AC/DC Quick Charger SOIC-8 Top View D D D Bottom View D D G G S S S S Orderable Part Number Package Type Form Minimum Order Quantity AO4296 SO-8 Tape & Reel 3000 Absolute Maximum Ratings TA=25°C unless otherwise noted Parameter Drain-Source Voltage Symbol VDS Gate-Source Voltage VGS TA=25°C Continuous Drain Current Pulsed Drain Current C Avalanche energy L=0.1mH VDS Spike 10µs TA=25°C Power Dissipation B C Junction and Storage Temperature Range Thermal Characteristics Parameter Maximum Junction-to-Ambient A Maximum Junction-to-Ambient A D Maximum Junction-to-Lead Rev.2.0: June 2016 Steady-State Steady-State A IAS 33 A EAS 54 mJ VSPIKE 120 V 3.1 W 2.0 TJ, TSTG Symbol t ≤ 10s V 55 PD TA=70°C ±20 10.5 IDM Avalanche Current C Units V 13.5 ID TA=70°C Maximum 100 RθJA RθJL -55 to 150 Typ 31 59 16 www.aosmd.com °C Max 40 75 24 Units °C/W °C/W °C/W Page 1 of 5 AO4296 Electrical Characteristics (TJ=25°C unless otherwise noted) Symbol Parameter STATIC PARAMETERS BVDSS Drain-Source Breakdown Voltage Conditions Min ID=250µA, VGS=0V 100 Typ Zero Gate Voltage Drain Current IGSS VGS(th) Gate-Body leakage current VDS=0V, VGS=±20V Gate Threshold Voltage VDS=VGS, ID=250µA 1 TJ=55°C 1.3 ±100 nA 1.75 2.3 V 6.8 8.3 12.2 14.8 10.6 RDS(ON) Static Drain-Source On-Resistance VGS=4.5V, ID=11.5A 8.0 gFS Forward Transconductance VDS=5V, ID=13.5A 75 VSD Diode Forward Voltage IS=1A, VGS=0V 0.7 IS Maximum Body-Diode Continuous Current TJ=125°C DYNAMIC PARAMETERS Input Capacitance Ciss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate resistance VGS=0V, VDS=50V, f=1MHz f=1MHz SWITCHING PARAMETERS Total Gate Charge Qg(10V) Qg(4.5V) Total Gate Charge Qgs Gate Source Charge Qgd tD(on) tr Turn-On Rise Time tD(off) Turn-Off DelayTime tf trr Turn-Off Fall Time Qrr VGS=10V, VDS=50V, ID=13.5A µA 5 VGS=10V, ID=13.5A Coss Units V VDS=100V, VGS=0V IDSS Max 0.7 mΩ mΩ S 1 V 4 A 3130 pF 245 pF 12.5 pF 1.4 2.1 Ω 42 60 nC 18.5 28 nC 7.5 nC Gate Drain Charge 4.5 nC Turn-On DelayTime 8 ns 5 ns 41 ns VGS=10V, VDS=50V, RL=3.70Ω, RGEN=3Ω 7 ns IF=13.5A, di/dt=500A/µs 28 Body Diode Reverse Recovery Charge IF=13.5A, di/dt=500A/µs 130 ns nC Body Diode Reverse Recovery Time A. The value of RθJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25°C. The value in any given application depends on the user's specific board design. B. The power dissipation PD is based on TJ(MAX)=150°C, using ≤ 10s junction-to-ambient thermal resistance. C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=150°C. Ratings are based on low frequency and duty cycles to keep initialTJ=25°C. D. The RθJA is the sum of the thermal impedance from junction to lead RθJL and lead to ambient. E. The static characteristics in Figures 1 to 6 are obtained using or equal to 4.5V Figure 9: Maximum Forward Biased Safe Operating Area (Note F) 1000 1 1E-05 0.001 0.1 10 Pulse Width (s) Figure 10: Single Pulse Power Rating Junction-toAmbient (Note F) ZθJA Normalized Transient Thermal Resistance 10 In descending order D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse D=Ton/T TJ,PK=TA+PDM.ZθJA.RθJA 1 RθJA=75°C/W 0.1 PDM 0.01 0.001 1E-05 Single Pulse Ton 0.0001 0.001 0.01 0.1 1 T 10 100 Pulse Width (s) Figure 11: Normalized Maximum Transient Thermal Impedance (Note F) Rev.2.0: June 2016 www.aosmd.com Page 4 of 5 AO4296 Figure A: Charge Gate Charge Test Circuit & Waveforms Gate Test Circuit & Waveform Vgs Qg 10V + + Vds VDC - Qgs Qgd VDC - DUT Vgs Ig Charge Figure B:Resistive ResistiveSwitching Switching Test Test Circuit Circuit&&Waveforms Waveforms RL Vds Vds DUT Vgs 90% + Vdd VDC - Rg 10% Vgs Vgs td(on) tr td(off) ton tf toff Figure C: UnclampedInductive InductiveSwitching Switching (UIS) Test Unclamped Test Circuit Circuit&&Waveforms Waveforms L 2 EAR= 1/2 LIAR Vds BVDSS Vds Id + Vdd Vgs Vgs I AR VDC - Rg Id DUT Vgs Vgs Figure D: Recovery Diode Recovery Test Circuit & Waveforms Diode Test Circuit & Waveforms Q rr = - Idt Vds + DUT Vgs Vds - Isd Vgs Ig Rev.2.0: June 2016 L Isd + Vdd t rr dI/dt I RM Vdd VDC - IF Vds www.aosmd.com Page 5 of 5