AON3818
24V Dual N-Channel αMOS™
General Description
Product Summary
• Trench Power αMOS™ LV technology
• Low RDS(ON)
• Low Gate Charge
• ESD protection
• RoHS and Halogen-Free Compliant
VDS
ID (at VGS=4.5V)
24V
8A
RDS(ON) (at VGS=4.5V)
< 13.5mΩ
RDS(ON) (at VGS=4.0V)
< 14mΩ
RDS(ON) (at VGS=3.7V)
< 15mΩ
RDS(ON) (at VGS=3.1V)
< 17mΩ
RDS(ON) (at VGS=2.5V)
< 21mΩ
Typical ESD protection
HBM Class 2
Applications
• Battery protection switch
• Mobile device battery charging and discharging
DFN 3x3
Top View
D2
D1
Bottom View
Top View
1
2
3
4
S2
G2
S1
G1
8
D1/D2
7
6
5
D1/D2
G1
G2
D1/D2
D1/D2
S2
S1
Pin 1
Orderable Part Number
Package Type
Form
Minimum Order Quantity
AON3818
DFN 3x3
Tape & Reel
3000
Absolute Maximum Ratings TA=25°C unless otherwise noted
Parameter
Drain-Source Voltage
Symbol
VDS
Gate-Source Voltage
Continuous Drain
Current G
VGS
TA=25°C
Pulsed Drain Current C
Junction and Storage Temperature Range
Thermal Characteristics
Parameter
Maximum Junction-to-Ambient
Maximum Junction-to-Ambient
Maximum Junction-to-Lead
Rev.2.0: July 2019
AD
t ≤ 10s
Steady-State
Steady-State
A
2.7
W
1.7
TJ, TSTG
Symbol
A
V
32
PD
TA=70°C
±12
6
IDM
TA=25°C
Power Dissipation B
Units
V
8
ID
TA=70°C
Maximum
24
RqJA
RqJL
-55 to 150
Typ
35
60
15
www.aosmd.com
°C
Max
45
75
20
Units
°C/W
°C/W
°C/W
Page 1 of 5
AON3818
Electrical Characteristics (TJ=25°C unless otherwise noted)
Symbol
Parameter
STATIC PARAMETERS
BVDSS
Drain-Source Breakdown Voltage
Conditions
Min
ID=250μA, VGS=0V
Typ
Max
Units
24
V
VDS=24V, VGS=0V
1
μA
IDSS
Zero Gate Voltage Drain Current
IGSS
VGS(th)
Gate-Body leakage current
VDS=0V, VGS=±10V
±10
μA
Gate Threshold Voltage
VDS=VGS, ID=250mA
0.4
0.8
1.2
V
VGS=4.5V, ID=8A
7.5
10.8
13.5
TJ=55°C
TJ=125°C
RDS(ON)
Static Drain-Source On-Resistance
5
10.5
15
19
VGS=4.0V, ID=6A
7.8
11.2
14
VGS=3.7V, ID=6A
8
11.5
15
VGS=3.1V, ID=4A
8
12.5
17
VGS=2.5V, ID=4A
8.6
14.8
21
gFS
Forward Transconductance
VDS=5V, ID=8A
42
VSD
Diode Forward Voltage
IS=1A,VGS=0V
0.66
IS
Maximum Body-Diode Continuous Current
DYNAMIC PARAMETERS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate resistance
VGS=0V, VDS=12V, f=1MHz
f=1MHz
SWITCHING PARAMETERS
Qg
Total Gate Charge
Qgs
Gate Source Charge
Qgd
tD(on)
tr
Turn-On Rise Time
tD(off)
Turn-Off DelayTime
tf
Turn-Off Fall Time
S
1
V
4
A
840
pF
210
pF
205
pF
2
kΩ
9.5
VGS=4.5V, VDS=12V, ID=8A
mΩ
15
nC
1.5
nC
Gate Drain Charge
4.5
nC
Turn-On DelayTime
0.3
μs
0.8
μs
1.7
μs
5.2
μs
VGS=4.5V, VDS=12V, RL=1.5W,
RGEN=3W
A. The value of RqJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25°C. The
value in any given application depends on the user's specific board design.
B. The power dissipation PD is based on TJ(MAX)=150°C, using ≤ 10s junction-to-ambient thermal resistance.
C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=150°C. Ratings are based on low frequency and duty cycles to keep
initialTJ=25°C.
D. The RqJA is the sum of the thermal impedance from junction to lead RqJL and lead to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using or equal to 2.5V
Figure 9: Maximum Forward Biased
Safe Operating Area (Note F)
1
1E-05 0.0001 0.001 0.01
100
0.1
1
10
100
Pulse Width (s)
Figure 10: Single Pulse Power Rating Junction-toAmbient (Note F)
D=Ton/T
TJ,PK=TA+PDM.ZqJA.RqJA
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
RqJA=75°C/W
0.1
PD
0.01
Single Pulse
Ton
T
0.001
1E-05
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
Rev.2.0: July 2019
www.aosmd.com
Page 4 of 5
AON3818
Gate Charge Test Circuit & Waveform
Vgs
Qg
10V
+
+ Vds
VDC
-
Qgs
Qgd
VDC
-
DUT
Vgs
Ig
Charge
Resistive Switching Test Circuit & Waveforms
RL
Vds
Vds
90%
+ Vdd
DUT
Vgs
VDC
-
Rg
10%
Vgs
Vgs
td(on)
tr
td(off)
ton
tf
toff
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
L
2
EAR= 1/2 LIAR
Vds
BVDSS
Vds
Id
+ Vdd
Vgs
Vgs
I AR
VDC
-
Rg
Id
DUT
Vgs
Vgs
Diode Recovery Test Circuit & Waveforms
Q rr = - Idt
Vds +
DUT
Vds -
Isd
Vgs
Ig
Rev.2.0: July 2019
Vgs
L
Isd
+ Vdd
t rr
dI/dt
I RM
Vdd
VDC
-
IF
Vds
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Page 5 of 5
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