AON6450L

AON6450L N-Channel SDMOS TM Power Transistor General Description Product Summary The AON6450L is fabricated with SDMOSTM trench technology that combines excellent RDS(ON) with low gate charge.The result is outstanding efficiency with controlled switching behavior. This universal technology is well suited for PWM, load switching and general purpose applications. Parameter VDS ID (at VGS=10V) 100V 52A RDS(ON) (at VGS=10V) < 14.5mΩ RDS(ON) (at VGS = 7V) < 17.5mΩ 100% UIS Tested! 100% R g Tested! - RoHS Compliant - Halogen Free D Top View Fits SOIC8 footprint ! G S DFN5X6 Absolute Maximum Ratings TA=25°C unless otherwise noted Parameter Symbol VDS Drain-Source Voltage VGS Gate-Source Voltage TC=25°C Continuous Drain Current Pulsed Drain Current C Avalanche Current C C TC=25°C Power Dissipation B TA=25°C Power Dissipation A TA=70°C Thermal Characteristics Parameter Maximum Junction-to-Ambient A AD Maximum Junction-to-Ambient Maximum Junction-to-Case EAR Steady-State Steady-State 41 A 84 mJ W 33 2.3 RθJA RθJC www.aosmd.com W 1.4 TJ, TSTG Symbol t ≤ 10s A 83 PDSM Junction and Storage Temperature Range Rev 0: January 2009 9 PD TC=100°C A 7 IAR Repetitive avalanche energy L=0.1mH V 110 IDSM TA=70°C ±25 33 IDM TA=25°C Continuous Drain Current Units V 52 ID TC=100°C Maximum 100 °C -55 to 150 Typ 14 40 1 Max 17 55 1.5 Units °C/W °C/W °C/W Page 1 of 7 AON6450L Electrical Characteristics (T J=25°C unless otherwise noted) Parameter Symbol STATIC PARAMETERS BVDSS Drain-Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current Conditions Min ID=250µA, VGS=0V VDS=100V, VGS=0V 100 50 Gate-Body leakage current VDS=0V, VGS= ±25V VGS(th) ID(ON) Gate Threshold Voltage On state drain current VDS=VGS ID=250µA 2.8 VGS=10V, VDS=5V 110 VGS=10V, ID=20A TJ=125°C VGS=7V, ID=20A gFS Forward Transconductance VSD Diode Forward Voltage IS=1A,VGS=0V Maximum Body-Diode Continuous Current IS VDS=5V, ID=20A DYNAMIC PARAMETERS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate resistance SWITCHING PARAMETERS Qg(10V) Total Gate Charge Qg(4.5V) Total Gate Charge Qgs Gate Source Charge Qgd Gate Drain Charge tD(on) Turn-On DelayTime tr Turn-On Rise Time tD(off) Turn-Off DelayTime tf Turn-Off Fall Time VGS=0V, VDS=50V, f=1MHz VGS=0V, VDS=0V, f=1MHz VGS=10V, VDS=50V, ID=20A Units V TJ=55°C Static Drain-Source On-Resistance Max 10 IGSS RDS(ON) Typ µA 100 nA 3.4 4 V 12.1 14.5 22.8 27.5 14 17.5 mΩ 1 V 52 A A 52 0.7 mΩ S 2000 2570 3100 pF 170 250 330 pF 50 80 120 pF 0.4 0.8 1.2 Ω 34 43 52 nC 9 11.5 14 nC 11 14 17 nC 8 13.5 19 nC VGS=10V, VDS=50V, RL=2.5Ω, RGEN=3Ω 15 ns 5 ns 28.5 ns 5 ns trr Body Diode Reverse Recovery Time IF=20A, dI/dt=500A/µs 17 24 31 Qrr Body Diode Reverse Recovery Charge IF=20A, dI/dt=500A/µs 75 108 140 ns nC A. The value of RθJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with TA =25°C. The Power dissipation PDSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on the user's specific board design, and the maximum temperature of 150°C may be used if the PCB allows it. B. The power dissipation PD is based on TJ(MAX)=150°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=150°C. Ratings are based on low frequency and duty cycles to keep initial TJ =25°C. D. The RθJA is the sum of the thermal impedence from junction to case R θJC and case to ambient. E. The static characteristics in Figures 1 to 6 are obtained using