AOSD62666E

AOSD62666E 60V Dual N-Channel AlphaSGT TM General Description Product Summary VDS • Trench Power AlphaSGTTM technology • Low RDS(ON) • Logic Level Gate Drive • ESD Protected • Excellent Gate Charge x RDS(ON) Product (FOM) • RoHS and Halogen-Free Compliant Applications ID (at VGS=10V) 60V 9.5A RDS(ON) (at VGS=10V) < 14.5mΩ RDS(ON) (at VGS=4.5V) < 19mΩ Typical ESD protection HBM Class 2 100% UIS Tested 100% Rg Tested • Motor Control, Lighting, Industrial and Load switch SOIC-8 Top View Bottom View D1 Top View S2 G2 S1 G1 1 2 3 4 8 7 6 5 D2 D2 D1 D1 G1 D2 G2 S1 S2 Pin1 Orderable Part Number Package Type Form Minimum Order Quantity AOSD62666E SO-8 Tape & Reel 3000 Absolute Maximum Ratings TA=25°C unless otherwise noted Parameter Drain-Source Voltage Symbol VDS Gate-Source Voltage VGS TA=25°C Continuous Drain Current Pulsed Drain Current C Avalanche energy L=0.3mH TA=25°C Power Dissipation B TA=70°C C Thermal Characteristics Parameter Maximum Junction-to-Ambient A Maximum Junction-to-Ambient A D Maximum Junction-to-Lead Rev.1.0: May 2017 Steady-State Steady-State A IAS 14 A EAS 29 mJ 2.5 W 1.6 TJ, TSTG Symbol t ≤ 10s V 38 PD Junction and Storage Temperature Range ±20 7.5 IDM Avalanche Current C Units V 9.5 ID TA=70°C Maximum 60 RθJA RθJL -55 to 150 Typ 42 70 30 www.aosmd.com °C Max 50 85 40 Units °C/W °C/W °C/W Page 1 of 5 AOSD62666E Electrical Characteristics (TJ=25°C unless otherwise noted) Symbol Parameter STATIC PARAMETERS BVDSS Drain-Source Breakdown Voltage Conditions Min ID=250µA, VGS=0V Zero Gate Voltage Drain Current IGSS VGS(th) Gate-Body leakage current VDS=0V, VGS=±20V Gate Threshold Voltage VDS=VGS, ID=250µA VGS=10V, ID=9.5A Static Drain-Source On-Resistance gFS Forward Transconductance VDS=5V, ID=9.5A VSD Diode Forward Voltage IS=1A, VGS=0V IS Maximum Body-Diode Continuous Current TJ=125°C VGS=4.5V, ID=8.5A Crss Reverse Transfer Capacitance Rg Gate resistance µA 2.2 V 12 14.5 19.2 23.5 15.3 19 0.72 VGS=0V, VDS=30V, f=1MHz mΩ S 1 V 3.5 A 755 pF 220 pF 20 pF 1.3 2.0 Ω 13.5 20 nC Qg(4.5V) Total Gate Charge 6.5 10 Qgs Gate Source Charge Gate Drain Charge Qoss Output Charge tD(on) Turn-On DelayTime tr Turn-On Rise Time tD(off) Turn-Off DelayTime tf trr Turn-Off Fall Time Qrr VGS=10V, VDS=30V, ID=9.5A VGS=0V, VDS=30V VGS=10V, VDS=30V, RL=3.15Ω, RGEN=3Ω 0.6 mΩ SWITCHING PARAMETERS Total Gate Charge Qg(10V) Qgd f=1MHz ±10 1.7 33 DYNAMIC PARAMETERS Input Capacitance Ciss Output Capacitance µA 5 1.2 Units V 1 TJ=55°C RDS(ON) Max 60 VDS=60V, VGS=0V IDSS Coss Typ nC 2.5 nC 3.0 nC 11 nC 5 ns 3 ns 19 ns 3 ns IF=9.5A, di/dt=500A/µs 15 Body Diode Reverse Recovery Charge IF=9.5A, di/dt=500A/µs 45 ns nC Body Diode Reverse Recovery Time A. The value of RθJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25°C. The value in any given application depends on the user's specific board design. B. The power dissipation PD is based on TJ(MAX)=150°C, using ≤ 10s junction-to-ambient thermal resistance. C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=150°C. Ratings are based on low frequency and duty cycles to keep initialTJ=25°C. D. The RθJA is the sum of the thermal impedance from junction to lead RθJL and lead to ambient. E. The static characteristics in Figures 1 to 6 are obtained using or equal to 4.5V Figure 9: Maximum Forward Biased Safe Operating Area (Note F) 100 1 1E-05 0.001 0.1 10 Pulse Width (s) Figure 10: Single Pulse Power Rating Junction-toAmbient (Note F) ZθJA Normalized Transient Thermal Resistance 10 In descending order D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse D=Ton/T TJ,PK=TA+PDM.ZθJA.RθJA 1 RθJA=85°C/W 0.1 PDM 0.01 0.001 1E-05 Single Pulse Ton T 0.0001 0.001 0.01 0.1 1 10 100 Pulse Width (s) Figure 11: Normalized Maximum Transient Thermal Impedance (Note F) Rev.1.0: May 2017 www.aosmd.com Page 4 of 5 AOSD62666E Figure A: Charge Gate Charge Test Circuit & Waveforms Gate Test Circuit & Waveform Vgs Qg 10V + + Vds VDC - Qgs Qgd VDC - DUT Vgs Ig Charge Figure B:Resistive ResistiveSwitching Switching Test Test Circuit Circuit&&Waveforms Waveforms RL Vds Vds DUT Vgs 90% + Vdd VDC - Rg 10% Vgs Vgs td(on) tr td(off) ton tf toff Figure C: UnclampedInductive InductiveSwitching Switching (UIS) Test Unclamped Test Circuit Circuit&&Waveforms Waveforms L 2 EAR= 1/2 LIAR Vds BVDSS Vds Id + Vdd Vgs Vgs I AR VDC - Rg Id DUT Vgs Vgs Figure D: Recovery Diode Recovery Test Circuit & Waveforms Diode Test Circuit & Waveforms Q rr = - Idt Vds + DUT Vgs Vds - Isd Vgs Ig Rev.1.0: May 2017 L Isd + Vdd t rr dI/dt I RM Vdd VDC - IF Vds www.aosmd.com Page 5 of 5