AOZ1020
EZBuck™ 2A Synchronous Buck Regulator
Not Recommended For New Designs
Features
The AOZ1020 is a synchronous high efficiency, simple
to use, 2A buck regulator. The AOZ1020 works from a
4.5V to 16V input voltage range, and provides up to 2A
of continuous output current with an output voltage
adjustable down to 0.8V.
●
4.5V to 16V operating input voltage range
●
Synchronous rectification: 130mΩ internal high-side
switch and 65mΩ internal low-side switch
●
High efficiency: up to 95%
●
Internal soft start
●
Active high power good state
●
Output voltage adjustable to 0.8V
●
2A continuous output current
●
Fixed 500kHz PWM operation
●
Cycle-by-cycle current limit
●
Pre-bias start-up
●
Short-circuit protection
●
Thermal shutdown
●
Small size SO-8 packages
ig
es
D
ew
Fo
r
Replacement Part: AOZ3024PI
N
The AOZ1020 comes in an SO-8 packages and is rated
over a -40°C to +85°C ambient temperature range.
ns
General Description
Applications
Point of load DC/DC conversion
●
PCIe graphics cards
●
Set top boxes
●
DVD drives and HDD
●
LCD panels
●
Cable modems
●
Telecom/Networking/Datacom equipment
ec
Typical Application
om
m
en
de
d
●
5V DC
C1
22µF
Ceramic
R3
VIN
PGOOD
L1 4.7µH
N
ot
R
VIN
EN
AOZ1020
VOUT
LX
R1
COMP
RC
CC
C2, C3
22µF Ceramic
FB
AGND
PGND
R2
Figure 1. 3.3V/2A Buck Regulator
Rev. 1.5 December 2010
www.aosmd.com
Page 1 of 15
AOZ1020
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1020AI
-40°C to +85°C
SO-8
RoHS
AOZ1020AIL
Green Product
All AOS products are offered in packages with Pb-free plating and compliant to RoHS standards.
Parts marked as Green Products (with “L” suffix) use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
1
8
PGOOD
VIN
2
7
LX
AGND
3
6
EN
FB
4
5
COMP
AGND
4
FB
5
COMP
6
EN
7
LX
8
PGOOD
d
VIN
3
Supply voltage input. When VIN rises above the UVLO threshold the device starts up.
Reference connection for controller section. Also used as thermal connection for controller section.
Electrically needs to be connected to PGND.
The FB pin is used to determine the output voltage via a resistor divider between the output and
GND.
External loop compensation pin.
The enable pin is active HIGH.
PWM output connection to inductor.
Power good signal output pin. It is an open drain output used to indicate the status of output
voltages. This pin is internally pulled low when the output is below 90% of the nominal voltage.
N
ot
R
ec
2
Power ground. Electrically needs to be connected to AGND.
de
PGND
en
1
Pin Function
om
m
Pin Name
D
ew
Fo
r
Pin Description
Pin Number
N
SO-8
(Top View)
es
PGND
ig
ns
Pin Configuration
Rev. 1.5 December 2010
www.aosmd.com
Page 2 of 15
AOZ1020
Block Diagram
VIN
UVLO
& POR
EN
Internal
+5V
5V LDO
Regulator
OTP
+
ISen
Softstart
Q1
ig
ILimit
FB
–
–
Level
Shifter
+
FET
Driver
PWM
Control
Logic
PWM
Comp
+
0.72V
+
Oscillator
N
–
Q2
Fo
r
+
0.2V
Frequency
Foldback
Comparator
LX
ew
COMP
D
EAmp
es
+
+
0.8V
ns
–
Reference
& Bias
d
PGOOD
de
–
om
m
en
AGND
PGND
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum Ratings may damage the device.
The device is not guaranteed to operate beyond the Recommended Operating Conditions.
LX to AGND
ot
EN to AGND
R
Supply Voltage (VIN)
ec
Parameter
Rating
Parameter
18V
-0.7V to VIN+0.3V
Supply Voltage (VIN)
-0.3V to VIN+0.3V
Output Voltage Range
Rating
4.5V to 16V
0.8V to VIN
-0.3V to 6V
Ambient Temperature (TA)
COMP to AGND
-0.3V to 6V
PGND to AGND
-0.3V to 0.3V
Package Thermal Resistance (ΘJA)(2)
SO-8
87°C/W
PGOOD to AGND
-0.3V to 6.0V
Package Thermal Resistance (ΘJC)
SO-8
30°C/W
N
FB to AGND
Junction Temperature (TJ)
+150°C
Storage Temperature (TS)
-65°C to +150°C
ESD Ratingl(1)
2.0kV
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Rev. 1.5 December 2010
Package Power Dissipation (PD)
@25°C Ambient
SO-8
-40°C to +85°C
1.15W
Note:
2. The value of ΘJA is measured with the device mounted on 1-in2
FR-4 board with 2oz. Copper, in a still air environment with TA =
25°C. The value in any given application depends on the user's specific board design.
www.aosmd.com
Page 3 of 15
AOZ1020
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.(3)
Symbol
VIN
Parameter
Conditions
Min.
Supply Voltage
Typ.
4.5
Max.
Units
16
V
Input Under-Voltage Lockout Threshold
VIN Rising
VIN Falling
4.1
3.7
Supply Current (Quiescent)
IOUT = 0, VFB = 1.2V, VEN > 1.2V
1.6
2.5
mA
IOFF
Shutdown Supply Current
VEN = 0V
1
10
µA
VFB
Feedback Voltage
TA = 25°C
0.8
0.812
0.788
0.5
%
Line Regulation
1
%
200
nA
es
ENABLE
VHYS
Off Threshold
On Threshold
D
EN Input Threshold
EN Input Hysteresis
MODULATOR
TA = -40°C to +85°C
Maximum Duty Cycle
DMIN
Minimum Duty Cycle
GVEA
Error Amplifier Voltage Gain
GEA
Error Amplifier Transconductance
Current Limit
Soft Start Interval
POWER GOOD
VOLPG
PG LOW Voltage
PG Leakage
600
kHz
%
6
%
500
V/ V
200
µA / V
2.5
4.0
PG Threshold Voltage
87
R
PG Delay Time
A
150
100
°C
4
ms
IOL = 1mA
PG Threshold Voltage Hystersis
tPG
500
mV
100
TJ Rising
TJ Falling
ec
VPGL
om
m
tSS
en
Over-Temperature Shutdown Limit
de
PROTECTION
ILIM
350
V
d
DMAX
100
Fo
r
N
Frequency
fO
0.6
2
ew
VEN
V
Load Regulation
Feedback Voltage Input Current
IFB
V
ns
IIN
ig
VUVLO
90
0.5
V
1
µA
92
%VO
3
%
128
µs
PWM OUTPUT STAGE
N
ot
High-Side Switch On-Resistance
Low-Side Switch On-Resistance
VIN = 12V
VIN = 5V
97
166
130
200
mΩ
VIN = 12V
VIN = 5V
50
75
65
105
mΩ
Note:
3. Specifications in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Rev. 1.5 December 2010
www.aosmd.com
Page 4 of 15
AOZ1020
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Light Load Operation
Full Load (CCM) Operation
Vin ripple
0.1V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
Vo ripple
20mV/div
IL
1A/div
VLX
20V/div
VLX
20V/div
es
ig
ns
IL
1A/div
1s/div
Startup to Full Load
50% to 100% Load Transient
ew
D
1s/div
N
PGOOD
5V/div
Vo Ripple
50mV/div
Fo
r
Vo
2V/div
de
100s/div
N
ot
R
ec
om
m
en
1ms/div
lo
1A/div
d
lin
0.5A/div
Rev. 1.5 December 2010
www.aosmd.com
Page 5 of 15
AOZ1020
Efficiency
AOZ1020AI Efficiency
Efficiency (VIN = 12V) vs. Load Current
100
95
90
3.3V OUTPUT
85
ns
Efficieny (%)
5.0V OUTPUT
1.8V OUTPUT
ig
80
1.2V OUTPUT
es
75
D
70
0
0.2
0.4
0.6
0.8
1.0
1.2
Load Current (A)
1.4
1.6
1.8
2.0
N
ot
R
ec
om
m
en
de
d
Fo
r
N
60
ew
65
Rev. 1.5 December 2010
www.aosmd.com
Page 6 of 15
AOZ1020
Detailed Description
The AOZ1020 is a current-mode, step down regulator with
integrated high-side PMOS switch and a low-side NMOS
switch. It operates from a 4.5V to 16V input voltage range
and supplies up to 2A of load current. The duty cycle
can be adjusted from 6% to 100% allowing a wide output
voltage range. Features include enable control, Power-On
Reset, input under voltage lockout, output over voltage
protection, active high power good state, fixed internal
soft-start and thermal shut down.
Comparing with regulators using freewheeling Schottky
diodes, the AOZ1020 uses freewheeling NMOSFET to
realize synchronous rectification. It greatly improves the
converter efficiency and reduces power loss in the
low-side switch.
es
D
ew
V O_MAX = V IN – I O × R DS ( ON )
where;
VO_MAX is the maximum output voltage,
en
de
d
The EN pin of the AOZ1020 is active HIGH. Connect the
EN pin to VIN if the enable function is not used. Pulling
EN to ground will disable the AOZ1020. Do not leave it
open. The voltage on the EN pin must be above 2V to
enable the AOZ1020. When voltage on the EN pin falls
below 0.6V, the AOZ1020 is disabled. If an application
circuit requires the AOZ1020 to be disabled, an open
drain or open collector circuit should be used to interface
to the EN pin.
The AOZ1020 uses a P-Channel MOSFET as the highside switch. It saves the bootstrap capacitor normally
seen in a circuit which is using an NMOS switch. It allows
100% turn-on of the high-side switch to achieve linear
regulation mode of operation. The minimum voltage drop
from VIN to VO is the load current x DC resistance of
MOSFET + DC resistance of buck inductor. It can be
calculated by the equation below:
N
The AOZ1020 has an internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In the soft start process, the output
voltage is typically ramped to regulation voltage in 4ms.
The 4ms soft start time is set internally.
Fo
r
Enable and Soft Start
ig
ns
The AOZ1020 is available in an SO-8 package.
current signal and ramp compensation signal, at the
PWM comparator input. If the current signal is less than
the error voltage, the internal high-side switch is on. The
inductor current flows from the input through the inductor
to the output. When the current signal exceeds the error
voltage, the high-side switch is off. The inductor current
is freewheeling through the internal low-side NMOSFET
switch to output. The internal adaptive FET driver
guarantees no turn on overlap of both high-side and
low-side switch.
Power Good
R
ec
om
m
The output of Power-Good is an open drain N-channel
MOSFET which supplies an active HIGH power good
stage. A pull-up resistor (R3) should connect this pin to a
DC power trail with maximum voltage no higher than 6V.
The AOZ1020 monitors the FB voltage; when FB pin
voltage is lower than 90% of the normal voltage,
N-channel MOSFET turns on and the Power-Good pin is
pulled LOW, which indicates the power is abnormal.
IO is the output current from 0A to 2A, and
RDS(ON) is the on resistance of internal MOSFET, the value is
between 97mΩ and 200mΩ depending on input voltage and
junction temperature.
Switching Frequency
The AOZ1020 switching frequency is fixed and set by
an internal oscillator. The practical switching frequency
could range from 400kHz to 600kHz due to device
variation.
Output Voltage Programming
ot
Steady-State Operation
N
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
The AOZ1020 integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error
voltage, which shows on the COMP pin, is compared
against the current signal, which is sum of inductor
Rev. 1.5 December 2010
VIN is the input voltage from 4.5V to 16V,
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network. See the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation below:
R 1⎞
⎛
V O = 0.8 × ⎜ 1 + -------⎟
R 2⎠
⎝
www.aosmd.com
Page 7 of 15
AOZ1020
Some standard value of R1, R2 and most used output
voltage values are listed in Table 1.
high side PMOS if the junction temperature exceeds
150°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
VO (V)
R1 (kΩ)
R2 (kΩ)
0.8
1.0
open
1.2
4.99
10
1.5
10
11.5
1.8
12.7
10.2
2.5
21.5
10
Input Capacitor
3.3
31.1
10
5.0
52.3
10
The input capacitor must be connected to the VIN pin and
PGND pin of AOZ1020 to maintain steady input voltage
and filter out the pulsing input current. The voltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
Application Information
es
D
VO ⎞ VO
IO
⎛
ΔV IN = ----------------- × ⎜ 1 – ---------⎟ × --------f × C IN ⎝
V IN⎠ V IN
N
Since the switch duty cycle can be as high as 100%, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on upper PMOS and
inductor.
The input ripple voltage can be approximated by equation below:
ew
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
ig
ns
The basic AOZ1020 application circuit is show in
Figure 1. Component selection is explained below.
The AOZ1020 has multiple protection features to prevent
system circuit damage under abnormal conditions.
d
Over Current Protection (OCP)
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a
buck circuit, the RMS value of input capacitor current
can be calculated by:
Fo
r
Protection Features
om
m
en
de
The sensed inductor current signal is also used for
over current protection. Since the AOZ1020 employs
peak current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited cycle
by cycle.
if we let m equal the conversion ratio:
VO
-------- = m
V IN
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 2 below. It can be seen that when VO is half of
VIN, CIN is under the worst current stress. The worst current stress on CIN is 0.5 x IO.
0.5
ot
R
ec
When the output is shorted to ground under fault
conditions, the inductor current decays very slow during
a switching cycle because of VO = 0V. To prevent catastrophic failure, a secondary current limit is designed
inside the AOZ1020. The measured inductor current is
compared against a preset voltage which represents the
current limit, between 2.5A and 3.6A. When the output
current is more than current limit, the high side switch will
be turned off. The converter will initiate a soft start once
the over-current condition is resolved.
VO ⎛
VO ⎞
- ⎜ 1 – --------⎟
I CIN_RMS = I O × -------V IN ⎝
V IN⎠
N
0.4
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.1V, the converter
starts operation. When input voltage falls below 3.7V,
the converter shuts down.
ICIN_RMS(m) 0.3
IO
0.2
0.1
0
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
Rev. 1.5 December 2010
www.aosmd.com
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
Page 8 of 15
AOZ1020
Table 2.
Vout
5.0V
3.3V
1.8V
L1
Manufacture
Unshielded, 4.7uH
LQH55DN4R7M03
MURATA
Shielded, 4.7uH
LQH66SN4R7M03
MURATA
Shield, 5.8uH
ET553-5R8
ELYTONE
Un-shielded, 4.7uH
DO3316P-472MLD
1.2V
0.8V
MURATA
ig
Inductor
Unshielded, 1.5uH
LQH55DN1R5M03
Coilcraft
ns
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics.
Note that the ripple current rating from capacitor manufactures are based on certain amount of life time.
Further de-rating may be necessary in practical design.
Shield, 1.5uH
LQH66SN1R5M03
MURATA
Shield, 2.2uH
ET553-2R2
ELYTONE
D
es
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
Un-shielded, 1.5uH
DO3316P-152MLD
Coilcraft
Un-shielded, 1.5uH
DO1813P-152HC
Coilcraft
N
ew
VO ⎛
VO ⎞
-⎟
ΔI L = ----------- × ⎜ 1 – -------f×L ⎝
V IN⎠
The peak inductor current is:
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
d
om
m
en
de
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20%
to 30% of output current.
Fo
r
ΔI L
I Lpeak = I O + -------2
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
R
ec
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
N
ot
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Table 2 lists some inductors for typical output voltage
design.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
1
ΔV O = ΔI L × ⎛ ESR CO + -------------------------⎞
⎝
8×f×C ⎠
O
where,
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused
by capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
1
ΔV O = ΔI L × ⎛ -------------------------⎞
⎝8 × f × C ⎠
O
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
ΔV O = ΔI L × ESR CO
Rev. 1.5 December 2010
www.aosmd.com
Page 9 of 15
AOZ1020
For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum are recommended to
be used as output capacitors.
In a buck converter, output capacitor current is continuous.
The RMS current of output capacitor is decided by the
peak to peak inductor ripple current. It can be calculated
by:
ΔI L
I CO_RMS = ---------12
and C compensation network connected to COMP
provides one pole and one zero. The pole is:
G EA
f p2 = ------------------------------------------2π × C C × G VEA
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage; and
es
1
f Z2 = ----------------------------------2π × C C × R C
ig
The zero given by the external compensation network,
capacitor C2 and resistor R3, is located at:
D
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and inductor ripple current is high, the output capacitor could be
overstressed.
ns
C2 is compensation capacitor in Figure 1.
ew
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1020 operates at a frequency range from 400kHz
to 600kHz. It is recommended to choose a crossover
frequency equal or less than 40kHz.
de
d
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is the dominant pole can
be calculated by:
N
The AOZ1020 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When designing the compensation loop, converter stability under all
line and load condition must be considered.
Fo
r
Loop Compensation
en
1
f p1 = ----------------------------------2π × C O × R L
om
m
The zero is an ESR zero due to output capacitor and its
ESR. It is can be calculated by:
1
f Z1 = -----------------------------------------------2π × C O × ESR CO
ec
where;
f C = 40kHz
The strategy for choosing RC and CC is to set the
cross over frequency with RC and set the compensator
zero with CC. Using selected crossover frequency, fC,
to calculate R3:
2π × C 2
VO
R C = f C × ---------- × -----------------------------V
G ×G
R
CO is the output filter capacitor,
RL is load resistor value, and
FB
EA
CS
where;
The compensation design is actually to shape the
converter control loop transfer function to get the desired
gain and phase. Several different types of compensation
network can be used for the AOZ1020. In most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
where fC is desired crossover frequency. For best performance,
fC is set to be about 1/10 of switching frequency,
N
ot
ESRCO is the equivalent series resistance of output capacitor.
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V, and
GCS is the current sense circuit transconductance, which is
5.64 A/V
In the AOZ1020, FB pin and COMP pin are the inverting
input and the output of internal error amplifier. A series R
Rev. 1.5 December 2010
www.aosmd.com
Page 10 of 15
AOZ1020
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. C2 can is selected by:
1.5
C C = ----------------------------------2π × R C × f p1
The maximum junction temperature of AOZ1020 is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1020 under different ambient
temperature.
The thermal performance of the AOZ1020 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
1. Do not use thermal relief connection to the VIN
and the PGND pin. Pour a maximized copper area
to the PGND pin and the VIN pin to help thermal
dissipation.
N
2. Input capacitor should be connected as close as
possible to the VIN pin and the PGND pin.
Fo
r
3. A ground plane is suggested. If a ground plane is
not used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
4. Make the current trace from the LX pin to L to CO to
the PGND as short as possible.
de
d
In the AOZ1020 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the LX
pin, to the filter inductor, to the output capacitor and load,
and then return to the input capacitor through ground.
Current flows in the first loop when the high-side switch is
on. The second loop starts from inductor, to the output
capacitors and load, to the low-side NMOSFET. Current
flows in the second loop when the low-side NMOSFET is
on.
ew
D
Thermal Management and Layout
Consideration
ns
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
The AOZ1020A is a standard SO-8 package. Layout tips
are listed below for the best electric and thermal
performance. Figure 3 illustrates a PCB layout example
of the AOZ1020A.
ig
CO × RL
C C = --------------------RC
es
Equation above can also be simplified to:
om
m
en
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capacitor, output capacitor, and PGND pin of the AOZ1020.
ec
In the AOZ1020 buck regulator circuit, the major power
dissipating components are the AOZ1020 and the output
inductor. The total power dissipation of converter circuit
can be measured by input power minus output power.
R
P total_loss = V IN × I IN – V O × I O
6. The LX pin is connected to internal PFET drain. It is
a low resistance thermal conduction path and the
most noisy switching node. Connect a copper plane
to the LX pin to help thermal dissipation. This
copper plane should not be too large otherwise
switching noise may be coupled to other parts of
the circuit.
7. Keep sensitive signal traces far away from the LX
pin.
ot
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
5. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
N
P inductor_loss = IO2 × R inductor × 1.1
The actual junction temperature can be calculated with
power dissipation in the AOZ1020 and thermal impedance from junction to ambient.
T junction = ( P total_loss – P inductor_loss ) × Θ JA
Rev. 1.5 December 2010
www.aosmd.com
Page 11 of 15
R3
ig
8 PGOOD
PGND 1
C1
ns
5V
C3
C2
AOZ1020
7 LX
AGND 3
6 EN
ew
D
Cd
VIN 2
es
L1
5 COMP
Rc
Cc
R2
Fo
r
N
FB 4
Vo
de
d
R1
N
ot
R
ec
om
m
en
Figure 3. AOZ1020A (SO-8) PCB Layout
Rev. 1.5 December 2010
www.aosmd.com
Page 12 of 15
AOZ1020
Package Dimensions, SO-8L
D
Gauge Plane
Seating Plane
e
0.25
8
E1
ew
D
h x 45°
1
es
ig
E
ns
L
Fo
r
N
7° (4x)
C
θ
A2 A
0.1
om
m
en
de
d
A1
b
R
ec
2.20
5.74
N
ot
1.27
0.80
Unit: mm
Dimensions in millimeters
Symbols
A
Min.
1.35
A1
A2
0.10
1.25
b
c
D
0.31
0.17
4.80
E1
e
E
3.80
h
L
θ
Nom.
Max.
1.65
—
1.50
—
1.75
—
4.90
0.25
5.00
0.25
1.65
0.51
3.90
4.00
1.27 BSC
5.80
6.00
6.20
0.25
—
0.50
0.40
—
1.27
0°
—
8°
Dimensions in inches
Symbols
A
Min.
0.053
Nom.
0.065
Max.
0.069
A1
A2
0.004
0.049
—
0.059
0.010
0.065
b
c
D
0.012
0.007
0.189
—
—
0.193
0.020
0.010
0.197
E1
e
E
0.150
h
L
0.010
0.016
—
—
0.020
0.050
θ
0°
—
8°
0.154 0.157
0.050 BSC
0.228 0.236 0.244
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.
4. Dimension L is measured in gauge plane.
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Rev. 1.5 December 2010
www.aosmd.com
Page 13 of 15
AOZ1020
Tape and Reel Dimensions
SO-8 Carrier Tape
P1
D1
See Note 3
P2
T
See Note 5
E1
E2
See Note 3
B0
A0
D0
P0
Feeding Direction
Unit: mm
K0
2.10
±0.10
D0
1.60
±0.10
D1
1.50
±0.10
E
12.00
±0.10
E2
5.50
±0.10
E1
1.75
±0.10
P0
8.00
±0.10
P2
2.00
±0.10
P1
4.00
±0.10
T
0.25
±0.10
D
B0
5.20
±0.10
SO-8 Reel
N
ew
A0
6.40
±0.10
Package
SO-8
(12mm)
es
K0
ig
ns
E
Fo
r
W1
N
K
de
M
V
om
m
en
R
S
d
G
W
W1
17.40
±1.00
K
H
10.60
ø13.00
+0.50/-0.20
S
2.00
±0.50
G
—
R
—
V
—
SO-8 Tape
R
ec
W
N
Tape Size Reel Size
M
12mm
ø330
ø330.00 ø97.00 13.00
±0.10 ±0.30
±0.50
H
N
ot
Leader/Trailer
& Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 1.5 December 2010
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min. or
125 empty pockets
Page 14 of 15
AOZ1020
Part Marking
AOZ1020AI
Z1020AI
FAYWLT
ig
ns
Part Number Code
es
Assembly Lot Code
ew
D
Year & Week Code
Fo
r
N
AOZ1020AIL
Z1020AI
Underscore denotes Green Product
Part Number Code
en
de
d
FAYWLT
Assembly Lot Code
Year & Week Code
ec
om
m
Fab & Assembly Location
R
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
ot
LIFE SUPPORT POLICY
N
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.5 December 2010
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
www.aosmd.com
Page 15 of 15
工商网监
湘ICP备2023018690号
