AOZ1073
EZBuck™ 3A Synchronous Buck Regulator
General Description
Features
The AOZ1073 is a synchronous high efficiency, simple
to use, 3A buck regulator. The AOZ1073 works from a
4.5V to 16V input voltage range, and provides up to 3A
of continuous output current with an output voltage
adjustable down to 0.8V.
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The AOZ1073 comes in an SO-8 packages and is rated
over a -40°C to +85°C ambient temperature range.
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4.5V to 16V operating input voltage range
Synchronous rectification: 85mΩ internal high-side
switch and 30mΩ Internal low-side switch
High efficiency: up to 95%
Internal soft start
Output voltage adjustable to 0.8V
3A continuous output current
Fixed 500kHz PWM operation
Cycle-by-cycle current limit
Pre-bias start-up
Short-circuit protection
Thermal shutdown
Output over voltage protection
Small size SO-8 package
Applications
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Point of load DC/DC conversion
PCIe graphics cards
Set top boxes
DVD drives and HDD
LCD panels
Cable modems
Telecom/networking/datacom equipment
Typical Application
VIN
C1
22µF
Ceramic
VIN
L1 4.7µH
EN
AOZ1073
R1
COMP
RC
CC
VOUT
LX
C2, C3
22µF Ceramic
FB
AGND
PGND
R2
Figure 1. 3.3V/3A Buck Regulator
Rev. 1.1 September 2008
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Page 1 of 15
AOZ1073
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1073AIL
-40°C to +85°C
SO-8
Green (Halogen Free)
• All AOS products are offered in packages with Pb-free plating and compliant to RoHS standards.
• Parts marked as Green Products (with “L” suffix) use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
PGND
1
8
LX
VIN
2
7
LX
AGND
3
6
EN
FB
4
5
COMP
SO-8
(Top View)
Pin Description
Pin Number
Pin Name
1
PGND
Pin Function
Power ground. Electrically needs to be connected to AGND.
2
VIN
3
AGND
4
FB
5
COMP
6
EN
The enable pin is active HIGH. Connect it to VIN if not used and do not leave it open.
7, 8
LX
PWM outputs connection to inductor.
Rev. 1.1 September 2008
Supply voltage input. When VIN rises above the UVLO threshold the device starts up.
Reference connection for controller section. Also used as thermal connection for controller section.
Electrically needs to be connected to PGND.
The FB pin is used to determine the output voltage via a resistor divider between the output and
GND.
External loop compensation pin.
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Page 2 of 15
AOZ1073
Block Diagram
VIN
UVLO
& POR
EN
Internal
+5V
5V LDO
Regulator
OTP
+
ISen
–
Reference
& Bias
Softstart
Q1
ILimit
+
+
0.8V
EAmp
FB
–
–
PWM
Comp
PWM
Control
Logic
+
Level
Shifter
+
FET
Driver
LX
Q2
COMP
+
0.2V
500kHz/68kHz
Oscillator
–
+
0.96V
Frequency
Foldback
Comparator
OVP
Comparator
–
AGND
PGND
Absolute Maximum Ratings
Recommend Operating Ratings
Exceeding the Absolute Maximum Ratings may damage the
device.
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Parameter
Rating
Parameter
Supply Voltage (VIN)
18V
Supply Voltage (VIN)
LX to AGND
-0.7V to VIN+0.3V
Output Voltage Range
EN to AGND
-0.3V to VIN+0.3V
Ambient Temperature (TA)
FB to AGND
-0.3V to 6V
COMP to AGND
-0.3V to 6V
PGND to AGND
-0.3V to 0.3V
Junction Temperature (TJ)
+150°C
Storage Temperature (TS)
-65°C to +150°C
ESD Rating(1)
2.0kV
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Rev. 1.1 September 2008
Rating
Package Thermal Resistance (ΘJA
SO-8
4.5V to 16V
0.8V to VIN
-40°C to +85°C
)(2)
Package Thermal Resistance (ΘJC)
SO-8
Package Power Dissipation (PD)
@ 25°C Ambient
SO-8
87°C/W
30°C/W
1.15W
Note:
2. The value of ΘJA is measured with the device mounted on 1-in2
FR-4 board with 2oz. Copper, in a still air environment with
TA = 25°C. The value in any given application depends on the
user's specific board design.
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Page 3 of 15
AOZ1073
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.(3)
Symbol
VIN
VUVLO
Parameter
Conditions
Supply Voltage
Typ.
4.5
Max.
Units
16
V
VIN Rising
4.1
VIN Falling
3.7
Supply Current (Quiescent)
IOUT = 0, VFB = 1.2V, VEN > 1.2V
1.6
2.5
mA
IOFF
Shutdown Supply Current
VEN = 0V
3
20
µA
VFB
Feedback Voltage
TA = 25°C
0.8
0.812
V
IIN
IFB
Input Under-Voltage Lockout Threshold
Min.
0.788
V
Load Regulation
0.5
%
Line Regulation
1
%
Feedback Voltage Input Current
200
nA
ENABLE
VEN
EN Input Threshold
Off Threshold
On Threshold
VHYS
0.6
2
EN Input Hysteresis
100
V
mV
MODULATOR
Frequency
350
DMAX
fO
Maximum Duty Cycle
100
500
600
kHz
DMIN
Minimum Duty Cycle
GVEA
Error Amplifier Voltage Gain
500
V/V
GEA
Error Amplifier Transconductance
200
µA / V
%
6
%
PROTECTION
ILIM
Current Limit
VPR
Output Over-Voltage Protection Threshold
Over-Temperature Shutdown Limit
tSS
3.5
5.0
Off Threshold
960
On Threshold
940
TJ Rising
150
TJ Falling
100
Soft Start Interval
3
A
mV
°C
5
6.5
VIN = 12V
85
115
VIN = 5V
120
170
VIN = 12V
30
36
VIN = 5V
50
60
ms
PWM OUTPUT STAGE
High-Side Switch On-Resistance
Low-Side Switch On-Resistance
mΩ
mΩ
Note:
3. Specifications in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Rev. 1.1 September 2008
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Page 4 of 15
AOZ1073
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Light Load Operation
Full Load (CCM) Operation
Vin ripple
0.1V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
Vo ripple
20mV/div
IL
1A/div
IL
1A/div
VLX
10V/div
VLX
10V/div
1µs/div
1µs/div
Startup to Full Load
Short Circuit Protection
Vin
10V/div
LX
10V/div
Vo
2V/div
Vo
2V/div
IL
2A/div
lin
1A/div
1ms/div
100µs/div
50% to 100% Load Transient
Short Circuit Recovery
LX
10V/div
Vo Ripple
100mV/div
Vo
2V/div
lo
1A/div
IL
2A/div
100µs/div
Rev. 1.1 September 2008
2ms/div
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Page 5 of 15
AOZ1073
Efficiency
100
AOZ1073 Efficiency
AOZ1073 Efficiency
Efficiency (VIN = 12V) vs. Load Current
Efficiency (VIN = 5V) vs. Load Current
95
95
5.0V OUTPUT
90
3.3V OUTPUT
90
3.3V OUTPUT
Efficieny (%)
Efficieny (%)
100
85
1.8V OUTPUT
80
1.2V OUTPUT
85
80
75
75
70
70
65
1.8V
65
0
0.5
1.0
1.5
2.0
2.5
0
3.0
0.5
Load Current (A)
1.0
1.5
2.0
2.5
3.0
75
85
Load Current (A)
Thermal Derating Curves
Derating Curve at 12 Input
3.3
4
3.2
1.8V
OUTPUT
1.2V OUTPUT
3
3.3V
OUTPUT
2
1
Output Current (IO)
Output Current (IO)
Derating Curve at 5V/6V Input
5
3.1
1.2V, 1.8V, 3.3V, 5.0V OUTPUT
3.0
2.9
0
2.8
25
35
45
55
65
75
85
Ambient Temperature (TA)
Rev. 1.1 September 2008
25
35
45
55
65
Ambient Temperature (TA)
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Page 6 of 15
AOZ1073
Detailed Description
The AOZ1073 is a current-mode, step down regulator with
integrated high-side PMOS switch and a low-side NMOS
switch. It operates from a 4.5V to 16V input voltage range
and supplies up to 3A of load current. The duty cycle
can be adjusted from 6% to 100% allowing a wide output
voltage range. Features include enable control, Power-On
Reset, input under voltage lockout, output over voltage
protection, active high power good state, fixed internal
soft-start and thermal shut down.
The AOZ1073 is available in an SO-8 package.
Enable and Soft Start
The AOZ1073 has an internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In the soft start process, the output
voltage is typically ramped to regulation voltage in 4ms.
The 4ms soft start time is set internally.
The EN pin of the AOZ1073 is active HIGH. Connect the
EN pin to VIN if the enable function is not used. Pulling
EN to ground will disable the AOZ1073. Do not leave it
open. The voltage on the EN pin must be above 2V to
enable the AOZ1073. When voltage on the EN pin falls
below 0.6V, the AOZ1073 is disabled. If an application
circuit requires the AOZ1073 to be disabled, an open
drain or open collector circuit should be used to interface
to the EN pin.
Steady-State Operation
The AOZ1073 uses a P-Channel MOSFET as the highside switch. It saves the bootstrap capacitor normally
seen in a circuit which is using an NMOS switch. It allows
100% turn-on of the high-side switch to achieve linear
regulation mode of operation. The minimum voltage drop
from VIN to VO is the load current x DC resistance of
MOSFET + DC resistance of buck inductor. It can be
calculated by the equation below:
V O _MAX = V IN – I O × R DS ( ON )
where;
VO_MAX is the maximum output voltage,
VIN is the input voltage from 4.5V to 16V,
IO is the output current from 0A to 3A, and
RDS(ON) is the on resistance of internal MOSFET, the value is
between 97mΩ and 200mΩ depending on input voltage and
junction temperature.
Switching Frequency
The AOZ1073 switching frequency is fixed and set by
an internal oscillator. The practical switching frequency
could range from 350kHz to 600kHz due to device
variation.
Output Voltage Programming
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
The AOZ1073 integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error
voltage, which shows on the COMP pin, is compared
against the current signal, which is sum of inductor
current signal and ramp compensation signal, at the
PWM comparator input. If the current signal is less than
the error voltage, the internal high-side switch is on. The
inductor current flows from the input through the inductor
to the output. When the current signal exceeds the error
voltage, the high-side switch is off. The inductor current
is freewheeling through the internal low-side N-MOSFET
switch to output. The internal adaptive FET driver
guarantees no turn on overlap of both high-side and
low-side switch.
Rev. 1.1 September 2008
Comparing with regulators using freewheeling Schottky
diodes, the AOZ1073 uses freewheeling NMOSFET to
realize synchronous rectification. It greatly improves the
converter efficiency and reduces power loss in the
low-side switch.
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network. See the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation below:
R
V O = 0.8 × 1 + ------1-
R 2
Some standard value of R1, R2 and most used output
voltage values are listed in Table 1.
VO (V)
R1 (kΩ)
R2 (kΩ)
0.8
1.2
1.5
1.8
2.5
3.3
5.0
1.0
4.99
10
12.7
21.5
31.1
52.3
open
10
11.5
10.2
10
10
10
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Page 7 of 15
AOZ1073
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
Since the switch duty cycle can be as high as 100%, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on upper PMOS and
inductor.
Protection Features
The AOZ1073 has multiple protection features to prevent
system circuit damage under abnormal conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for
over current protection. Since the AOZ1073 employs
peak current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited cycle
by cycle.
When the output is shorted to ground under fault
conditions, the inductor current decays very slow during
a switching cycle because of VO = 0V. To prevent catastrophic failure, a secondary current limit is designed
inside the AOZ1073. The measured inductor current is
compared against a preset voltage which represents the
current limit, between 3.5A and 5.0A. When the output
current is more than current limit, the high side switch will
be turned off. The converter will initiate a soft start once
the over-current condition is resolved.
Output Over Voltage Protection (OVP)
The AOZ1073 monitors the feedback voltage: when the
feedback voltage is higher than 960mV, it immediately
turns-off the PMOS to protect the output voltage
overshoot at fault condition. When feedback voltage is
lower than 940mV, the PMOS is allowed to turn on in the
next cycle.
Application Information
The basic AOZ1073 application circuit is show in
Figure 1. Component selection is explained below.
Input Capacitor
The input capacitor must be connected to the VIN pin and
PGND pin of AOZ1073 to maintain steady input voltage
and filter out the pulsing input current. The voltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
The input ripple voltage can be approximated by equation
below:
IO
VO VO
∆V IN = ------------------ × 1 – ---------- × ---------f × C IN
V IN V IN
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a
buck circuit, the RMS value of input capacitor current
can be calculated by:
VO
VO
I CIN _RMS = I O × --------- 1 – ---------
V IN
V IN
if we let m equal the conversion ratio:
VO
---------- = m
V IN
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 2 below. It can be seen that when VO is half of VIN,
CIN is under the worst current stress. The worst current
stress on CIN is 0.5 x IO.
0.5
0.4
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.1V, the converter
starts operation. When input voltage falls below 3.7V,
the converter shuts down.
ICIN_RMS(m) 0.3
IO
0.2
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side PMOS if the junction temperature exceeds
150°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
Rev. 1.1 September 2008
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0.1
0
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
Page 8 of 15
AOZ1073
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics.
Note that the ripple current rating from capacitor manufactures are based on certain amount of life time.
Further de-rating may be necessary in practical design.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
VO
VO
∆I L = ----------- × 1 – ---------
f ×L
V IN
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
∆V O = ∆I L × ES R CO + ---------------------------
8×f ×C
O
where,
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
The peak inductor current is:
∆I
I Lpeak = I O + --------L2
1
∆V O = ∆I L × ---------------------------
8 × f × C
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20%
to 30% of output current.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
Rev. 1.1 September 2008
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be considered for long term reliability.
O
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
∆V O = ∆I L × ES R CO
For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum are recommended to
be used as output capacitors.
In a buck converter, output capacitor current is continuous.
The RMS current of output capacitor is decided by the
peak to peak inductor ripple current. It can be calculated
by:
∆I L
I CO _RMS = ---------12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and inductor ripple current is high, the output capacitor could be
overstressed.
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AOZ1073
Loop Compensation
The AOZ1073 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is the dominant pole can
be calculated by:
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When designing the compensation loop, converter stability under all
line and load condition must be considered.
1
f p1 = -----------------------------------2π × C O × R L
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
AOZ1073 operates at a frequency range from 350kHz
to 600kHz. It is recommended to choose a crossover
frequency equal or less than 40kHz.
The zero is an ESR zero due to output capacitor and its
ESR. It is can be calculated by:
f C = 40kHz
1
f Z 1 = -------------------------------------------------2π × C O × ESR CO
The strategy for choosing RC and CC is to set the
cross over frequency with RC and set the compensator
zero with CC. Using selected crossover frequency, fC,
to calculate R3:
where;
VO
2π × C 2
× ----------------------------R C = f C × ----------G ×G
V
CO is the output filter capacitor,
RL is load resistor value, and
FB
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter control loop transfer function to get the desired
gain and phase. Several different types of compensation
network can be used for the AOZ1073. In most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1073, FB pin and COMP pin are the inverting
input and the output of internal error amplifier. A series R
and C compensation network connected to COMP
provides one pole and one zero. The pole is:
G EA
f p2 = -----------------------------------------2π × C C × G VEA
EA
CS
where;
where fC is desired crossover frequency. For best performance,
fC is set to be about 1/10 of switching frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V, and
GCS is the current sense circuit transconductance, which is
6.68 A/V
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. C2 can is selected by:
1.5
C C = ----------------------------------2π × R 3 × f p1
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage; and
C2 is compensation capacitor in Figure 1.
The zero given by the external compensation network,
capacitor C2 and resistor R3, is located at:
The above equation can be simplified to:
CO × RL
C C = ---------------------R3
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
1
f Z 2 = ------------------------------------2π × C C × R C
Rev. 1.1 September 2008
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Page 10 of 15
AOZ1073
Thermal Management and Layout
Consideration
In the AOZ1073 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the LX
pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the anode of Schottky
diode, to the cathode of Schottky diode. Current flows in
the second loop when the low side diode is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capacitor, output capacitor, and PGND pin of the AOZ1073.
In the AOZ1073 buck regulator circuit, the major power
dissipating components are the AOZ1073 and the output
inductor. The total power dissipation of converter circuit
can be measured by input power minus output power.
P total _loss = V IN × I IN – V O × I O
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
P inductor _loss = IO2 × R inductor × 1.1
The actual junction temperature can be calculated with
power dissipation in the AOZ1073 and thermal impedance from junction to ambient.
T junction = ( P total _loss – P inductor _loss ) × Θ JA
The maximum junction temperature of AOZ1073 is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1073 under different ambient
temperature.
Rev. 1.1 September 2008
The thermal performance of the AOZ1073 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
The AOZ1073 is a standard SO-8 package. Layout tips
are listed below for the best electric and thermal
performance. Figure 3 illustrates a PCB layout example
of the AOZ1073.
1. Do not use thermal relief connection to the VIN
and the PGND pin. Pour a maximized copper area
to the PGND pin and the VIN pin to help thermal
dissipation.
2. Input capacitor should be connected as close as
possible to the VIN pin and the PGND pin.
3. A ground plane is suggested. If a ground plane is
not used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
4. Make the current trace from the LX pins to L to CO to
the PGND as short as possible.
5. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or VOUT.
6. The LX pins are connected to internal PFET drain.
They are a low resistance thermal conduction path
and the most noisy switching node. Connect a
copper plane to the LX pins to help thermal
dissipation. This copper plane should not be too
large otherwise switching noise may be coupled to
other parts of the circuit.
7. Keep sensitive signal traces far away from the LX
pins.
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Page 11 of 15
C1
PGND 1
C3
C2
AOZ1073
8 LX
L1
7 LX
AGND 3
6 EN
Cd
VIN 2
FB 4
Rc
R2
Cc
5 COMP
R1
Vo
Figure 3. AOZ1073 (SO-8) PCB Layout
Rev. 1.1 September 2008
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Page 12 of 15
AOZ1073
Package Dimensions, SO-8L
D
Gauge Plane
Seating Plane
e
0.25
8
L
E
E1
h x 45°
1
C
θ
7° (4x)
A2 A
0.1
b
A1
Dimensions in millimeters
2.20
5.74
1.27
0.80
Unit: mm
Symbols
A
A1
A2
b
c
D
E1
e
E
h
L
θ
Min.
1.35
0.10
1.25
0.31
0.17
4.80
3.80
Nom.
1.65
—
1.50
—
—
4.90
3.90
1.27 BSC
5.80
6.00
0.25
—
0.40
—
0°
—
Max.
1.75
0.25
1.65
0.51
0.25
5.00
4.00
6.20
0.50
1.27
8°
Dimensions in inches
Symbols
A
A1
A2
b
c
D
E1
e
E
h
L
θ
Min.
0.053
0.004
0.049
0.012
0.007
0.189
0.150
Nom. Max.
0.065 0.069
—
0.010
0.059 0.065
—
0.020
—
0.010
0.193 0.197
0.154 0.157
0.050 BSC
0.228 0.236 0.244
0.010
—
0.020
0.016
—
0.050
0°
—
8°
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.
4. Dimension L is measured in gauge plane.
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Rev. 1.1 September 2008
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Page 13 of 15
AOZ1073
Tape and Reel Dimensions
SO-8 Carrier Tape
P1
D1
See Note 3
P2
T
See Note 5
E1
E2
E
See Note 3
B0
K0
A0
D0
P0
Feeding Direction
Unit: mm
Package
SO-8
(12mm)
A0
6.40
±0.10
B0
5.20
±0.10
K0
2.10
±0.10
D0
1.60
±0.10
D1
1.50
±0.10
E
12.00
±0.10
SO-8 Reel
E1
1.75
±0.10
E2
5.50
±0.10
P0
8.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.10
T
0.25
±0.10
W1
S
G
N
M
K
V
R
H
W
N
W
Tape Size Reel Size
M
12mm
ø330
ø330.00 ø97.00 13.00
±0.50
±0.10 ±0.30
W1
17.40
±1.00
H
K
ø13.00
10.60
+0.50/-0.20
S
2.00
±0.50
G
—
R
—
V
—
SO-8 Tape
Leader/Trailer
& Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 1.1 September 2008
Components Tape
Orientation in Pocket
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Leader Tape
500mm min. or
125 empty pockets
Page 14 of 15
AOZ1073
Package Marking
AOZ1073AIL (Underlined, Halogen Free)
Z1073AI
Part Number Code
FAYWLT
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.1 September 2008
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Page 15 of 15
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