AOZ1240
EZBuck™ 2A Simple Buck Regulator
General Description
Features
The AOZ1240 is a high efficiency, simple to use, 2A buck
regulator flexible enough to be optimized for a variety of
applications. The AOZ1240 works from a 4.5V to 32V
input voltage range, and provides up to 2A of continuous
output current on each buck regulator output. The output
voltage is adjustable down to 0.8V.
●
4.5V to 32V operating input voltage range
●
70mΩ internal NFET, efficiency: up to 95%
●
Internal soft start
●
Output voltage adjustable down to 0.8V
●
2A continuous output current
●
Fixed 370kHz PWM operation
●
Cycle-by-cycle current limit
●
Short-circuit protection
●
Thermal shutdown
●
Small size, SO-8
Applications
●
Point of load DC/DC conversion
●
Set top boxes
●
DVD drives and HDD
●
LCD monitors & TVs
●
Cable modems
●
Telecom/networking/datacom equipment
Typical Application
C7
VIN
C1
22µF
VIN
BS
EN
L1
6.8µH
AOZ1240
R1
C2, C3
22µF x 2
FB
VBIAS
C4
VOUT
LX
COMP
GND
R2
RC
CC
Figure 1. 3.3V/2A Buck Regulator
Rev. 1.3 September 2010
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Page 1 of 15
AOZ1240
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1240AI
-40°C to +85°C
SO-8
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Pin Configuration
LX
1
8
VBIAS
BST
2
7
VIN
GND
3
6
EN
FB
4
5
COMP
SO-8
(Top View)
Pin Description
Pin Number
Pin Name
Pin Function
1
LX
PWM output connection to inductor. LX pin needs to be connected externally. Thermal connection
for output stage.
2
BST
Bootstrap voltage input. High side driver supply. Connected to 0.1µF capacitor between BST and
LX.
3
GND
Ground.
4
FB
5
COMP
6
EN
Enable pin. The enable pin is active HIGH. Connect EN pin to VIN if not used. Do not leave the EN
pin floating.
7
VIN
Supply voltage input. Range from 4.5V to 32V. When VIN rises above the UVLO threshold the
device starts up. All VIN pins need to be connected externally.
8
VBIAS
Rev. 1.3 September 2010
Feedback input. It is regulated to 0.8V. The FB pin is used to determine the PWM output voltage
via a resistor divider between the output and GND.
External loop compensation. Output of internal error amplifier. Connect a series RC network to
GND for control loop compensation.
Compensation pin of internal linear regulator. Place a 1µF capacitor between this pin and ground.
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AOZ1240
Block Diagram
VIN
+5V
VBIAS
UVLO
& POR
EN
5V LDO
Regulator
OTP
+
ISen
–
Reference
& Bias
Softstart
BST
ILimit
Q1
GM = 200µA / V
+
+
0.8V
EAmp
FB
–
–
PWM
Comp
PWM
Control
Logic
LX
+
COMP
+
0.2V
Frequency
Foldback
Comparator
Q2
370kHz / 24kHz
Oscillator
–
GND
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum Ratings may damage the device.
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Parameter
Supply Voltage (VIN)
Rating
Parameter
34V
LX to GND
-0.7V to VIN+0.3V
Supply Voltage (VIN)
EN to GND
-0.3V to VIN+0.3V
Output Voltage Range
FB to GND
-0.3V to 6V
COMP to GND
-0.3V to 6V
BST to GND
VBIAS to GND
VLX+6V
-0.3V to 6V
Junction Temperature (TJ)
+150°C
Storage Temperature (TS)
-65°C to +150°C
ESD Rating(1)
2kV
Ambient Temperature (TA)
Package Thermal Resistance (ΘJA)(2)
SO-8
Rating
4.5V to 32V
0.8V to VIN
-40°C to +85°C
105°C/W
Note:
2. The value of ΘJA is measured with the device mounted on 1-in2
FR-4 board with 2oz. Copper, in a still air environment with TA =
25°C. The value in any given application depends on the user's specific board design.
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Rev. 1.3 September 2010
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Page 3 of 15
AOZ1240
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, unless otherwise specified(3)
Symbol
VIN
Parameter
Conditions
Supply Voltage
Min.
Typ.
4.5
Max.
Units
32
V
Input Under-Voltage Lockout Threshold
VIN Rising
VIN Falling
Supply Current (Quiescent)
IOUT = 0, VFB = 1.2V, VEN > 2V
2
3
mA
IOFF
Shutdown Supply Current
VEN = 0V
3
20
µA
VFB
Feedback Voltage
0.8
0.818
VUVLO
IIN
IFB
4.3
4.1
0.782
V
V
Load Regulation
0.5
%
Line Regulation
0.08
%/V
Feedback Voltage Input Current
200
nA
ENABLE
VEN
EN Input Threshold
VHYS
EN Input Hysteresis
Off Threshold
On Threshold
0.6
2.5
200
V
mV
MODULATOR
Frequency
315
DMAX
Maximum Duty Cycle
85
DMIN
Minimum Duty Cycle
GVEA
Error Amplifier Voltage Gain
500
V/ V
GEA
Error Amplifier Transconductance
200
µA / V
fO
370
425
kHz
%
6
%
PROTECTION
ILIM
Current Limit
2.5
4.5
A
Over-Temperature Shutdown Limit
TJ Rising
TJ Falling
145
100
°C
fSC
Short Circuit Hiccup Frequency
VFB = 0V
24
kHz
tSS
Soft Start Interval
4
ms
PWM OUTPUT STAGE
RDS(ON)
High-Side Switch On-Resistance
High-Side Switch Leakage
70
VEN = 0V, VLX = 0V
100
mΩ
10
µA
Note:
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Rev. 1.3 September 2010
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Page 4 of 15
AOZ1240
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 24V, VOUT = 3.3V unless otherwise specified.
Light Load (DCM) Operation
Full Load (CCM) Operation
Vin ripple
0.1V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
Vo ripple
20mV/div
IL
1A/div
IL
1A/div
VLX
20V/div
VLX
20V/div
1μs/div
1μs/div
Startup to Full Load
Short Circuit Protection
Vo
2V/div
Vo
2V/div
lin
0.5A/div
2ms/div
lL
2A/div
200μs/div
50% to 100% Load Transient
Short Circuit Recovery
Vo
2V/div
Vo Ripple
200mV/div
lo
1A/div
2ms/div
200μs/div
Rev. 1.3 September 2010
IL
2A/div
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AOZ1240
Efficiency Curves
Efficiency
Efficiency
VIN = 5V
VIN = 12V
100
100
95
95
8.0V OUTPUT
5.0V OUTPUT
Efficieny (%)
Efficieny (%)
3.3V OUTPUT
90
85
1.8V OUTPUT
80
90
3.3V OUTPUT
85
80
75
75
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
Current (A)
1.0
1.5
2.0
2.5
3.0
Current (A)
Efficiency
VIN = 24V
100
95
Efficieny (%)
8.0V OUTPUT
5.0V OUTPUT
90
3.3V OUTPUT
85
80
75
0
0.5
1.0
1.5
2.0
2.5
3.0
Current (A)
Rev. 1.3 September 2010
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Page 6 of 15
AOZ1240
Detailed Description
Switching Frequency
The AOZ1240 is a current-mode step down regulator with
integrated high side NMOS switch. It operates from a 4.5V
to 32V input voltage range and supplies up to 2A of load
current. The duty cycle can be adjusted from 6% to 85%
allowing a wide range of output voltage. Features include
enable control, Power-On Reset, input under voltage
lockout, fixed internal soft-start and thermal shut down.
The AOZ1240 switching frequency is fixed and set by an
internal oscillator. The switching frequency is set 370khz.
The AOZ1240 is available in an SO-8 package.
Enable and Soft Start
The AOZ1240 has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In soft start process, the output
voltage is ramped to regulation voltage in typically 6.8ms.
The 6.8ms soft start time is set internally.
Connect the EN pin to VIN if enable function is not used.
Pull it to ground will disable the AOZ1240. Do not leave it
open. The voltage on EN pin must be above 2.5 V to
enable the AOZ1240. When voltage on EN pin falls
below 0.6V, the AOZ1240 is disabled. If an application
circuit requires the AOZ1240 to be disabled, an open
drain or open collector circuit should be used to interface
to EN pin.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin with a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R2 with equation below.
R 1⎞
⎛
V O = 0.8 × ⎜ 1 + -------⎟
R 2⎠
⎝
Some standard values for R1 and R2 for the most
commonly used output voltages are listed in Table 1.
Table 1.
VO (V)
R1 (kΩ)
R2 (kΩ)
0.8
1.0
Open
1.2
4.99
10
1.5
10
11.5
1.8
12.7
10.2
2.5
21.5
10
3.3
31.6
10
5.0
52.3
10
Steady-State Operation
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
The AOZ1240 integrates an internal N-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Since the N-MOSFET requires a
gate voltage higher than the input voltage, a boost
capacitor connected between LX pin and BST pin drives
the gate. The boost capacitor is charged while LX is low.
An internal 10Ω switch from LX to GND is used to insure
that LX is pulled to GND even in the light load. Output
voltage is divided down by the external voltage divider at
the FB pin. The difference of the FB pin voltage and
reference is amplified by the internal transconductance
error amplifier. The error voltage, which shows on the
COMP pin, is compared against the current signal, which
is sum of inductor current signal and ramp compensation
signal, at PWM comparator input. If the current signal is
less than the error voltage, the internal high-side switch
is on. The inductor current flows from the input through
the inductor to the output. When the current signal
exceeds the error voltage, the high-side switch is off. The
inductor current is freewheeling through the Schottky
diode to output.
Rev. 1.3 September 2010
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
Protection Features
The AOZ1240 has multiple protection features to prevent
system circuit damage under abnormal conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for
over current protection. Since the AOZ1240 employs
peak current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited
cycle-by-cycle.
The cycle-by-cycle current limit threshold is internally
set. When the load current reaches the current limit
threshold, the cycle by cycle current limit circuit turns
off the high side switch immediately to terminate the
current duty cycle. The inductor current stop rising.
The cycle-by-cycle current limit protection directly limits
inductor peak current. The average inductor current is
also limited due to the limitation on peak inductor current.
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AOZ1240
When cycle by cycle current limit circuit is triggered, the
output voltage drops as the duty cycle decreasing.
The AOZ1240 has internal short circuit protection to protect itself from catastrophic failure under output short circuit conditions. The FB pin voltage is proportional to the
output voltage. Whenever FB pin voltage is below 0.2V,
the short circuit protection circuit is triggered. To prevent
current limit running away, when comp pin voltage is
higher than 2.1 V, the short circuit protection is also triggered. As a result, the converter is shut down and hiccups at a frequency equals to 1/16 of normal switching
frequency. The converter will start up via a soft start once
the short circuit condition disappears. In short circuit protection mode, the inductor average current is greatly
reduced because of the low hiccup frequency.
Power-On Reset (POR)
if let m equal the conversion ratio:
VO
-------- = m
V IN
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2. It can be seen that when VO is half of
VIN, CIN is under the worst current stress. The worst
current stress on CIN is 0.5 x IO.
0.5
0.4
ICIN_RMS(m) 0.3
IO
0.2
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.3V, the converter
starts operation. When input voltage falls below 4.1V,
the converter will stop switching.
0.1
0
Thermal Protection
Application Information
The basic AOZ1240 application circuit is shown in
Figure 1. Component selection is explained below.
Input Capacitor
The input capacitor (C1 in Figure 1) must be connected
to the VIN pin and GND pin of the AOZ1240 to maintain
steady input voltage and filter out the pulsing input
current. The voltage rating of input capacitor must be
greater than maximum input voltage plus ripple voltage.
The input ripple voltage can be approximated by equation below:
IO
VO ⎞ VO
⎛
ΔV IN = ----------------- × ⎜ 1 – ---------⎟ × --------V IN⎠ V IN
f × C IN ⎝
1
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high ripple current rating. Depending on the
application circuits, other low ESR tantalum capacitor
or aluminum electrolytic capacitor may also be used.
When selecting ceramic capacitors, X5R or X7R type
dielectric ceramic capacitors are preferred for their better
temperature and voltage characteristics. Note that the
ripple current rating from capacitor manufactures is
based on certain amount of life time. Further de-rating
may be necessary for practical design requirement.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is,
VO ⎛
VO ⎞
ΔI L = ----------- × ⎜ 1 – ---------⎟
V IN⎠
f×L ⎝
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
Rev. 1.3 September 2010
0.5
m
Figure 2. ICIN vs. Voltage Conversion Ratio
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side NMOS if the junction temperature exceeds
145°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
VO ⎞
VO ⎛
I CIN_RMS = I O × --------- ⎜ 1 – ---------⎟
V IN ⎝
V IN⎠
0
The peak inductor current is:
ΔI L
I Lpeak = I O + -------2
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
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Page 8 of 15
AOZ1240
reduces RMS current through inductor and switches,
which results in less conduction loss.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked for
thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise, but they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
In a buck converter, output capacitor current is continuous.
The RMS current of output capacitor is decided by
the peak to peak inductor ripple current. It can be
calculated by:
ΔI L
I CO_RMS = ---------12
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
Schottky Diode Selection
The external freewheeling diode supplies the current to
the inductor when the high side NMOS switch is off. To
reduce the losses due to the forward voltage drop and
recovery of diode, Schottky diode is recommended to
use. The maximum reverse voltage rating of the chosen
Schottky diode should be greater than the maximum
input voltage, and the current rating should be greater
than the maximum load current.
Loop Compensation
The AOZ1240 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
1
ΔV O = ΔI L × ⎛ ESR CO + -------------------------⎞
⎝
8×f×C ⎠
O
where;
CO is output capacitor value and
ESRCO is the Equivalent Series Resistor of output capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused
by capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
1
ΔV O = ΔI L × ------------------------8×f×C
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
1
f p1 = ----------------------------------2π × C O × R L
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
O
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
ΔV O = ΔI L × ESR CO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric
type of ceramic, or other low ESR tantalum capacitor
or aluminum electrolytic capacitor may also be used as
output capacitors.
1
f Z1 = -----------------------------------------------2π × C O × ESR CO
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
Rev. 1.3 September 2010
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Page 9 of 15
AOZ1240
The compensation design is actually to shape the
converter close loop transfer function to get desired gain
and phase. Several different types of compensation
network can be used for AOZ1240. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1240, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
G EA
f p2 = ------------------------------------------2π × C C × G VEA
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200x10-6
A/V, and
GCS is the current sense circuit transconductance, which is
5.64 A/V
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. CC can is selected by:
1.5
C C = ----------------------------------2π × R C × f p1
The equation above can also be simplified to:
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
CO × RL
C C = --------------------RC
GVEA is the error amplifier voltage, and
CC is the compensation capacitor
The zero given by the external compensation network,
capacitor CC (C5 in Figure 1) and resistor RC (R1 in
Figure 1), is located at:
1
f Z2 = ----------------------------------2π × C C × R C
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover frequency is also called the converter
bandwidth. Generally a higher bandwidth means faster
response to load transient. However, the bandwidth
should not be too high due to system stability concern.
When designing the compensation loop, converter stability under all line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. It is recommended
to choose a crossover frequency less than 30kHz.
f C = 30kHz
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to
calculate RC:
2π × C O
VO
R C = f C × ---------- × -----------------------------V FB G EA × G CS
where;
fC is desired crossover frequency,
Rev. 1.3 September 2010
Thermal Management and Layout
Consideration
In the AOZ1240 buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts
from the input capacitors, to the VIN pin, to the LX pins,
to the filter inductor, to the output capacitor and load,
and then return to the input capacitor through ground.
Current flows in the first loop when the high side switch
is on. The second loop starts from inductor, to the output
capacitors and load, to the GND pin of the AOZ1240, to
the LX pins of the AZO1240. Current flows in the
second loop when the low side diode is on.
In PCB layout, minimizing the two loops area reduces
the noise of this circuit and improves efficiency. A
ground plane is recommended to connect input
capacitor, output capacitor, and GND pin of the
AOZ1240.
In the AOZ1240 buck regulator circuit, the three major
power dissipating components are the AOZ1240, external diode and output inductor. The total power
dissipation of converter circuit can be measured by input
power minus output power.
P total_loss = V IN × I IN – V O × I O
The power dissipation of inductor can be approximately
calculated by output current and DCR of the inductor.
P inductor_loss = IO2 × R inductor × 1.1
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AOZ1240
The power dissipation of the diode is:
Several layout tips are listed below for the best electric
and thermal performance. Figure 3 gives the example of
layout for the AOZ1240.
VO ⎞
⎛
P diode_loss = I O × V F × ⎜ 1 – ---------⎟
V IN⎠
⎝
The actual AOZ1240 junction temperature can be
calculated with power dissipation in the AOZ1240 and
thermal impedance from junction to ambient.
T junction = ( P total_loss – P inductor_loss ) × Θ JA
+ + T ambient
2. Input capacitor should be connected to the VIN pin
and the GND pin as close as possible.
3. Make the current trace from LX pins to L to Co to the
GND as short as possible.
The maximum junction temperature of AOZ1240 is
145°C, which limits the maximum load current capability.
The thermal performance of the AOZ1240 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
Rev. 1.3 September 2010
1. Do not use thermal relief connection to the VIN and
the GND pin. Pour a maximized copper area to the
GND pin and the VIN pin to help thermal dissipation.
4. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
5. Keep sensitive signal trace such as trace connected
with FB pin and COMP pin far away form the LX pins.
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C4
Cb
R1
C1
R2
AOZ1240
Figure 3. Layout Example for AOZ1240
Rev. 1.3 September 2010
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Page 12 of 15
AOZ1240
Package Dimensions, SO-8
D
Gauge Plane
Seating Plane
e
0.25
8
L
E
E1
h x 45°
1
C
θ
7° (4x)
A2 A
0.1
b
A1
Dimensions in millimeters
2.20
5.74
1.27
0.80
Unit: mm
Symbols
A
Min.
1.35
A1
A2
0.10
1.25
b
c
D
0.31
0.17
4.80
E1
e
E
3.80
h
L
θ
Nom.
Max.
1.65
—
1.50
—
1.75
—
4.90
0.25
5.00
0.25
1.65
0.51
3.90
4.00
1.27 BSC
5.80
6.00
6.20
0.25
—
0.50
0.40
—
1.27
0°
—
8°
Dimensions in inches
Symbols
A
Min.
0.053
Nom.
0.065
Max.
0.069
A1
A2
0.004
0.049
—
0.059
0.010
0.065
b
c
D
0.012
0.007
0.189
—
—
0.193
0.020
0.010
0.197
E1
e
E
0.150
h
L
0.010
0.016
—
—
0.020
0.050
θ
0°
—
8°
0.154 0.157
0.050 BSC
0.228 0.236 0.244
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.
4. Dimension L is measured in gauge plane.
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Rev. 1.3 September 2010
www.aosmd.com
Page 13 of 15
AOZ1240
Tape and Reel Dimensions, SO-8
SO-8 Carrier Tape
P1
D1
See Note 3
P2
T
See Note 5
E1
E2
E
See Note 3
B0
K0
A0
D0
P0
Feeding Direction
Unit: mm
Package
SO-8
(12mm)
A0
6.40
±0.10
B0
5.20
±0.10
K0
2.10
±0.10
D0
1.60
±0.10
D1
1.50
±0.10
E
12.00
±0.10
SO-8 Reel
E1
1.75
±0.10
E2
5.50
±0.10
P0
8.00
±0.10
P2
2.00
±0.10
P1
4.00
±0.10
T
0.25
±0.10
W1
S
G
N
M
K
V
R
H
W
W
N
Tape Size Reel Size
M
12mm
ø330
ø330.00 ø97.00 13.00
±0.10 ±0.30
±0.50
W1
17.40
±1.00
K
H
10.60
ø13.00
+0.50/-0.20
S
2.00
±0.50
G
—
R
—
V
—
SO-8 Tape
Leader/Trailer
& Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 1.3 September 2010
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min. or
125 empty pockets
Page 14 of 15
AOZ1240
Part Marking
Z1240AI
FAYWLT
Part Number
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
LEGAL DISCLAIMER
Applications or uses as critical components in life support devices or systems are not authorized. AOS does not
assume any liability arising out of such applications or uses of its products. AOS reserves the right to make
changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the
product for their intended application. Customer shall comply with applicable legal requirements, including all
applicable export control rules, regulations and limitations.
AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at:
http://www.aosmd.com/terms_and_conditions_of_sale
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.3 September 2010
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
www.aosmd.com
Page 15 of 15
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