AOZ1284PI-1_2

AOZ1284 EZBuck™ 4A Simple Buck Regulator General Description Features The AOZ1284 is a high voltage, high efficiency, simple to use, 4A buck regulator optimized for a variety of applications. The AOZ1284 works from a 3.0V to 36V input voltage range, and provides up to 4A of continuous output current. The output voltage is adjustable from 30V down to 0.8V.        The AOZ1284 integrates an N-channel high-side power MOSFET. The switching frequency can set from 200kHz to 2MHz with an external resistor. The soft-start time can be set with an external capacitor.      3.0V to 36V operating input voltage range 50mΩ internal NMOS Efficiency up to 95% Adjustable soft-start Output voltage adjustable from 0.8V to 30V 4A continuous output current Adjustable switching frequency from 200kHz to 2MHz Cycle-by-cycle current limit Short-circuit protection Over-voltage protection Over-temperature protection EPAD SO-8 package Applications       Point of load DC/DC conversion Set top boxes and cable modems Automotive applications DVD drives and HDDs LCD Monitors & TVs Telecom/Networking/Datacom equipment Typical Application Figure 1. 36V/4A Buck Regulator Rev. 0.5 March 2012 www.aosmd.com Page 1 of 14 AOZ1284 Ordering Information Part Number AOZ1284PI AOZ1284PI-1 Temperature Range Package Environmental -40°C to +85°C EPAD SO-8 Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. Pin Configuration LX 1 8 EN BST 2 Exposed PAD 7 SS GND 3 VIN 6 FB 5 COMP FSW 4 EPAD SO-8 (Top View) Pin Description Part Number 1 2 Pin Name LX BST 3 4 5 6 GND FSW COMP FB 7 8 Exposed PAD SS EN VIN Rev. 0.5 March 2012 Pin Function PWM Output Pin. Connect to inductor. Bootstrap Voltage Pin. Driver supply for High Side NMOS. Connected to 100nF capacitor between BST and LX. Ground Pin. Frequency Bias Pin. Connect to resistor to determine switching frequency. Compensation Pin. Connect to Resistor and Capacitor for system stability. Feedback Pin. It is regulated to 0.8V. The FB pin is used to determine the PWM output voltage via a resistor divider between the Output and Ground. Soft Start Pin. Enable Pin. Supply Voltage Pin. www.aosmd.com Page 2 of 14 AOZ1284 Functional Block Absolute Maximum Ratings Recommended Operating Ratings Exceeding the Absolute Maximum Ratings may damage the device. This device is not guaranteed to operate beyond the Recommended Operating Ratings. Parameter Supply Voltage (VIN) LX to GND EN, SS, FB and COMP to GND BST to GND Junction Temperature (TJ) Storage Temperature (TS) ESD Rating HB Model(1) Parameter Supply Voltage (VIN) Output Voltage (VOUT) Ambient Temperature (TA) Package Thermal Resistance EPAD SO-8 (JA) Rating 40V -0.7V to VIN+0.3V -0.3V to +6V -0.3V to VLX+6V +150°C -65°C to +150°C 2kV Rating 3.0V to 36V 0.8V to VIN*0.85V -40°C to +85°C 50°C/W Note: 1. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5kΩ in series with 100pF. Rev. 0.5 March 2012 www.aosmd.com Page 3 of 14 AOZ1284 Electrical Characteristics TA = 25°C, VIN = 12V, VEN = 3V, VOUT = 3.3V, unless otherwise specified. Specifications in BOLD indicate a temperature range of -40 °C to +85 °C. Symbol Parameter VIN VUVLO Supply Voltage Input Under-Voltage Lockout Threshold IIN Supply Current (Quiescent) IOFF VFB VFB_LOAD VFB_LINE IFB Shutdown Supply Current Feedback Voltage Load Regulation Line Regulation Feedback Voltage Input Current Conditions Min. Typ. 3 VIN rising VIN falling IOUT = 0, VFB = 1V, VEN >1.2V VEN = 0V TA=25oC 0.4A < Load < 3.6A Io=2A VFB = 800mV Max Units 36 2.9 V 2.3 1 788 800 0.5 0.03 0.5 V 1.5 mA 10 812 µA mV % %/V µA 1 Enable VEN_OFF VEN_ON EN Input Threshold VEN_HYS EN Input Hysteresis Off threshold On threshold 0.4 1.2 V 200 mV 5 5.5 6 6.5 A 2 2.5 3 µA 160 0.8 200 1 87 150 500 170 4.5 240 1.2 kHz MHz % ns V/V µA/V A/V 10 µA 70 mΩ Current Limit Peak Current Limit 1284 1284-1 Soft Start (SS) ISS Soft Start Source Current Modulator fO Frequency DMAX TON_MIN GVEA GEA GCS Maximum Duty Cycle Minimum On Time Error Amplifier Voltage Gain Error Amplifier Transconductance Current Sense Circuit Transconductance, RF = 270kΩ RF = 46.6kΩ fO = 1MHz Power Stage Output ILEAKAGE NMOS Leakage RDSON1 NMOS On- Resistance VEN=0V, VLX=0V 50 Thermal Protection TSD Thermal Shutdown Threshold 145 °C TSD_HYS Thermal Shutdown Hysteresis 45 °C Rev. 0.5 March 2012 www.aosmd.com Page 4 of 14 AOZ1284 Typical Performance Characteristics TA = 25°C, VIN = 24V, VEN = 5V, VOUT = 5V, unless otherwise specified. Rev. 0.5 March 2012 www.aosmd.com Page 5 of 14 AOZ1284 Efficiency Curves Rev. 0.5 March 2012 www.aosmd.com Page 6 of 14 AOZ1284 Detailed Description The AOZ1284 is a current-mode step down regulator with integrated high side NMOS switch. It operates from a 3V to 36V input voltage range and supplies up to 4A of load current. Features include enable control, Power-On Reset, input under voltage lockout, external soft-start and thermal shut down. The AOZ1284 is available in EPAD SO-8 package. Enable and Soft Start The AOZ1284 has external soft start feature to limit inrush current and ensure the output voltage ramps up smoothly to regulation voltage. A soft start process begins when the input voltage rises to 3V and voltage on EN pin is HIGH. In soft start process, a 2.5µA internal current source charges the external capacitor at SS. As the SS capacitor is charged, the voltage at SS rises. The SS voltage clamps the reference voltage of the error amplifier, therefore output voltage rising time follows the SS pin voltage. With the slow ramping up output voltage, the inrush current can be prevented. Minimum external soft-start capacitor 850pF is required, and the corresponding soft-start time is about 200µs. The EN pin of the AOZ1284 is active high. Connect the EN pin to a voltage between 1.2V to 5V if enable function is not used. Pull it to ground will disable the AOZ1284. Do not leave it open. The voltage on EN pin must be above 1.2V to enable the AOZ1284. When voltage on EN pin falls below 0.4V, the AOZ1284 is disabled. If an application circuit requires the AOZ1284 to be disabled, an open drain or open collector circuit should be used to interface to EN pin. Steady-State Operation Under steady-state conditions, the converter operates in fixed frequency and Continuous-Conduction Mode (CCM). The AOZ1284 integrates an internal N-MOSFET as the high-side switch. Inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power MOSFET. Since the NMOSFET requires a gate voltage higher than the input voltage, a boost capacitor connected between LX pin and BST pin drives the gate. The boost capacitor is charged while LX is low. An internal 10Ω switch from LX to GND is used to insure that LX is pulled to GND even in the light load. Output voltage is divided down by the external voltage divider at the FB pin. The difference of the FB pin voltage and reference is amplified by the internal transconductance error amplifier. The error voltage, which shows on the Rev. 0.5 March 2012 COMP pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at PWM comparator input. If the current signal is less than the error voltage, the internal high-side switch is on. The inductor current flows from the input through the inductor to the output. When the current signal exceeds the error voltage, the high-side switch is off. The inductor current is freewheeling through the Schottky diode to output. Switching Frequency The AOZ1284 switching frequency can be programmed by external resistor. External resistor value can be calculated by following formula. RF (k )  50000  5 k fO (kHz ) Some standard values of RF for most commonly used switching frequency are listed in Table 1. fO(Hz) 200k 500k 1M RF (kΩ) 270 100 46.6 Table 1 Output Voltage Programming Output voltage can be set by feeding back the output to the FB pin with a resistor divider network. In the application circuit shown in Figure 1 (Typical Application). The resistor divider network includes R2 and R3. Usually, a design is started by picking a fixed R3 value and calculating the required R2 with equation below.  R  VO  0.8  1  1   R2  Some standard value of R1, R2 for most commonly used output voltage values are listed below in Table 2. www.aosmd.com VO (V) 0.8 1.2 1.5 1.8 2.5 3.3 5.0 R1 (kΩ) 1.0 4.99 10 12.7 21.5 31.6 52.3 Table 2 R2 (kΩ) Open 10 11.5 10.2 10 10 10 Page 7 of 14 AOZ1284 Combination of R1 and R2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. Protection Features The AOZ1284 has multiple protection features to prevent system circuit damage under abnormal conditions. Over Current Protection (OCP) The sensed inductor current signal is also used for over current protection. Since the AOZ1284 employs peak current mode control, the COMP pin voltage is proportional to the peak inductor current. The COMP pin voltage is limited to be between 0.4V and 2.5V internally. The peak inductor current is automatically limited cycle by cycle. The cycle by cycle current limit threshold is internally set. When the load current reaches the current limit threshold, the cycle by cycle current limit circuit turns off the high side switch immediately to terminate the current duty cycle. The inductor current stop rising. The cycle by cycle current limit protection directly limits inductor peak current. The average inductor current is also limited due to the limitation on peak inductor current. When cycle by cycle current limit circuit is triggered, the output voltage drops as the duty cycle decreasing. The AOZ1284 has internal short circuit protection to protect itself from catastrophic failure under output short circuit conditions. The FB pin voltage is proportional to the output voltage. Whenever FB pin voltage is below 0.2V, the short circuit protection circuit is triggered. Application Information The basic AOZ1284 application circuit is shown in Figure 1. Component selection is explained below. Input capacitor The input capacitor (C1 in Figure 1) must be connected to the VIN pin and GND pin of the AOZ1284 to maintain steady input voltage and filter out the pulsing input current. The voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. The input ripple voltage can be approximated by equation below: VI N   IO V  1  O  f  CI N  VI N  VO   V IN  Since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. For a buck circuit, the RMS value of input capacitor current can be calculated by: ICIN _ RMS  IO  VO VIN  VO 1   VIN    if let m equal the conversion ratio: VO VIN m The relation between the input capacitor RMS current and voltage conversion ratio is calculated and shown below in Figure 2. It can be seen that when VO is half of VIN, CIN is under the worst current stress. The worst current stress on CIN is 0.5·IO. Power-On Reset (POR) A power-on reset circuit monitors the input voltage. When the input voltage exceeds 2.9V, the converter starts operation. When input voltage falls below 2.3V, the converter will stop switching. 0.5 0.5 0.4 0.3 I CIN_RMS ( m) IO 0.2 Thermal Protection An internal temperature sensor monitors the junction temperature. It shuts down the internal control circuit and high side NMOS if the junction temperature exceeds 145ºC. The regulator will restart automatically under the control of soft-start circuit when the junction temperature decreases to 100ºC. Rev. 0.5 March 2012 www.aosmd.com 0.1 0 0 0 0 0.5 m 1 1 Figure 2. ICIN vs. Voltage conversion ratio Page 8 of 14 AOZ1284 For reliable operation and best performance, the input capacitors must have current rating higher than ICINRMS at worst operating conditions. Ceramic capacitors are preferred for input capacitors because of their low ESR and high ripple current rating. Depending on the application circuits, other low ESR tantalum capacitor or aluminum electrolytic capacitor may also be used. When selecting ceramic capacitors, X5R or X7R type dielectric ceramic capacitors are preferred for their better temperature and voltage characteristics. Note that the ripple current rating from capacitor manufactures is based on certain amount of life time. Further de-rating may be necessary for practical design requirement. The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. De-rating needs to be considered for long term reliability. Output ripple voltage specification is another important factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It can be calculated by the equation below:  1 VO  I L   ESRCO  8  f  CO      where; Inductor The inductor is used to supply constant current to output when it is driven by a switching voltage. For given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: I L  VO  V  1  O f  L  VIN    CO is output capacitor value and ESRCO is the Equivalent Series Resistor of output capacitor. When low ESR ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simplified to: The peak inductor current is: ILPEAK  IO  VO  I L  I L 2 High inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. Low ripple current reduces inductor core losses. It also reduces RMS current through inductor and switches, which results in less conduction loss. When selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. The inductor takes the highest current in a buck circuit. The conduction loss on inductor needs to be checked for thermal and efficiency requirements. Surface mount inductors in different shape and styles are available from Wurth, Sumida, Coilcraft, and Murata. Shielded inductors are small and radiate less EMI noise. But they cost more than unshielded inductors. The choice depends on EMI requirement, price and size. Output Capacitor The output capacitor is selected based on the DC output voltage rating, output ripple voltage specification and ripple current rating. Rev. 0.5 March 2012 1 8  f  CO If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to: VO  I L  ESR CO For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum capacitor or aluminum electrolytic capacitor may also be used as output capacitors. In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calculated by: ICO _ RMS  I L 12 Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. www.aosmd.com Page 9 of 14 AOZ1284 Schottky Diode Selection The external freewheeling diode supplies the current to the inductor when the high side NMOS switch is off. To reduce the losses due to the forward voltage drop and recovery of diode, Schottky diode is recommended to use. The maximum reverse voltage rating of the chosen Schottky diode should be greater than the maximum input voltage, and the current rating should be greater than the maximum load current. Low Input operation When VIN is lower than 4.5V, such as 3.0V, an external 5V is required to add into the BST pin for proper operation. fP 2  where; GEA is the error amplifier transconductance, which is 200·10-6 A/V; GVEA is the error amplifier voltage gain, which is 500 V/V and CC is compensation capacitor. The zero given by the external compensation network, capacitor CC (C5 in Figure 1) and resistor RC (R1 in Figure 1), is located at: fZ 2  Loop Compensation The AOZ1284 employs peak current mode control for easy use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It greatly simplifies the compensation loop design. With peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. The pole is dominant pole and can be calculated by: fP 1  1 2  CC  RC To design the compensation circuit, a target crossover frequency fC for close loop must be selected. The system crossover frequency is where control loop has unity gain. The crossover frequency is also called the converter bandwidth. Generally a higher bandwidth means faster response to load transient. However, the bandwidth should not be too high due to system stability concern. When designing the compensation loop, converter stability under all line and load condition must be considered. Usually, it is recommended to set the bandwidth to be less than 1/10 of switching frequency. 1 2  CO  RL The zero is a ESR zero due to output capacitor and its ESR. It is can be calculated by: fZ1  GEA 2  CC  GVEA 1 2  CO  ESRCO The strategy for choosing RC and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC, to calculate RC: RC  fC  where; 2  CO VO  VFB GEA  GCS CO is the output filter capacitor; where; RL is load resistor value and fC is desired crossover frequency; ESRCO is the equivalent series resistance of output capacitor. VFB is 0.8V; The compensation design is actually to shape the converter close loop transfer function to get desired gain and phase. Several different types of compensation network can be used for AOZ1284. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. In the AOZ1284, FB pin and COMP pin are the inverting input and the output of internal transconductance error amplifier. A series R and C compensation network connected to COMP provides one pole and one zero. The pole is: Rev. 0.5 March 2012 GEA is the error amplifier transconductance, which is 200·10-6 A/V and GCS is the current sense circuit transconductance, which is 4.5 A/V. The compensation capacitor CC and resistor RC together make a zero. This zero is put somewhere close to the dominate pole fp1 but lower than 1/5 of selected crossover frequency. CC can is selected by: www.aosmd.com CC  1.5 2  RC  fP1 Page 10 of 14 AOZ1284 Equation above can also be simplified to: CC  CO  RL RC Easy to use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com. Thermal management and layout consideration In the AOZ1284 buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the VIN pin, to the LX pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. Current flows in the first loop when the high side switch is on. The second loop starts from inductor, to the output capacitors and load, to the GND pin of the AOZ1284, to the LX pins of the AOZ1284. Current flows in the second loop when the low side diode is on. In PCB layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. A ground plane is recommended to connect input capacitor, output capacitor, and GND pin of the AOZ1284. The thermal performance of the AOZ1284 is strongly affected by the PCB layout. Extra care should be taken by users during design process to ensure that the IC will operate under the recommended environmental conditions. Several layout tips are listed below for the best electric and thermal performance. The Figure 3 (a) and (b) give the example of layout for AOZ1284A and AOZ1284D respectively. 1. Do not use thermal relief connection to the VIN and the GND pin. Pour a maximized copper area to the GND pin and the VIN pin to help thermal dissipation. 2. Input capacitor should be connected to the VIN pin and the GND pin as close as possible. 3. Make the current trace from LX pins to L to Co to the GND as short as possible. 4. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. 5. Keep sensitive signal trace such as trace connected with FB pin and COMP pin far away from the LX pins. In the AOZ1284 buck regulator circuit, the three major power dissipating components are the AOZ1284, external diode and output inductor. The total power dissipation of converter circuit can be measured by input power minus output power. Ptotal _ loss  VIN  IIN  VO  IO The power dissipation of inductor can be approximately calculated by output current and DCR of inductor. Pinductor _ loss  IO 2  Rinductor  1.1 The power dissipation of diode is  V Pdiode _ loss  IO  VF  1  O  VIN    The actual AOZ1284 junction temperature can be calculated with power dissipation in the AOZ1284 and thermal impedance from junction to ambient. T junction  Ptotal _ loss  Pinductor _ loss  Pdiode _ loss   JA  Tambient The maximum junction temperature of AOZ1284 is 145ºC, which limits the maximum load current capability. Rev. 0.5 March 2012 www.aosmd.com Page 11 of 14 AOZ1284 Package Dimensions, SO-8 EP1 Gauge plane 0.2500 D0 C L L1 E2 E1 E3 E L1' D1 Note 5 D 7 (4x) A2 e B A A1 Dimensions in millimeters RECOMMENDED LAND PATTERN 3.70 2.20 5.74 2.71 2.87 Symbols Min. Nom. Max. Symbols Min. Nom. Max. A 1.40 1.55 1.70 A 0.055 0.061 0.067 A1 0.00 0.05 0.10 A1 0.000 0.002 0.004 A2 1.40 1.50 1.60 A2 0.055 0.059 0.063 B 0.31 0.406 0.51 B 0.012 0.016 0.020 C 0.17 — 0.25 C 0.007 — 0.010 D 4.80 4.96 5.00 D 0.189 0.195 0.197 D0 3.20 3.40 3.60 D0 0.126 0.134 0.142 D1 3.10 3.30 3.50 D1 0.122 0.130 0.138 E 5.80 6.00 6.20 E 0.228 0.236 0.244 e — 1.27 — e — 0.050 — E1 3.80 3.90 4.00 E1 0.150 0.153 0.157 E2 2.21 2.41 2.61 E2 0.087 0.095 0.103 E3 1.27 0.80 0.635 UNIT: mm 0.40 REF 0.016 REF E3 L 0.40 0.95 1.27 L 0.016 0.037 0.050 y — — 0.10 y — — 0.004 0° 3° 8° 0° 3° 8° — 0.04 0.12 — 0.002 0.005 | L1–L1' | L1 1.04 REF Notes: 1. Package body sizes exclude mold flash and gate burrs. 2. Dimension L is measured in gauge plane. 3. Tolerance 0.10mm unless otherwise specified. 4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. 5. Die pad exposure size is according to lead frame design. 6. Followed from JEDEC MS-012 Rev. 0.5 March 2012 Dimensions in inches www.aosmd.com | L1–L1' | L1 0.041 REF Page 12 of 14 AOZ1284 Tape and Reel Dimensions, SO-8 EP1 Carrier Tape P1 D1 P2 T E1 E2 E B0 K0 A0 D0 P0 Feeding Direction UNIT: mm Package A0 B0 K0 D0 D1 E E1 E2 P0 P1 P2 T SO-8 (12mm) 6.40 ±0.10 5.20 ±0.10 2.10 ±0.10 1.60 ±0.10 1.50 ±0.10 12.00 ±0.10 1.75 ±0.10 5.50 ±0.10 8.00 ±0.10 4.00 ±0.10 2.00 ±0.10 0.25 ±0.10 Reel W1 S G N M K V R H W UNIT: mm Tape Size Reel Size 12mm ø330 M N W W1 H K S G R V ø330.00 ±0.50 ø97.00 ±0.10 13.00 ±0.30 17.40 ±1.00 ø13.00 +0.50/-0.20 10.60 2.00 ±0.50 — — — Leader/Trailer and Orientation Trailer Tape 300mm min. or 75 empty pockets Rev. 0.5 March 2012 Components Tape Orientation in Pocket www.aosmd.com Leader Tape 500mm min. or 125 empty pockets Page 13 of 14 AOZ1284 Part Marking AOZ1284PI (SO-8) Z1284PI FAYWLT Part Number Code Assembly Lot Code Fab & Assembly Location Year & Week Code AOZ1284PI-1 (SO-8) Z1284PI1 FAYWLT Part Number Code Assembly Lot Code Fab & Assembly Location Year & Week Code This datasheet contains preliminary data; supplementary data may be published at a later date. Alpha and Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 0.5 March 2012 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 14 of 14