AOZ13987DI-02

AOZ13987DI-02 ECPower™ 20V 20mΩ Smart Protection Switch True Reverse Current Blocking General Description Features AOZ13987DI-02 is protection switch intended for applications that require reverse current protection. The input operating voltage range is from 3.4V to 22V, and both VIN and VOUT terminals are rated at 28V absolute maximum. The power switch is capable for 20 A surge current for 10ms. AOZ13987DI-02 provides undervoltage lockout, over-voltage, and over-temperature protection. The FLTB pin flags thermal shutdown and over-voltage faults.  8A continuous sink current  20 A peak current for 10ms @ 2% duty cycle  20 m typical ON resistance  3.4V to 22V operating input voltage  VIN and VOUT are rated 28 V Abs max  Ideal Diode True Reverse Current Blocking (IDTRCB)  Programmable soft-start  VIN Under-Voltage Lockout (UVLO)  VIN Over-Voltage Lockout (OVLO)  Thermal shutdown protection  IEC 61000-4-2: ±8kV on VIN and VOUT  IEC 61000-4-5: 35V on VIN, no cap  Thermally enhanced DFN3x3-12L package AOZ13987DI-02 is the ideal solution for multi-port TypeC PD current sinking application. The Ideal Diode True Reverse Current Blocking (IDTRCB) feature prevents VIN to rise due to reverse current flow from VOUT under all conditions. An internal soft-start circuit controls inrush current due to highly capacitive loads and the slew rate can be adjusted using an external capacitor. The integrated back-to-back MOSFET offer industry’s lowest ON resistance and highest SOA to safely handle high current and wide range of output capacitances on VOUT. The AOZ13987DI-02 is available in a thermally enhanced 3mm x 3mm DFN-12 package which can operate over -40°C to +125 °C junction temperature range. Applications  Thunderbolt/USB Type-C PD power switch  Notebook computers  Docking station/dongles  Power ORing Typical Application Electrically Isolated Thermal Pad VIN VBUS VOUT CIN TVS Diode USB Connector Charger COUT SS CAP CCAP AOZ13987DI-02 CSS 5V PD Controller RFLTB EN GND FLTB GND Rev. 1.0 December 2020 www.aosmd.com Page 1 of 17 AOZ13987DI-02 Dual Port Typical Application VBUS VOUT VIN CIN1 5V SS USB Connector 1 CCAP1 Charger COUT1 AOZ13987DI-02 CSS1 CAP RFLTB1 FLTB EN GND GND PD Controller VBUS VOUT VIN CIN2 COUT2 AOZ13987DI-02 SS USB Connector 2 CCAP2 CSS2 CAP FLTB EN RFLTB2 GND GND Rev. 1.0 December 2020 www.aosmd.com Page 2 of 17 AOZ13987DI-02 Ordering Information Part Number Junction Temperature Range Package Environmental AOZ13987DI-02 -40°C to +125°C DFN3x3-12L RoHS All AOS products are offered in packages with Pb-free plating and compliant to RoHS standards. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. Pin Configuration VOUT 1 EXP VOUT 2 12 NC 11 DNC DNC 3 10 VIN CAP 4 9 VIN EN 5 8 FLTB GND 6 7 SS DFN3x3-12L (Top Transparent View) Pin Description Pin Number Pin Name Pin Function 1, 2 VOUT 3 DNC Do Not Connect. Internally connected to Exposed Pad (EXP). 4 CAP Connect a 1nF capacitor to GND. 5 EN 6 GND Output pins. Connect to internal load. Enable active high. Ground. Soft-start pin. Connect a capacitor CSS from SS to GND to set the soft-start time. 7 SS 8 FLTB Fault Indicator, open-drain output. Pull low after a fault condition is detected. 9, 10 VIN Connect to adapter or power input. Place a 10 µF capacitor from VIN to GND. 11 DNC Do Not Connect. Internally connected to VIN. 12 NC No connect. EXP Exposed Thermal Pad. It is the common drain node for the power switches and it must be electrically isolated. Solder to a metal surface directly underneath the EXP and connect to floating copper thermal pads on multiple PCB layers through many VIAs. For best thermal performance, make the floating copper pads as large as possible. EXP Rev. 1.0 December 2020 www.aosmd.com Page 3 of 17 AOZ13987DI-02 Absolute Maximum Ratings(1) Recommend Operating Ratings Exceeding the Absolute Maximum ratings may damage the device. The device is not guaranteed to operate beyond the Maximum Operating Ratings. Parameter Parameter Rating VIN, VOUT to GND Rating Supply Voltage (VIN) -0.3V to +28V 3.4V to 22V EN, SS, FLTB to GND -0.3V to +6V EN, FLTB CAP to VIN -0.3V to +6V SS 0V to 5.5V CAP to VIN 0V to 5.5V Junction Temperature (TJ) +150 °C Storage Temperature (TS) -65°C to +150°C ESD Rating HBM All Pins ±4kV IEC 61000-4-2: VIN and VOUT Pins ±8kV 0V to 5.5V DC Switch Current (ISW) 0A to 8A Peak Switch Current (ISW) for 10ms @ 2% Duty Cycle 20 A Junction Temperature (TJ) Note: -40 °C to +125°C Package Thermal Resistance 3x3 DFN-12 (JC) 3x3 DFN-12 (JA) 1. Devices are inherently ESD sensitive, handling precautions are required. Human body model is a 100pF capacitor discharging through a 1.5k resistor. 2°C/W 35°C/W Electrical Characteristics TA = 25°C, VIN = 20 V, EN = 5V, CCAP = 1nF, CIN = 10µF, COUT = 10µF, CSS = 5.6nF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units 3.4 22 V 3.0 3.35 V VVIN Input Supply Voltage VUVLO Under-voltage Lockout Threshold VUVLO_HYS Under-voltage Lockout Hysteresis IVIN_ON Input Quiescent Current IVIN_OFF Input Shutdown Current IOUT = 0 A, EN = 0V 32 48 µA IVOUT_OFF Output Leakage Current VOUT = 20V, VIN = 0 V, EN = 0 V 32 48 µA IOUT = 1A 20 mΩ VIN = 5V, IOUT = 1A 21 mΩ RON_20V RON_5V Switch On Resistance(2) VIN rising 250 IOUT = 0 A VEN_H Enable Input High Threshold EN rising VEN_L Enable Input Low Threshold EN falling REN_LO EN Input Pull-down Resistance VFLTB_LO FLTB Pull-down Voltage 550 mV 750 1.4 0.6 475 µA V V 730 FLTB sinking 3mA 985 kΩ 0.3 V 25 V Input Over-voltage Protection VOVP Over-voltage Protection Threshold VIN rising tOVP_DEB Over-voltage Protection Debounce Time Latch off. No restart 512 µs 23 24 True Reverse Current Blocking VIDTRCB Ideal Diode TRCB Regulation Voltage VIN - VOUT 35 mV VTRCB Fast TRCB Threshold VOUT - VIN 50 mV tTRCB_DEL TRCB Delay Time 0.5 µs Note: 2. On resistance is tested under test mode to bypass ideal diode function. Rev. 1.0 December 2020 www.aosmd.com Page 4 of 17 AOZ13987DI-02 Electrical Characteristics TA = 25°C, VIN = 20 V, EN = 5V, CCAP = 1nF, CIN = 10µF, COUT = 10µF, CSS = 5.6nF, unless otherwise specified. Symbol Parameters Condition Min. Typ. Max. Units Dynamic Timing Characteristics tD_ON Turn-On Delay Time From EN rising edge to VOUT reaching 10% of VIN 8 ms tON Turn-On Rise Time VOUT from 10% to 90% of VIN 1.9 ms tOFF Turn-Off Fall Time From EN falling edge to IOUT = 0 A 32 µs Temperature rising. System latch off. 140 °C Thermal Shutdown Protection TSD Thermal Shutdown Threshold Functional Block Diagram EXP VIN CAP VOUT Gate Drive & Charge Pump Soft Start SS FLTB Control Logic UVLO OVLO TRCB EN VIN VOUT GND Rev. 1.0 December 2020 www.aosmd.com Page 5 of 17 AOZ13987DI-02 Timing Diagrams EN tON tD_ON 90% VOUT 10% Figure 1. Turn-on Delay and Turn-on Time VOVP VIN VOUT tOVP_DEB FLTB EN Figure 2. Over-Voltage Protection Rev. 1.0 December 2020 www.aosmd.com Page 6 of 17 AOZ13987DI-02 Typical Characteristics TA = 25°C, VIN = 20 V, EN = 5V, CIN = 10 µF, COUT = 10µF, CSS = 5.6nF, CCAP = 1nF, unless otherwise specified. VIN (2 V/div) VIN (5V/div) VOUT (2 V/div) VOUT (5V/div) IIN (5 A/div) I_IN (5 A/div) EN (5 V/div) EN (5 V/div) 2 ms/div 2 ms/div Figure 3. Soft-Start Delay (VIN = 5V, ROUT = 0.6Ω) Figure 4. Soft-Start Delay (VIN = 20V, ROUT = 2.8Ω) VIN (5 V/div) VIN (2 V/div) VOUT (5 V/div) VOUT (2 V/div) I_IN (5 A/div) I_IN (5 A/div) EN (5 V/div) EN (5 V/div) 1 ms/div 200µs/div Figure 5. Soft-Start Ramp (VIN = 5V, ROUT = 0.6Ω) Figure 6. Soft-Start Ramp (VIN = 20V, ROUT = 2.8Ω) VIN (5 V/div) VIN (2 V/div) VOUT (5 V/div) VOUT (2 V/div) I_IN (5 A/div) I_IN (5 A/div) EN (5 V/div) EN (5 V/div) 20 µs/div 20 µs/div Figure 7. Shutdown (VIN = 5V, ROUT = 0.6Ω) Rev. 1.0 December 2020 Figure 8. Shutdown (VIN = 20V, ROUT = 2.8Ω) www.aosmd.com Page 7 of 17 AOZ13987DI-02 Typical Characteristics (Continued) TA = 25°C, VIN = 20V, EN = 5V, CIN = 10 µF, COUT = 10 µF, CSS = 5.6 nF, CCAP = 1nF, unless otherwise specified. I_IN (2A/div) VIN (5V/div) Latched-Off VIN (1V/div) VOUT (5V/div) tOVP_DEB VOUT (1V/div) FLTB (5V/div) FLTB (5V/div) 500 µs/div 200 µs/div Figure 9. True Reverse Current Blocking (ROUT = 20Ω) Rev. 1.0 December 2020 Figure 10. Over-Voltage Protection www.aosmd.com Page 8 of 17 AOZ13987DI-02 Typical Characteristics (Continued) TA = 25°C, unless otherwise specified. 700 35 Shutdown Current (µA) Quiescent Current (µA) 30 600 500 400 25 20 15 10 5 0 300 2 4 6 8 10 12 14 16 18 0 20 2 4 6 8 12 10 14 16 VIN (V) Figure 11. Quiescent Current vs. VIN Figure 12. Shutdown Current vs. VIN 28 20 18 VIN (V) 30 27 25 ON Resistance (m) ON Resistance (m) 26 25 24 23 22 21 20 15 10 20 5 19 0 -40 18 4 6 8 10 12 16 14 18 20 0 20 40 80 60 100 Temperature (°C) Figure 13. ON Resistance vs. VIN Figure 14. ON Resistance vs. Temperature (VIN=20V) 900 200 800 180 160 700 600 500 400 300 140 120 100 80 60 200 40 100 20 0 -40 -20 VIN (V) VIN - VOUT (mV) VOUT Reverse Leakage Current (nA) 2 0 -20 0 20 40 60 80 100 0 1 2 3 4 5 6 7 Temperature (°C) Output Current (A) Figure 15. VOUT Reverse Leakage Current vs. Temperature Figure 16. VIN-VOUT vs. Output Current Rev. 1.0 December 2020 www.aosmd.com 8 Page 9 of 17 AOZ13987DI-02 Detailed Description The AOZ13987DI-02 is a high-side protection switch with programmable soft-start, over-voltage, and overtemperature protections. It is capable of operating from 3.4V to 22 V The internal power switch consists of back-to-back connected MOSFET. When the switch is enabled, the overall resistance between VIN and VOUT is only 20mΩ when IOUT > 3.5A, minimizing power loss and heat generation. The back-to-back configuration of MOSFET completely isolates VIN and VOUT when the switch is turned off, preventing leakage between the two pins. Power Delivery Capability During start-up, the voltage at VOUT linearly ramps up to the VIN voltage over a period of time set by the soft-start time. This ramp time is referred to as the soft-start time and is typically in milliseconds. Figure 16 illustrates the soft-start condition and power dissipation. Power = (VIN –VOUT) x I_SW Fully Enhanced 2 Power =(I_SW) x RON VO UT VIN Fast transient load increase With a high-reliability MOSFET as the power switch and superior packaging technology, the AOZ13987DI-02 is capable of dissipating this power. The power dissipated is: Power Dissipated = I_SW × (VIN –VOUT) To calculate the average power dissipation during the soft-start period: ½ of the input voltage should be used as the output voltage will ramp towards the input voltage, as shown in Figure 16. For example, if the output capacitance COUT is 10 µF, the input voltage VIN is 20 V, the soft-start time is 2 ms, and there is an additional 1A of system current (I_SYS), then the average power being dissipated by the part is: 20 V I SW = 10 uF  ----------- + 1 A = 1.1 A  2 ms Average Power Dissipation 20 V = 1.1 A  ----------- = 11 W 2 Referring to the SOA curve in Figure 17, the maximum power allowed for 2 ms is 100 W (5 A x 20V or 10A x 10V). The AOZ13987DI-02 power switch is robust enough to drive a large output capacitance with load in reasonable soft-start time. 1000.0 Time Figure 16. Soft-Start Power Dissipation During this soft-start time, there will be a large voltage across the power switch. Also, there will be current I_SW through the switch to charge the output capacitance. In addition, there may be load current to the downstream system as well. This total current is calculated as: 10.0 100µs 160µs 300µs 500µs 2ms R DS(ON) limited DC 1.0 T C = 25° C 0.1 0.0 0.01 0.1 1 10 100 Drain - Source Voltage, VDS (V) dVOUT I SW = C OUT  -------------------- + I SYS  dt  Figure 17. Safe Operating Area (SOA) Curves for Power Switch In the soft-start condition, the switch is operating in the linear mode, and power dissipation is high. The ability to handle this power is largely a function of the power MOSFET linear mode SOA and good package thermal performance RJC (Junction-to-Case) as the soft-start ramp time is in milliseconds. RJA (Junction-to-Ambient), which is more a function of PCB thermal performance, doesn't play a role. Rev. 1.0 December 2020 IDM limited 100.0 System load only Drain Current ID (A) I_SW Charging COUT and Supplying system load After soft-start is completed, the power switch is fully on, and it is at its lowest resistance. The power switch acts as a resistor. Under this condition, the power dissipation is much lower than the soft-start period. However, as this is a continuous current, a low on-resistance is required to minimize power dissipation. Attention must be paid to board layout so that losses dissipated in the sinking switch are dissipated to the PCB and hence the ambient. www.aosmd.com Page 10 of 17 AOZ13987DI-02 With a low on-resistance of 20 mΩ, the AOZ13987DI-02 provides the most efficient power delivery without much resistive power dissipation. While Type C power delivery is limited to 20V @ 5A or a 100W, many high-end laptops require peak currents far in excess of the 5 A. While the thermal design current (TDC) for a CPU may be low, peak current (ICCmax in the case of Intel and EDP in the case of AMD) of many systems is often 2 x thermal design current. These events are typical of short duration (< 2ms) and low duty cycle, but they are important for system performance as a CPU/GPU capable of operating at several GHz can boost its compute power in those 2ms peak current events. The AOZ13987DI-02 can handle such short, high current, transient pulses without any reliability degradation, thus enhancing the performance of highend systems when plugged into the Type C adapter. The shorter the pulse and the lower the duty cycle, the higher the pulse current that the part can sustain. The part has enough time to dissipate the heat generated from the pulse current with longer off-time, as shown in Figure 18. For example, AOZ13987DI-02 can maintain 20A for 10ms with a duty cycle of 2%. 35 The voltages at VIN pin are constantly monitored once the device is enabled. In case the voltage exceeds the OVLO threshold, over-voltage protection is activated: 1) If the power switch is on, it will be turned off after OVP debounce time (tOVP_DEB) to isolate VOUT from VIN; 2) OVP will prevent power switch to be turned on if it is in off state; In either case FLTB pin is pulled low to report the fault condition. The device can only be re-enabled by either toggling EN pin or cycling the input power supply. True Reverse Current Blocking When the device is ON with no load or under light load conditions, it regulates VOUT to be 35 mV below VIN. As the load current is increasing or decreasing, the device adjusts the gate drive to maintain the 35mV drop from VIN to VOUT. As the load current continues to increase the device increases the gate drive until the gate is fully turned on and VIN to VOUT drop is determined by IR drop through the MOSFET. If for any reason VOUT increases such that VIN to VOUT drop to less than 35 mV, the gate driver forces the switch to turn off. Duty Cycle 1% 30 Pulse Current (Amp) Over-Voltage Protection (OVP) Duty Cycle 2% Duty Cycle 5% 25 Duty Cycle 10% SOA Current Limit 20 15 The AOZ13987DI-02 also features a fast comparator that turns off the power switch upon detection of VOUT – VIN is higher than 50mV (VTRCB) after TRCB delay time (tTRCB_DEL). When the AOZ13987DI-02 is first enabled or during each auto-restart, power switch will be kept off if VOUT is 50mV higher than VIN. Thermal Shutdown Protection 10 0 2 4 6 8 10 12 14 Current Pulse Width (mS) 16 18 20 Figure 18. AOZ13987DI-02 Sinking Switch Pulsed Current vs. Duration for a Given Duty Cycle Enable The active high EN pin is the ON/OFF control for the power switch. The device is enabled when the EN pin is high and not in UVLO state. The EN pin must be driven to a logic high (VEN_H) or logic low (VEN_L) state to guarantee operation. AOZ13987DI-02 draws about 32 μA supply current when it is disabled. Input Under-Voltage Lockout (UVLO) The internal control circuit is powered from VIN. The under-voltage lockout (UVLO) circuit monitors the voltage at the input pin (VIN) and only allows the power switches to turn on when it is higher than 3.35V (VUVLO). When the die temperature reaches 140 °C, the power switch is turned off. The device can only be re-enabled by either toggling EN pin or cycling the input power supply. Soft-Start Slew-Rate Control When EN pin is asserted high, the slew rate control applies voltage on the gate of the power switch in a manner such that the output voltage is ramped up linearly until VOUT reaches VIN voltage level. The output ramps up time (tON) is programmable by an external soft-start capacitor (CSS). The following formula provides the estimated 10% to 90% ramp up time. t ON  VIN  C ss    100  24  0.0023  where CSS is in nF and tON is in µs. Rev. 1.0 December 2020 www.aosmd.com Page 11 of 17 AOZ13987DI-02 System Startup The device is enabled when EN ≥ 1.4V and VIN is higher than UVLO threshold (VUVLO). The device will check if any fault condition exists. If no fault exists, the power switch is turned on and VOUT is then ramped up after enable delay (tD_ON), controlled by the soft-start time (tON) until VOUT reaches VIN voltage level. Soft-start time can be programmed externally through SS input with a capacitor CSS to control in-rush current. In-rush Current Limit and SCP at Start Up AOZ13987DI-02 has the current limit and short circuit protection functions at start up. The current limit ramp increases linearly and reaches to a fixed current within 1.25ms. With this fixed current limit ramp, the inrush current can be effectively clamped to reduce the initial current spikes. At initial startup, the internal power switch carries large voltage close to Vin and has large power loss. To ensure the internal FET working in Safe Operation Area (SOA), a fixed timer is set to shut down the power switch if the inrush current is clamped by current limit ramp for about 512 µs continuously. This timer will be reset once the inrush current drops below the current limit ramp. For short circuit event, the part will shut down after this 512 µs timer is finished. In case of large output capacitors, the soft-start time needs to increase to avoid the large inrush current hit the current limit ramp for 512 µs. Both current limit and SCP shutdown are disabled after soft-start time is finished. The power switch will not be turned on and FLTB pin will be pulled low only for OVP and TSD conditions but not TRCB condition to indicate fault status of the device. The power switch will be turned on once TRCB condition no longer exists. The device will continuously monitor these fault conditions. In addition, the short circuit condition is being monitored during the soft start. Input Capacitor Selection The input capacitor prevents large voltage transients from appearing at the input, and provides the instantaneous current needed each time the switch turns on to charge output capacitors and to limit input voltage drop. It is also to prevent high-frequency noise on the power line from passing through to the output. The input capacitor should be located as close to the pin as possible. A 10μF ceramic capacitor is recommended. The USB specification limits the capacitance on VBUS to a maximum of 10μF. Use this maximum value for noise immunity due to the system and cable plug/unplug transients. Output Capacitor Selection The output capacitor has to supply enough current for a large peak current load that it may encounter during system transient. This bulk capacitance must be large enough to supply fast transient load in order to prevent the output from dropping. Power Dissipation Calculation Fault Protection The AOZ13987DI-02 offers multiple protection against the following fault conditions: VIN over-voltage (OVLO), Reverse Current Blocking when VOUT > VIN, and over temperature. Calculate the power dissipation for normal load condition using the following equation: Power Dissipated = RON × (IOUT)2 When the device is first enabled, the power switch is off and fault conditions are checked. If any of these conditions exist: 1. VIN is higher than the OVP threshold (VOVLO); 2. VOUT is 50mV (VFRCB) higher than VIN; 3. Die temperature is higher than thermal shutdown threshold (TSD); Rev. 1.0 December 2020 www.aosmd.com Page 12 of 17 AOZ13987DI-02 Layout Guidelines AOZ13987DI-02 is a protection switch designed deliver high current. Layout is critical to remove the heat generated by this current. For the most efficient heat sinking, connect as much copper as possible to the exposed pad. The exposed pad is the common drain of the power switch which must be electrically isolated. On the top layer expand the exposed pad island as much as possible for optimal thermal performance. The exposed pad copper plane must be electrically isolated. See example in Figure 19. Figure 20. Inner Layer Layout. Create electrically isolated thermal island with flooded plane. On the bottom layer, similar to the inner layers, create an isolated thermal island. Typically, there is more area available on the bottom area for a larger thermal pad. The top and bottom layers have better thermal performance than the inner layers because they are exposed to the atmosphere. See example in Figure 21. Figure 19. Top Layer Layout. Maximum number of VIAs from top layer exposed pad to inner layer. There are two ways to create thermal islands on the inner layers as showed in Figure 20. The more layers that have these electrically isolated thermal heat sink islands the better the thermal performance will be. Connect all isolated thermal island (top, inner layers and bottom) together with as many VIAs as possible. Figure 21. Bottom Layer Layout. Create a large electrically isolated thermal pad. Rev. 1.0 December 2020 www.aosmd.com Page 13 of 17 AOZ13987DI-02 Package Dimensions, DFN3x3-12L Rev. 1.0 December 2020 www.aosmd.com Page 14 of 17 AOZ13987DI-02 Tape and Reel Dimensions, DFN3x3-12L Carrier Tape Reel Rev. 1.0 December 2020 www.aosmd.com Page 15 of 17 AOZ13987DI-02 Tape and Reel Dimensions, DFN3x3-12L DFN3x3 EP TAPE Leader / Trailer & Orientation Rev. 1.0 December 2020 www.aosmd.com Page 16 of 17 AOZ13987DI-02 Part Marking AOZ13987DI-02 DFN 3x3 BS02 YWLT Option Code Special Code Part Number Code Assembly Lot Code Year & Week Code LEGAL DISCLAIMER Applications or uses as critical components in life support devices or systems are not authorized. AOS does not assume any liability arising out of such applications or uses of its products. AOS reserves the right to make changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the product for their intended application. Customer shall comply with applicable legal requirements, including all applicable export control rules, regulations and limitations. AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at: http://www.aosmd.com/terms_and_conditions_of_sale LIFE SUPPORT POLICY ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.0 December 2020 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 17 of 17