AOZ2253TQI-20
28V/8A Synchronous EZBuckTM Regulator
General Description
Features
The AOZ2253TQI-20 is a high-efficiency, easy-to-use
DC/DC synchronous buck regulator that operates up to
28V. The device is capable of supplying 8A of continuous
output current with an output voltage adjustable down to
0.8V (±1.0%).
Wide input voltage range
The AOZ2253TQI-20 integrates an internal linear
regulator to generate 5.3V VCC from input. If input
voltage is lower than 5.3V, the linear regulator operates
at low drop output mode, which allows the VCC voltage is
equal to input voltage minus the drop-output voltage of
the internal linear regulator.
– 14V to 28V
8A continuous output current
Output voltage adjustable down to 0.8V (±1.0%)
Low RDS(ON) internal NFETs
– 28m high-side
– 11m low-side
Constant On-Time with input feed-forward
Ceramic capacitor stable
Adjustable soft start
A proprietary constant on-time PWM control with input
feed-forward results in ultra-fast transient response while
maintaining relatively constant switching frequency over
the entire input voltage range.
Power Good output
The device features multiple protection functions such as
VCC under-voltage lockout, cycle-by-cycle current limit,
output over-voltage protection, short-circuit protection,
and thermal shutdown.
Thermal shutdown
The AOZ2253TQI-20 is available in a 4mm x 4mm QFN22L package and is rated over a -40°C to +85°C ambient
temperature range.
Integrated bootstrap diode
Cycle-by-cycle current limit
Short-circuit protection
Force PWM operation
Thermally enhanced 4mm x 4mm QFN-22L package
Applications
Compact desktop PCs
Graphics cards
Set-top boxes
LCD TVs
Cable modems
Point-of-load DC/DC converters
Telecom/Networking/Datacom equipment
Rev. 2.0 May 2019
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Page 1 of 17
AOZ2253TQI-20
Typical Application
Input
14V to 28V
IN
AIN
R3
100kΩ
Power Good
BST
VCC
C4
4.7μF
C2
22μF
C5
0.1μF
AOZ2253TQI-20
LX
PGOOD
Off On
EN
L1
3.3μH
Output
12V, 8A
R2
FB
C3
88μF
R1
AGND
SS
CSS
PGND
Power Ground
Analog Ground
Output Voltage vs Operating Frequency
Operating Frequency (kHz)
500
450
400
350
300
250
200
4
5
6
7
8
9
10
11
12
13
14
Output Voltage (V)
Rev. 2.0 May 2019
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Page 2 of 17
AOZ2253TQI-20
Recommended Start-Up Sequence
VIN
EN
50µs
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ2253TQI-20
-40°C to +85°C
22-Pin 4mm x 4mm QFN
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
VCC
BST
EN
LX
22
21
20
19
18
1
17
LX
FB 2
16
LX
15
PGND
14
PGND
NC 5
13
PGND
AIN 6
12
PGND
AGND 3
LX
8
IN
9
10
11
LX
7
IN
NC 4
LX
IN
IN
PGOOD
SS
Pin Configuration
22-Pin 4mm x 4mm QFN
(Top View)
Rev. 2.0 May 2019
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Page 3 of 17
AOZ2253TQI-20
Pin Description
Pin Number
Pin Name
Pin Function
1
PGOOD
Power Good Signal Output. PGOOD is an open-drain output used to indicate the status
of the output voltage. It is internally pulled low when the output voltage is 15% lower than
the nominal regulation voltage for or 20% higher than the nominal regulation voltage.
PGOOD is pulled low during soft-start and shut down.
2
FB
3
AGND
4, 5
NC
No Connect.
6
AIN
Supply to internal analog function. AIN pin must be connected to IN pins. For noisy
operation, it’s better to have a RC filter from IN to AIN for better noise immunity.
7, 8, 9
IN
Supply Input. IN is the regulator input. All IN pins must be connected together.
10, 11, 16, 17, 18
LX
Switching Node.
12, 13, 14, 15
PGND
Power Ground.
19
EN
Enable Input. The AOZ2253TQI-20 is enabled when EN is pulled high. The device shuts
down when EN is pulled low.
20
BST
Bootstrap Capacitor Connection. The AOZ2253TQI-20 includes an internal bootstrap
diode. Connect an external capacitor between BST and LX as shown in the Typical
Application diagram.
21
VCC
Supply Input for analog functions. Bypass VCC to AGND with a 4.7µF~10µF ceramic
capacitor. Place the capacitor close to VCC pin.
22
SS
Rev. 2.0 May 2019
Feedback Input. Adjust the output voltage with a resistive voltage-divider between the
regulator’s output and AGND.
Analog Ground.
Soft-Start Time Setting Pin. Connect a capacitor between SS and AGND to set the
soft-start time.
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Page 4 of 17
AOZ2253TQI-20
Absolute Maximum Ratings
Exceeding the Absolute Maximum Ratings may damage
the device.
Parameter
Maximum Operating Ratings
The device is not guaranteed to operate beyond the
Maximum Operating Ratings.
Rating
Parameter
IN, AIN to AGND
-0.3V to 30V
LX to AGND(2)
-0.3V to 30V
BST to AGND
-0.3V to 36V
SS, PGOOD, FB, EN, VCC to AGND
Supply Voltage (VIN)
Junction Temperature (TJ)
+150°C
-65°C to +150°C
ESD Rating(1)
0.8V to 0.85*VIN
Ambient Temperature (TA)
-40°C to +85°C
Package Thermal Resistance
(θJA)
(θJC)
-0.3V to +0.3V
Storage Temperature (TS)
14V to 28V
Output Voltage Range
-0.3V to 6V
PGND to AGND
Rating
32°C/W
4°C/W
2kV
Notes:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5k in series with 100pF.
2. LX to PGND Transient (t 2V, PFM
mode
IOFF
Shutdown Supply Current
VEN = 0V
VFB
Feedback Voltage
TA = 25°C
TA = 0°C to 85°C
IFB
Min.
3.2
0.792
0.788
0.16
mA
15
µA
0.800
0.800
0.808
0.812
V
V
Load Regulation
0.5
%
Line Regulation
1
%
FB Input Bias Current
200
nA
0.5
V
V
Enable
Off threshold
On threshold
VEN
EN Input Threshold
VEN_HYS
EN Input Hysteresis
100
mV
TON_MIN
Minimum On Time
60
ns
TOFF_MIN
Minimum Off Time
300
ns
1.4
Modulator
Soft-Start
ISS_OUT
SS Source Current
Rev. 2.0 May 2019
VSS = 0V
CSS = 0.001µF to 0.1µF
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7
11
15
µA
Page 5 of 17
AOZ2253TQI-20
Electrical Characteristics
TA = 25°C, VIN = 14V, EN = 5V, unless otherwise specified. Specifications in BOLD indicate a temperature range of
-40°C to 85°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max
Units
Power Good Signal
VPG_LOW
PGOOD Low Voltage
IOL = 1mA
PGOOD Leakage Current
0.5
V
±1
µA
VPGH
PGOOD Threshold
(Low Level to High Level)
FB rising
90
%
VPGL
PGOOD Threshold
(High Level to Low Level)
FB rising
FB falling
120
85
%
%
5
%
PGOOD Threshold Hysteresis
Under Voltage and Over Voltage Protection
VPL
Under Voltage Threshold
TPL
Under Voltage Delay Time
VPH
Over Voltage Threshold
FB falling
70
%
32
µs
FB rising
120
%
High-Side NFET On-Resistance
VIN = 14V
28
High-Side NFET Leakage
VEN = 0V, VLX = 0V
Low-Side NFET On-Resistance
VLX = 14V
Low-Side NFET Leakage
VEN = 0V
Power Stage Output
RDS(ON)
RDS(ON)
m
10
11
µA
m
10
µA
Over-current and Thermal Protection
ILIM
Current Limit
VCC = 5V
Thermal Shutdown Threshold
TJ rising
TJ falling
Rev. 2.0 May 2019
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12
A
150
100
°C
°C
Page 6 of 17
AOZ2253TQI-20
Functional Block Diagram
BST AIN
IN
PGood
LDO
VCC
EN
UVLO
Reference
& Bias
Error Comp
0.8V
SS
FB
ISENSE
(AC)
TOFF_MIN
Q
Timer
PG Logic
S
Q
R
FB
Decode
LX
ILIM Comp
ILIM
Current
Information
Processing
ISENSE
OTP
ISENSE (AC)
Vcc
TON
Q
ISENSE
Timer
EN
Light Load
Comp
Light Load
Threshold
ISENSE
PGND
Rev. 2.0 May 2019
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AGND
Page 7 of 17
AOZ2253TQI-20
Typical Performance Characteristics
TA = 25°C, VIN = 19V, VOUT = 12V, unless otherwise specified.
Normal Operation
Load Transient 0A to 8A
VLX
(20V/div)
ILX
(10A/div)
ILX
(10A/div)
V O ripple
(20mV/div)
V O ripple
(500mV/div)
10µs/div
2ms/div
Short Circuit Protection
Full Load Start-up
VLX
(20V/div)
VLX
(20V/div)
EN
(5V/div)
ILX
(20A/div)
ILX
(10A/div)
VO
(500mV/div)
VO
(10V/div)
2ms/div
20µs/div
Efficiency vs. Load Current
100
90
VOUT = 12V
80
Efficiency (%)
70
60
50
40
30
Vin = 19V
20
Vin = 24V
10
0
Rev. 2.0 May 2019
0
1.0
2.0
5.0
3.0
4.0
Output Current (A)
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6.0
7.0
8.0
Page 8 of 17
AOZ2253TQI-20
Detailed Description
The AOZ2253TQI-20 is a high-efficiency, easy-to-use,
synchronous buck regulator optimized for notebook
computers. The regulator is capable of supplying 8A of
continuous output current with an output voltage
adjustable down to 0.8V.
The input voltage of AOZ2253TQI-20 can be as low as
14V. The highest input voltage of AOZ2253TQI-20 can
be 28V. Constant on-time PWM with input feed-forward
control scheme results in ultra-fast transient response
while maintaining relatively constant switching frequency
over the entire input range. True AC current mode control
scheme guarantees the regulator can be stable with
ceramics output capacitor. Protection features include
VCC under-voltage lockout, cycle-by-cycle current limit,
output over voltage and under voltage protection, shortcircuit protection, and thermal shutdown.
The AOZ2253TQI-20 is available in 22-pin 4mm×4mm
QFN package.
VOUT
VSS
VSS = 3.3V
VSS = 0.8V
PGOOD
Figure 1. Soft Start Sequence
Enable
The AOZ2253TQI-20 has an embedded discharge path,
including a 100kΩ resistor and an M1 NMOS device. The
discharge path is activated when VIN(Input Voltage) is
high and VEN(Enable Voltage) is low. The internal circuit
of EN pin is shown in Figure 2.
Input Power Architecture
VS
The AOZ2253TQI-20 integrates an internal linear
regulator to generate 5.3V (±5%) VCC from input. If input
voltage is lower than 5.3V, the linear regulator operates
at low drop-output mode; the VCC voltage is equal to
input voltage minus the drop-output voltage of internal
linear regulator.
R1
VEN
Soft Start
The AOZ2253TQI-20 has external soft start feature to
limit in-rush current and ensure the output voltage ramps
up smoothly to regulate voltage. A soft start process
begins when VCC rises to 4.5V and voltage on EN pin is
HIGH. An internal current source charges the external
soft-start capacitor; the FB voltage follows the voltage of
soft-start pin (VSS) when it is lower than 0.8V. When VSS
is higher than 0.8V, the FB voltage is regulated by
internal precise band-gap voltage (0.8V). When VSS is
higher than 3.3V, the PGOOD signal is high. The softstart time for PGOOD can be calculated by the following
formula:
TSS(µs) = 330 x CSS(nF)
If CSS is 1nF, the soft start time will be 330µs; if CSS is
10nF, the soft start time will be 3.3ms.
EN
Detection
EN
REN_PL
100k
R2
EN1
EN Signal
EN1
M1
AGND
Figure 2. Enable Internal Circuit
There are two different enable control methods:
1. Connection to EN pin by an external resistor divider.
2. Direct connection to EN pin by an external power
source, Vs.
In the first condition, we must consider the internal pull
down resistance by using a divider circuit with an external
power source Vs and get VEN, the VEN can be calculated
by the following formula:
Ven
Rev. 2.0 May 2019
VIN
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R2 // REN _ PL
R1 ( R2 // REN PL )
• Vs
Page 9 of 17
AOZ2253TQI-20
When the VIN is high and VEN is high, the EN internal M1
is turned off, and then the pull down resistance is
removed for VEN, the VEN can be re-calculated by:
Ven
R2
• Vs
R1 R2
In the second condition, the AOZ2253TQI-20 will be
turned on when the VEN is higher than 1.4V, and will be
turned off when the VEN is lower than 0.5V. The simplified
schematic and timing sequence are shown in Figure 3.
Hysteresis
1.1V
EN pin
1.4V
0.5V
EN pin
EN
1.05V
EN
True Current Mode Control
The constant-on-time control scheme is intrinsically
unstable if output capacitor’s ESR is not large enough as
an effective current-sense resistor. Ceramic capacitors
usually can not be used as output capacitor.
The AOZ2253TQI-20 senses the low-side MOSFET
current and processes it into DC current and AC current
information using AOS proprietary technique. The AC
current information is decoded and added on the FB pin
on phase. With AC current information, the stability of
constant-on-time control is significantly improved even
without the help of output capacitor’s ESR; and thus, the
pure ceramic capacitor solution can be applicant. The
pure ceramic capacitor solution can significantly reduce
the output ripple (no ESR caused overshoot and
undershoot) and less board area design.
Current-Limit Protection
Figure 3. Enable Threshold Schematic and Timing
Sequence
Constant-On-Time PWM Control with Input
Feed-Forward
The control algorithm of AOZ2253TQI-20 is constant-ontime PWM control with input feed-forward. The simplified
control schematic is shown in Figure. 4. The high-side
switch on-time is determined solely by a one-shot whose
pulse width is inversely proportional to input voltage (IN).
The one-shot is triggered when the internal 0.8V is higher
than the combined information of FB voltage and the AC
current information of inductor, which is processed and
obtained through the sensed low-side MOSFET current
once it turns-on. The added AC current information can
help the stability of constant-on time control even with
pure ceramic output capacitors, which have very low
ESR. The AC current information has no DC offset, which
does not cause offset with output load change, which is
fundamentally different from other V2 constant-on time
control schemes.
IN
PWM
Programmable
One-Shot
–
Comp
+
The AOZ2253TQI-20 has the current-limit protection by
using RDS(ON) of the low-side MOSFET to be as current
sensing. To detect real current information, a minimum
constant off time (300ns typical) is implemented after a
constant-on time. If the current exceeds the current-limit
threshold, the PWM controller is not allowed to initiate a
new cycle. The actual peak current is greater than the
current-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit
characteristic and maximum load capability are a function
of the inductor value and input and output voltages. The
current limit will keep the low-side MOSFET on and will
not allow another high-side on-time, until the current in
the low-side MOSFET reduces below the current limit.
After 8 switching cycles, the AOZ2253TQI-20 considers
this is a true failed condition and thus turns-off both highside and low-side MOSFET and shuts down. The
AOZ2253TQI-20 enters hiccup mode to periodically
restart the part. When the current limit protection is
removed, the AOZ2253TQI-20 exits hiccup mode.
FB Voltage/
AC Current
Information
0.8V
Figure 4. Simplified Control Schematic
Rev. 2.0 May 2019
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Page 10 of 17
AOZ2253TQI-20
OVP Threshold
Inductor Current
Feedback Voltage
Feedback Voltage
Inductor Current
LX Voltage
LX Voltage
VIN+0.7V
-0.7V
Output Voltage
Output Voltage
VCC Voltage
VCC Voltage
Soft-Start Voltage
Soft-Start Voltage
Figure 5. OCP Timing Chart
Output Voltage Under-voltage Protection
If the output voltage is lower than 70% by over-current or
short circuit, AOZ2253TQI-20 will wait for 32µs (typical)
and turns-off both high-side and low-side MOSFET and
shuts down. When the output voltage under-voltage
protection is removed, the AOZ2253TQI-20 restarts
again.
Output Voltage Over-voltage Protection
The threshold of OVP is set 20% higher than 800mV.
When the VFB voltage exceeds the OVP threshold, highside MOSFET is turned off and low-side MOSFET is
turned on until VFB voltage is lower than 800mV.
Rev. 2.0 May 2019
Figure 6. OVP Timing Chart
Power Good Output
The power good (PGOOD) output, which is an open
drain output, requires the pull-up resistor. When the
output voltage is 15% below than the nominal regulation
voltage for, the PGOOD is pulled low. When the output
voltage is 20% higher than the nominal regulation
voltage, the PGOOD is also pull low.
When combined with the under-voltage-protection circuit,
this current-limit method is effective in almost every
circumstance.
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Page 11 of 17
AOZ2253TQI-20
Application Information
The basic AOZ2253TQI-20 application circuit is shown
on page 2. Component selection is explained below.
Input Capacitor
The input capacitor must be connected to the IN pins and
PGND pin of the AOZ2253TQI-20 to maintain steady
input voltage and filter out the pulsing input current. A
small decoupling capacitor, usually 4.7µF, should be
connected to the VCC pin and AGND pin for stable
operation of the AOZ2253TQI-20. The voltage rating of
input capacitor must be greater than maximum input
voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
VO VO
IO
V IN = ----------------- 1 – --------- --------V IN V IN
f C IN
Inductor
(1)
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
VO
VO
I CIN_RMS = I O --------- 1 – ---------
V IN
V IN
(2)
if let m equal the conversion ratio:
VO
-------- = m
V IN
(3)
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 7. It can be seen that when VO is half of VIN, CIN is
under the worst current stress. The worst current stress
on CIN is 0.5 x IO.
0.5
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
VO
VO
I L = ----------- 1 – ---------
V IN
fL
(4)
The peak inductor current is:
I L
I Lpeak = I O + -------2
(5)
High inductance gives low inductor ripple current but
requires a larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 30% to
50% of output current.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on the inductor needs to be checked
for thermal and efficiency requirements.
0.4
ICIN_RMS(m) 0.3
IO
0.2
Surface mount inductors in different shapes and styles
are available from Coilcraft, Elytone and Murata.
Shielded inductors are small and radiate less EMI noise,
but they do cost more than unshielded inductors. The
choice depends on EMI requirement, price and size.
0.1
0
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN-RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high ripple current rating. Depending on the
application circuits, other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used. When
selecting ceramic capacitors, X5R or X7R type dielectric
ceramic capacitors are preferred for their better
temperature and voltage characteristics. Note that the
ripple current rating from capacitor manufactures is
based on certain amount of life time. Further de-rating
may be necessary for practical design requirement.
0
0.5
m
1
Figure 7. ICIN vs. Voltage Conversion Ratio
Rev. 2.0 May 2019
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Page 12 of 17
AOZ2253TQI-20
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
V O = I L ESR CO + -------------------------
8fC
(6)
O
where,
CO is output capacitor value and ESRCO is the
Equivalent Series Resistor of output capacitor.
When a low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the
switching frequency dominates. Output ripple is mainly
caused by capacitor value and inductor ripple current.
The output ripple voltage calculation can be simplified to:
1
V O = I L ------------------------8fC
O
(7)
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
V O = I L ESR CO
(8)
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum are recommended
to be used as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current.
It can be calculated by:
I L
I CO_RMS = ---------12
Rev. 2.0 May 2019
(9)
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, the output capacitor could
be overstressed.
Thermal Management and Layout
Consideration
In the AOZ2253TQI-20 first loop starts from the input
capacitors, to the IN pin, to the LX pins, to the filter
inductor, to the output capacitor and load, and then
return to the input capacitor through ground. Current
flows in the first loop when the high side switch is on. The
second loop starts from inductor, to the output capacitors
and load, to the low side switch. Current flows in the
second loop when the low side low side switch is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input
capacitor, output capacitor, and PGND pin of the
AOZ2253TQI-20.
In the AOZ2253TQI-20 buck regulator circuit, the major
power dissipating components are the AOZ2253TQI-20
and the output inductor. The total power dissipation of
converter circuit can be measured by input power minus
output power.
P total_loss = V IN I IN – V O I O
(10)
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor and
output current.
P inductor_loss = IO2 R inductor 1.1
(11)
The actual junction temperature can be calculated with
power dissipation in the AOZ2253TQI-20 and thermal
impedance from junction to ambient.
(12)
T junction = P total_loss – P inductor_loss JA + T A
The maximum junction temperature of AOZ2253TQI-20
is 150ºC, which limits the maximum load current
capability.
The thermal performance of the AOZ2253TQI-20 is
strongly affected by the PCB layout. Extra care should be
taken by users during design process to ensure that the
IC will operate under the recommended environmental
conditions.
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Page 13 of 17
AOZ2253TQI-20
3. Input capacitors should be connected to the IN pin
and the PGND pin as close as possible to reduce the
switching spikes.
Layout Considerations
Several layout tips are listed below for the best electric
and thermal performance.
4. Decoupling capacitor CVCC should be connected to
VCC and AGND as close as possible.
1. The LX pins and pad are connected to internal low
side switch drain. They are low resistance thermal
conduction path and most noisy switching node.
Connected a large copper plane to LX pin to help
thermal dissipation.
5. Voltage divider R1 and R2 should be placed as close
as possible to FB and AGND.
6. Keep sensitive signal traces such as feedback trace
far away from the LX pins.
2. The IN pins and pad are connected to internal high
side switch drain. They are also low resistance thermal conduction path. Connected a large copper
plane to IN pins to help thermal dissipation. Pin 4,5
are NC pins and can be connected to IN pins directly
for more copper clad and better thermal dissipation.
It will help to reduce high side MOSFET temperature.
7. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
CVCC
Cb
L
VCC
BST
EN
LX
21
20
19
18
1
17
LX
FB
2
16
LX
AGND
3
15
PGND
NC
4
14
PGND
NC
5
13
PGND
AIN
6
12
PGND
8
9
10
11
IN
IN
LX
LX
IN
VIN
Rev. 2.0 May 2019
LX
IN
7
R1
22
R2
SS
VOUT
PGOOD
VOUT
Cout
PGND
Cin
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Page 14 of 17
AOZ2253TQI-20
Package Dimensions, QFN 4x4, 22 Lead EP2_S
D
Pin #1 Dot
By Marking
D2
L1
D3
L5
L5
L
e
E
E1
E3
E2
b
L4
L2
TOP VIEW
L3
D1
D1
BOTTOM VIEW
A1
A
A2
SIDE VIEW
RECOMMENDED LAND PATTERN
0.25
0.22
0.60
1.00
0.25
0.50
0.45
3.10
2.75
3.10
0.04
3.43
0.25
0.75
1.20
0.27
0.75
UNIT: MM
0.85
Dimensions in inches
Dimensions in millimeters
Symbols
Min.
Typ.
Max.
Symbols
Min.
Typ.
Max.
A
A1
A2
E
E1
E2
E3
D
D1
D2
D3
L
L1
L2
L3
L4
L5
b
e
0.80
0.00
0.90
—
0.2 REF
4.00
3.05
1.75
3.05
4.00
0.75
0.85
1.20
0.40
0.62
0.28
0.62
0.35
0.27
0.25
0.50 BSC
1.00
0.05
A
A1
A2
E
E1
E2
E3
D
D1
D2
D3
L
L1
L2
L3
L4
L5
b
e
0.031
0.000
0.035
—
0.008 REF
0.157
0.120
0.069
0.120
0.157
0.030
0.033
0.047
0.016
0.024
0.011
0.024
0.014
0.011
0.010
0.020 BSC
0.039
0.002
3.90
2.95
1.65
2.95
3.90
0.65
0.75
1.10
0.35
0.57
0.23
0.57
0.30
0.17
0.20
4.10
3.15
1.85
3.15
4.10
0.85
0.95
1.30
0.45
0.67
0.33
0.67
0.40
0.37
0.30
0.153
0.116
0.065
0.116
0.153
0.026
0.029
0.043
0.014
0.022
0.009
0.022
0.012
0.007
0.008
0.161
0.124
0.073
0.124
0.161
0.034
0.037
0.051
0.018
0.026
0.013
0.026
0.016
0.015
0.012
Notes:
1. Controlling dimensions are in millimeters. Converted inch dimensions are not necessarily exact.
2. Tolerance: ± 0.05 unless otherwise specified.
3. Radius on all corners is 0.152 max., unless otherwise specified.
4. Package wrapage: 0.012 max.
5. No plastic flash allowed on the top and bottom lead surface.
6. Pad planarity: ± 0.102
7. Crack between plastic body and lead is not allowed.
Rev. 2.0 May 2019
www.aosmd.com
Page 15 of 17
AOZ2253TQI-20
Tape and Reel Dimensions, QFN 4x4, 22 Lead EP2_S
Rev. 2.0 May 2019
www.aosmd.com
Page 16 of 17
AOZ2253TQI-20
Part Marking
AOZ2253TQI-20
(QFN 4x4)
ACTN
Part Number Code
Option Code
YWLT
Assembly Lot Code
Year & Week Code
LEGAL DISCLAIMER
Applications or uses as critical components in life support devices or systems are not authorized. AOS does not
assume any liability arising out of such applications or uses of its products. AOS reserves the right to make
changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the
product for their intended application. Customer shall comply with applicable legal requirements, including all
applicable export control rules, regulations and limitations.
AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at:
http://www.aosmd.com/terms_and_conditions_of_sale
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 2.0 May 2019
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Page 17 of 17
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