AOZ5276QI-01

AOZ5276QI High-Current, High-Performance Smart Power Stage General Description Features The AOZ5276QI is a general-purpose Smart Power Stage (SPS) consisting of two asymmetrical MOSFETs and an integrated driver for high current, high frequency DC-DC converters.  3V to 20V power supply range  30V HS MOSFET provides better system ruggedness  90A continuous output current – Up to 100A for 10ms on pulse – Up to 150A for 10µs on pulse The AOZ5276QI provides an output voltage signal (IMON), which represents the real-time module current with a gain of 5mV/A. The IMON signal can be directly used to replace inductor DCR sensing or resistor sensing in multiphase voltage regulator systems without the need for temperature compensation.  Optimized for switching frequency up to 1MHz  Integrated current monitor (5mV/A) with 5% accuracy over temperature  Integrated temperature monitor (8mV/°C) with 2% accuracy The AOZ5276QI also includes an accurate module temperature monitor (TMON). TMON is a voltage sourced signal with a gain of 8mV/°C.  Fault Indicator  Under-Voltage LockOut (UVLO) on VCC  Under-Voltage LockOut (UVLO) on VIN The MOSFETs are individually optimized for operation in the synchronous buck configuration. The High-Side (HS) MOSFET is optimized to achieve low capacitance and gate charge for fast switching with low duty cycle operation. The Low-Side (LS) MOSFET has ultra-low ON resistance to minimize conduction loss. The standard 5mm x 6mm QFN package is optimally designed to minimize parasitic inductance for minimal EMI signature.  High-Side MOSFET Over-Current and Short-Circuit Protection  Zero Current Detect Function (ZCD)  Over Temperature Protection (OTP)  Standard QFN5x6-39L package Applications  Server systems  High end CPU/GPU power stage  Communications Infrastructure Typical Application Circuit 3V ~ 20V OCSET/ZCD VIN BOOT VOS EN PWM PWM Controller Driver Logic and Delay TMON/FLT IMON REFIN CBOOT HS Driver PHASE VSWH LS Driver VOUT GL VCC Rev. 1.0 February 2022 L1 COUT AGND 5V CIN CVCC PVCC PGND CPVCC www.aosmd.com PGND Page 1 of 18 AOZ5276QI Ordering Information Part Number Junction Temperature Range Package PreOVP Environmental AOZ5276QI -40°C to 125°C QFN5x6-39L Active RoHS AOZ5276QI-01 -40°C to 125°C QFN5x6-39L Disabled RoHS AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. VOS 1 AGND 2 REFIN IMON OCSET/ZCD TMON/FLT EN PWM BOOT PHASE PHASE VIN Pin Configuration 39 38 37 36 35 34 33 32 31 30 29 VIN 28 VIN PGND VIN 40 25 VCC 3 PVCC 4 26 VIN PGND 5 25 VIN GL 6 27 VIN GL 24 PGND 41 23 PGND PGND 7 PGND 22 PGND 20 PGND 14 15 16 17 18 19 VSWH VSWH VSWH 13 VSWH 12 VSWH 11 VSWH 10 VSWH 20 PGND VSWH PGND 9 VSWH 21 PGND VSWH 8 QFN5x6-39L (Top View) Rev.1.0 February 2022 www.aosmd.com Page 2 of 18 AOZ5276QI Pin Description Pin Number Pin Name Pin Function 1 VOS 2 AGND 3 VCC 5 V Bias for Internal Logic Blocks. Ensure to position a 1 µF MLCC directly between VCC and AGND (Pin 2). 4 PVCC 5 V Power Rail for High-Side and Low-Side MOSFET Drivers. Ensure to position a 1µF MLCC directly between PVCC and PGND (Pin 5). 5, 40 PGND Power Ground for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF MLCC directly between PGND and PVCC (Pin 4). Output voltage sense. Signal Ground. 6, 41 GL 7, 8, 9, 20, 21, 22, 23, 24 PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET). 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 VSWH Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side MOSFET. 25, 26, 27, 28, 29, 30 VIN 31, 32 PHASE This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 33). 33 BOOT High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between BOOT and the PHASE (Pin 31 and 32). 34 PWM PWM input signal from Controller IC. This input is compatible with 3.3V and 5V Tri-State logic levels. 35 EN 36 37 Low-Side MOSFET Gate connection. This is for test purposes only. Power stage High Voltage Input (Drain connection of High-Side MOSFET). Output enable pin. When this pin is pulled to a logic low level, the IC disables most blocks. EN=HIGH enables all blocks inside IC and requires 4µs power up time. TMON/FLT Temperature Monitor and Fault Flag Pin. TMON/FLT will be pulled HI (~ 3.3 V) or LOW (0V) to indicate a fault condition (see Table 5). For multi-phase application, the TMON/FLT pin can be connected together as a common bus. The highest voltage representing the highest temperature among all phases will be sent to the PWM controller. No more than 470pF total capacitance can be directly connected across TMON/FLT and AGND (Pin 2). A higher capacitance load is allowed with a series resistor (~ 1kΩ) for up to 1nF. At 0°C and in normal operation, the output voltage is 0.6V with a temperature coefficient value of 8mV/°C. There is an internal pull up source to 3.3V when a fault condition occurs. OCSET/ZCD Setting control for OCP limit threshold and Zero Cross Detect function (ZCD). OCP limit threshold is detected and latched 120µs after device enabled. Refer to Table 3 for the resistor value for each current limit threshold level. After 120µs, the OCP limit is set and this pin becomes ZCD control only. ZCD is active when this pin is floating or pulled HI. IMON Current Monitor output signal referenced to REFIN (Pin 39). Connect the IMON output to the appropriate Current Sense input of the controller. No more than 47pF capacitance can be directly connected across IMON and REFIN pins. With a 100Ω series resistor, up to 470pF may be used. REFIN Input for external reference voltage for IMON (Pin 38). This voltage should be between 0.7 V and 2.0V. Nominal value is 1.2V. Place a low ESR ceramic capacitor (~ 0.1µF) from this pin to AGND (Pin 2). Connect REFIN to the appropriate Current Sense Reference output from the controller. 38 39 Rev.1.0 February 2022 www.aosmd.com Page 3 of 18 AOZ5276QI Functional Block Diagram VCC BOOT PVCC VIN REF/BIAS UVLO UVLO EN VCC Boot PWM Tri-State Logic PWM HS Sequencing and Propagation Delay Control VOS LS UVLO Fault Detect OCP OTP VSWH REFIN LS Gate PVCC LS Gate Driver VCC UVLO VIN UVLO IMON OCP Thermal Monitor CS GL PGND AGND VOS Rev.1.0 February 2022 Current Monitor Control Logic Thermal TMON/FLT Fault Detect VSWH Driver Logic Tri-State OCP/ZCD OCSET/ZCD PHASE HS Gate PHASE Check PWM 3.3V HS Gate Driver Level Shifter Enable www.aosmd.com Page 4 of 18 AOZ5276QI Absolute Maximum Ratings Recommended Operating Conditions Exceeding the Absolute Maximum ratings may damage the device. The device is not guaranteed to operate beyond the Maximum Recommended Operating Conditions. Parameter Parameter Rating Low Voltage Supply (VCC, PVCC) -0.3V to 6V -0.3V to 25V High Voltage Supply (VIN) Control Inputs (PWM, EN, REFIN, OCSET/ZCD, VOS) -0.3V to (VCC+0.3V) Output (TMON/FLT, IMON) -0.3V to (VCC+0.3V) -0.3V to 31V Bootstrap Voltage DC (BOOT-PGND) Bootstrap Voltage Transient (BOOT-PGND) -8V to 40V -0.3V to 6V BOOT Voltage Transient(1) (BOOT-PHASE/VSWH) -0.3V to 9V Switch Node Voltage DC (PHASE/VSWH) Switch Node Voltage Transient(1) (PHASE/VSWH) 4.5V to 5.5V Control Inputs (PWM, EN, OCSET/ZCD, VOS) 0V to VCC Output (TMON/FLT, IMON) 0V to 3.3V Operating Frequency 0.7V to 2.0V 200 kHz to 1MHz -8V to 33V (PGND-0.3V) to (PVCC+0.3V) Low-Side Gate Voltage Transient(2) (GL) (PGND-2.5V) to (PVCC+0.3V) 90A VSWH Current DC VSWH Current 10ms Pulse 100A VSWH Current 10µs Pulse 150A Storage Temperature (TS) 3V to 20V -0.3V to 25V Low-Side Gate Voltage DC (GL) -65°C to +150°C 150°C Max Junction Temperature (TJ) ESD Rating Low Voltage/ MOSFET Driver Supply (VCC, PVCC) Control Inputs (REFIN) (1) Bootstrap Voltage DC (BOOT-PHASE/VSWH) (3) High Voltage Supply (VIN) Rating ±2kV HBM ±1 kV CDM Notes: 1. Peak voltages can be applied for 10ns per switching cycle. 2. Peak voltages can be applied for 20ns per switching cycle. 3. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5k in series with 100pF. Rev.1.0 February 2022 www.aosmd.com Page 5 of 18 AOZ5276QI Electrical Characteristics(4) TJ = 25 °C to 125 °C. Typical values reflect 25°C junction temperature; VIN = 12V, VCC = PVCC = EN = 5V, unless otherwise specified. Min/Max values are guaranteed by test, design, or statistical correlation. Symbol Parameter General VIN Power Stage Power Supply VCC Low Voltage Bias Supply RJC (5) RJA(5) Thermal Resistance Conditions Min Typ 3 PVCC = VCC 4.5 Max Units 20 V 5.5 V PCB Temp = 100 °C 1.8 °C/W Fsw=600 kHz, VOUT =1 V 12.5 °C/W Input Supply and UVLO VCC_UVLO VCC_HYST VCC Under-Voltage Lockout VCC Rising VCC Hysteresis tVCC_DEL VCC Power On Delay From VCC UVLO release VIN_UVLO VIN Under-Voltage Lockout VIN Rising VIN_HYST VIN Hysteresis IVCC Control Circuit Bias Current IPVCC Drive Circuit Operating Current PWM Input VPWM_H Logic High Input Voltage VPWM_L Logic Low Input Voltage RPWM_DOWN RPWM_UP PWM Pin Input Resistance 3.4 3.8 4.2 400 2.2 2.4 V mV 200 µs 2.6 V 400 mV EN=0V, PWM= Floating 600 800 µA EN=5V, PWM= Floating 5 7 mA PWM = 300kHz, 20% Duty Cycle 15 mA PWM = 600kHz, 20% Duty Cycle 30 mA 2.7 0.65 V V Pull Down 10 k Pull Up 23 k VTRI PWM Tri-State Window VPMW_FLOAT PWM Tri-State Voltage Clamp tPMW_SKIP Minimum PWM Pulse Detection tPWMH_MIN Forced Minimum On Pulse 30 ns tPWML_SKIP Forced Minimum Off Pulse 50 ns 1.1 PWM = Floating 2.1 1.5 V V 10 ns EN Input VEN_ON Output Enable Threshold VEN_OFF Output Disable Threshold REN EN Input Resistance Pull-Down Resistor 100 k tPD_ENH Propagation Delay for EN: L  H PWM= GND, Delay from EN (L  H) to GL (L  H) 30 µs tPD_ENL Propagation Delay for EN: H  L PWM=GND, Delay from EN (H  L) to GL (H  L) 50 ns Gate Driver Timing tPDLU PWM to High-Side Gate PWM: HL, VSWH: HL 25 ns tPDLL PWM to Low-Side Gate PWM: L H, GL: H L 25 ns tPDHU Low-side to High-Side Gate Deadtime GL: H L, GH(6): L H 10 ns tPDHL High-Side to Low-side Gate Deadtime VSWH: H  1V, GL: L  H 10 ns tTSSHD Tri-State Shutdown Delay tTSEXIT Tri-State Propagation Delay tLGMIN Low-Side Minimum On-Time Rev. 1.0 February 2022 2.4 0.8 PWM: L  VTRI, GL: H  L and PWM: H  VTRI, VSWH: H  L PWM: VTRI  H, VSWH: L  H PWM: VTRI  L, GL: L  H ZCD enables www.aosmd.com V V 40 150 80 ns 30 ns ns Page 6 of 18 AOZ5276QI Electrical Characteristics(4) TJ = 25°C to 125°C. Typical values reflect 25°C junction temperature; VIN = 12V, VCC = PVCC = EN = 5 V, unless otherwise specified. Min/Max values are guaranteed by test, design, or statistical correlation. Symbol Parameter Conditions Min Typ Max Units IMON Timing and Operating Range tFALL_BLK VSWH Falling Blanking Time tPRO_DEL IMON to IL Propagation Delay BWIMON 250 L=150nH, Freq=600kHz, VOUT=1.8VIMON Valley to IL Valley 60 IMON Gain Bandwidth 5 7.5 VREFIN REFIN Voltage Range 0.7 1.2 VIMON IMON Voltage Range 0.3 CIMON Max IMON Output Capacitance Allowed Across IMON and REFIN 10 With 100Ω resistor in series ns 75 ns MHz 2.0 V 3 V 47 pF 470 pF IMON Accuracy AIMON IMON Gain VIMON_ACC IMON Accuracy 5 mV/A -20A ≤ IOUT ≤ 20A -1 1 A 20A ≤ IOUT ≤ 60A -5 5 % Zero Cross Detect Threshold (When OCSET/ZCD = Open) IZCD_OFS ZCD Current Threshold Offset PWM=0V 2 A IZCD_BLK ZCD Blanking Time PWM=0V 300 ns TMON Operating Range and Over-Temperature Threshold ATMON_SLP TMON Slope Gain No Load 7.8 8 8.2 mV/°C VTMON_25C TMON Voltage at 25°C V(TJCT)=0.6 V + (8mV x TJCT) 0.776 0.8 0.824 V VTMON_125C TMON Voltage at 125°C V(TJCT)=0.6 V + (8mV x TJCT) 1.56 1.6 1.64 V ITMON_SOUR TMON Sourcing Current TMON = 0V 800 µA ITMON_SINK TMON Sinking Current TMON = 3.3V 90 µA TOTP Over-Temperature Threshold Temperature Rising TOTP_HYST Over-Temperature Hysteresis 135 140 145 °C 15 °C 120 µs Current Limit and Low Side Negative Current Limit ILIM_DEF Current Limit Threshold Setup Time to Latch after the IC power-up Default Current Limit ROCSET =Open 120 A ILIM_1 Current Limit 1 ROCSET = 80 kΩ. See Table 3 100 A ILIM_2 Current Limit 2 ROCSET = 25 kΩ. See Table 3 ILIM_HYS OCP Hysteresis tOCP_SETUP NOC_COUNT INEG_OCP OC Counts before Reporting Fault and HS Latches Off Negative OCP Threshold 85 A 10 A 9 counts Negative Turbo Mode -60 A TMON = 2.5V 10 mA Fault Output Indicator ITMON/FLT ITMON/FLT TMON/FLT Output Current at Fault Conditions TMON/FLT Fault Report Time 100 ns Preliminary Over-Voltage Protection (AOZ5276 Only) VPOVP Over-Voltage Protection Threshold 2.8 V Notes: 4. All voltages are specified with respect to the corresponding AGND pin. 5. Characterization value. Not tested in production. 6. GH is an internal pin. Rev. 1.0 February 2022 www.aosmd.com Page 7 of 18 AOZ5276QI Timing Diagram 90% PWM 10% tPDLL tPDHL 90% GL 10% 10% tPDLU 90% GH VSWH tPDHU 1V 1V Figure 1. PWM Logic Input Timing Diagram PWM VTRI t TSSHD tTSSHD t TSSHD t TSSHD GL tTSEXIT TTSEXIT tTSEXIT tTSEXIT GH Figure 2. PWM Tri-State Hold Off and Exit Timing Diagram Rev. 1.0 February 2022 www.aosmd.com Page 8 of 18 AOZ5276QI Typical Performance Characteristics 96 16 94 14 92 12 Power Loss (W) Efficiency (%) TA = 25°C, VIN = 12V, VOUT = 1V, VCC = PVCC = EN = 5V, unless otherwise specified. 90 88 Vin=12V, Vo=0.9V, fsw=500k 86 Vin=12V, Vo=0.9V, fsw=800k 84 80 Vin=12V, Vo=1.8V, fsw=800k 5 15 10 20 25 30 40 35 45 Vin=12V, Vo=0.9V, fsw=800k Vin=12V, Vo=1.8V, fsw=500k 10 Vin=12V, Vo=1.8V, fsw=800k 8 6 4 Vin=12V, Vo=1.8V, fsw=500k 82 Vin=12V, Vo=0.9V, fsw=500k 2 50 60 55 65 0 70 5 15 10 20 25 30 40 35 45 50 60 55 65 Output Current (A) Output Current (A) Figure 3. Efficiency vs. Output Current Figure 4. Power Loss vs. Output Current 8.0 4.0 6.0 3.9 4.0 3.8 70 IOUT = 20A IOUT = 60A IOUT = 40A VCC Voltage (V) IMON Accuracy (%) UVLO Rising 2.0 0.0 -2.0 3.6 3.5 -4.0 3.4 -6.0 3.3 -8.0 25 35 45 55 65 75 85 95 105 115 35 45 55 65 75 85 95 105 115 125 Temperature (°C) Temperature (°C) Figure 5. IMON Accuracy (IVCC) vs. Temperature Figure 6. UVLO (VCC) Threshold vs. Temperature 1.8 2.8 1.7 Logic High Threshold 2.4 Rising Threshold EN Voltage (V) 1.6 2.0 Tri-state Window 1.6 1.2 0.8 1.5 1.4 Falling Threshold 1.3 1.2 Logic Low Threshold 0.4 0.0 25 UVLO Falling 3.2 25 125 3.2 PWM Voltage (V) 3.7 35 45 55 65 75 85 1.1 95 105 115 125 1.0 25 Temperature (°C) 45 55 65 75 85 95 105 115 125 Temperature (°C) Figure 7. PWM Threshold vs. Temperature Rev. 1.0 February 2022 35 www.aosmd.com Figure 8. EN Threshold vs. Temperature Page 9 of 18 AOZ5276QI Application Information Power-On Reset (POR) AOZ5276QI is a fully integrated smart power module designed to work over an input voltage range of 3V to 20V with 5V supplies for gate drive and internal control circuits.This smart power stage module features accurate current monitoring (IMON) which provides both HighSide and Low-Side MOSFET current information in both constant current and diode emulated mode operation. It also features temperature monitoring (TMON) which provides continuous thermal reading of the module temperature. Additional features such as, Power Input (VIN) Under-Voltage Lock-Out (UVLO), Control Circuit Input Voltage (VCC) UVLO, and light load efficiency control. A bootstrap capacitor "auto-refresh" feature ensures the boot capacitor is sufficiently charged before the High-Side MOSFET is being turned on. During initial start-up, both VCC and VIN voltage rise is monitored. Once the rising VCC voltage exceeds 3.8V (VCC_UVLO) and VIN voltage exceeds 2.4V (VIN_UVLO) for 120µs, normal operation of the driver is enabled. The PVCC voltage is not being monitored as it should be connected to VCC. Both VCC and VIN POR are gated to the TMON/FLT pin, which resumes normal TMON operation 120µs after both VCC and VIN are above their POR levels and no other faults occur. For UVLO function detail, see Table 5. The High-Side and Low-Side MOSFETs are combined into a single package with the pin configuration optimized for power routing with minimum parasitic inductance. The MOSFETs are individually tailored for efficient operation in low duty cycle synchronous buck converter applications. In addition, a high current driver is also included in the package to minimize the gate drive loop delay resulting in extremely fast switching. Powering the Module and the Gate Drives An external 5V supply (PVCC) is required for driving the MOSFETs. The MOSFETs are designed with low gate thresholds so that lower drive voltage can be used to reduce the switching and drive losses without compromising the conduction losses. The integrated gate driver is capable of supplying high peak current into the gate of Low-Side MOSFET to achieve extremely fast switching. A ceramic bypass capacitor of 1µF or higher is recommended from PVCC to PGND. For effective filtering it is strongly recommended to have a direct connection from this capacitor to PGND. The bootstrap supply for driving the High-Side MOSFET is generated by connecting a small capacitor between BOOT pin and the switching node (PHASE). It is recommended that this capacitor Cboot should be connected as close as possible to the device across PHASE (Pin 32) and BOOT (Pin 33). Pin 31 (PHASE) connection is optional as Pin 32 connection is sufficient. Rboot is an optional external resistor that can be used by designers to slow down the turn-on speed of the HighSide MOSFET. Selecting the Rboot value is a compromise between switching speed and the amplitude of power switching node (VSWH) voltage spikes. Typical values of Rboot are between 1Ω and 5Ω. Rev.1.0 February 2022 The AOZ5276QI must be powered up before the PWM input is applied. During start-up it is necessary for the PWM signal to go through a proper soft start sequence to minimize inrush current in the converter. Powering the module with a full duty cycle PWM signal applied may lead to a number of undesirable consequences. PWM Input The AOZ5276QI is compatible with 3.3V PWM input logic and supports Tri-State PWM. When the input is high impedance or left open, both the gate drive outputs will be turned off and the Low-Side and High-Side gates are actively held low. The PWM Threshold in Table 1 lists the thresholds for high-level and low-level logic, as well as Tri-State operation. Table 1. PWM Input and Tri-State Thresholds Parameters VPWMH VPWML VTRI(L) VTRI(H) Thresholds 2.70V 0.65V 1.1V 2.1V The AOZ5276QI is compatible with standard multiphase controllers as well as other controller IC’s utilizing 3.3V PWM logic. If the PWM input is being pulled into and remains in the tri-state window for a set hold-off time (tTSSHD), the driver will force both MOSFETs to their off state. When the PWM signal moves outside the tri-state window, the driver immediately resumes operation and drives the MOSFETs according to the PWM input. This feature allows the controller to use PWM as a method of forcing both MOSFETs to be off. For the condition that the PWM input is floating, the pin will be pulled into the Tri-State Clamp Voltage (VPWM_FLOAT) internally, thus forcing both MOSFETs to a safe off state. Table 2 shows the logic truth table for PWM and EN inputs. www.aosmd.com Page 10 of 18 AOZ5276QI Temperature Monitoring (TMON/FLT) Table 2. GH and GL Operation Truth Table Low-Side EN GH(7) High-Side PWM GL MOSFET MOSFET Tri-State X 0 0 OFF OFF 0 1 0 1 OFF OFF 1 1 1 0 ON OFF X 0 0 0 OFF OFF Note: 7. GH signal is not available on package level. Current Monitoring (IMON) An accurate Current Sense Amplifier monitors the current through the Low-Side MOSFET. A voltage signal proportional to that current appears at the IMON (Pin 38), relative to REFIN (Pin 39), with current sense gain of 5mV/A. Both IMON and REFIN should be connected to the appropriate current sense inputs of the controller. This IMON signal effectively eliminates the needs of using external sense resistor or inductor DCR sensing. AOZ5276QI monitors its internal temperature and provides a signal proportional to that temperature on the TMON/FLT pin. TMON/FLT has a voltage of 600mV at 0°C and temperature gain of 8mV/°C (ATMON_SLP). Figure 10 shows a simplified functional representation. The top section represents the protection fault that will pull the output high. The mid-section shows the symbolic sensor and the output buffer. The bottom section will set the initial state of TMON/FLT before the module is active. The TMON/FLT pin is configured internally such that a user can tie multiple pins together externally and the resulting TMON/FLT bus will assume the voltage of the highest contributor (representing the highest temperature). 3.3V 600mV + 8mV/°C * Temp Figure 9 shows the Low-Side MOSFET current sense mechanism. After the falling edge of the PWM, there are two delays: 1. TMON/FLT VCC_UVLO VIN_UVLO The expected propagation delay from PWM to VSWH (tPDLU) 2. The blanking delay to allow time for the transition to settle (tFALL_BLK) OCP HSD OTP Figure 10. Temperature Monitor Internal Circuit The IMON signal emulates the actual inductor current waveform. PWM Zero Cross Detect (ZCD) OCSET/ZCD pin controls the functions of ZCD. When OCSET/ZCD pin is left open or pulled up, ZCD function is being enabled. ZCD will detect the valley current when Low-Side MOSFET is on. If the current is less than 2A (IZCD_OFS), the MOSFET will be turned off independent of PWM logic level. This is an automatic light load mechanism and suitable for most analog PWM controllers. GH VSWH See Table 5 for details of ZCD function. GL Negative Current Protection (NCP) OCSET/ZCD pin also controls the function of NCP. When OCP threshold is set to any level with a resistor from OCSET/ZCD to AGND, NCP function becomes active. IL Blanking Time IMON Figure 9. Commutating Current Re-Construction at IMON For NCP function, the MOSFET will be turned off independent of PWM logic level if the current is less than -60 A (INEG_OCP). This is to protect the Low-Side MOSFET recovering from very high negative current. NCP will be released when negative current is less than 50A. See Table 5 for details of NCP function. Rev.1.0 February 2022 www.aosmd.com Page 11 of 18 AOZ5276QI Over Temperature Protection (OTP) High-Side Short Detect (HSD) If the internal temperature exceeds the OverTemperature threshold (TOTP), the TMON/FLT (Pin 36) is pulled to 3.3V after 100ns (tTMON/FLT) delay. Both HighSide and Low-Side MOSFETs are turned off under OTP condition. The TMON/FLT will remain in the fault mode until the junction temperature drops below the hysteresis threshold (TOTP_HYST). At that point, the TMON/FLT and IMON pins resume normal operation. See Table 5 for OTP function detail. When Low-Side MOSFET is on, the voltage across the High-Side MOSFET is monitored. A High-Side short condition is detected if the voltage is higher than the HSD threshold. The TMON/FLT pin will be pulled high to indicate a fault condition. The power module will not change the High-Side and Low-Side MOSFET status until the fault condition is released by power cycling. Over Current Protection (OCP) An Over Current Production (OCP) fault is detected when the current running through the power stage exceeds 120A (ILIM_DEF). The OCP level can be set by using external resistor at OCSET/ZCD (Pin 37). During the initial 120µs (tOCP_SETUP) after the part is enabled, the resistor value is detected and latched within the system to store the OCP threshold level. After OCP level is latched, the OCSET/ZCD pin will function as ZCD/ NCP control only. If the OCP event is trigged 9 times (NOC_COUNT) consecutively, TMON/FLT (Pin 36) will be internally pulled to 3.3V to indicate a fault condition. The FAULT flag will be released by a power reset or the output current is 10A less than the OCP threshold. For OCP function detail, refer to Table 5. OCSET/ZCD pin control 3 functions: 1. Zero Cross Detect (ZCD) 2. Negative Current Protection (NCP) 3. OCP Threshold Setting See Table 3 for the corresponding functions. OCSET/ZCD setting and Table 3. OCSET/ZCD Setting for OCP Level, ZCD and NCP Function OCSET/ ZCD Within 120µs after power-up After 120µs since IC power-up OCP Level ZCD NCP Open 120A Enable Not Active 80kΩ 100A Not Active Enable