AOZ5312UQI

AOZ5312UQI High-Current, High-Performance DrMOS Power Module General Description Features The AOZ5312UQI is a high efficiency synchronous buck power stage module consisting of two asymmetrical MOSFETs and an integrated driver. The MOSFETs are individually optimized for operation in the synchronous buck configuration. The High-Side MOSFET is optimized to achieve low capacitance and gate charge for fast switching with low duty cycle operation. The Low-Side MOSFET has ultra-low ON resistance to minimize conduction loss.  2.5V to 20V power supply range The AOZ5312UQI uses a PWM input for accurate control of the power MOSFETs switching activities, is compatible with 3V and 5V (CMOS) logic and supports Tri-State PWM.  SMOD# control for Diode Emulation / CCM operation A number of features are provided making the AOZ5312UQI a highly versatile power module. The bootstrap switch is integrated in the driver. The Low-Side MOSFET can be driven into diode emulation mode to provide asynchronous operation and improve light-load performance. The pin-out is also optimized for low parasitics, keeping their effects to a minimum.  4.5V to 5.5V driver supply range  60A continuous output current - Up to 80A with 10ms on pulse - Up to 120A with 10us on pulse  Up to 2MHz switching operation  3V/5V PWM and Tri-State input compatible  Under-Voltage LockOut protection  Low Profile 5x5 QFN-31L package Applications  Memory and graphics cards  VRMs for motherboards  Point of load DC/DC converters  Video gaming consoles Typical Application Circuit 2 .5 V ~ 2 0 V V IN BOOT VCC PW M C o n tro lle r CBOOT HS D riv e r THW N PHASE D riv e r L o g ic and D e la y D IS B # C IN VSW H VO UT L1 SM O D# LS D riv e r PW M CO U T GL AGND VCC PVCC PG ND CVC C 5V Rev. 1.0 July 2019 CP V C C www.aosmd.com PG ND Page 1 of 18 AOZ5312UQI Ordering Information Part Number Junction Temperature Range Package Environmental AOZ5312UQI -40°C to +150°C QFN5x5-31L RoHS AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. PWM 1 SMOD# 2 DISB# THWN PVCC PGND GL VSWH VSWH VSWH Pin Configuration 31 30 29 28 27 26 25 24 GL 23 VSWH 22 VSWH PGND VCC 3 21 VSWH AGND 4 20 VSWH BOOT 5 19 VSWH NC 6 PHASE 7 VIN 8 PGND 18 VSWH VIN 17 VSWH VIN 13 14 15 PGND VIN 12 PGND 11 PGND 10 PGND 9 VIN 16 VSWH QFN5x5-31L (Top View) Rev. 1.0 July 2019 www.aosmd.com Page 2 of 18 AOZ5312UQI Pin Description Pin Number Pin Name Pin Function 1 PWM PWM input signal from the controller IC. When DISB#=0V, the internal resistor divider will be disconnected and this pin will be at high impedance. 2 SMOD# Pull low to enable Discontinuous Mode of Operation (DCM), Diode Emulation or Skip Mode. There is an internal pull-down resistor to AGND. 3 VCC 5V Bias for Internal Logic Blocks. Ensure to position a 1µF MLCC directly between VCC and AGND (Pin 4). 4 AGND Signal Ground. 5 BOOT High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between BOOT and the PHASE (Pin 7). 6 NC 7 PHASE 8, 9, 10, 11 VIN 12, 13, 14, 15 PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET). 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 VSWH Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side MOSFET. These pins are used for Zero Cross Detection and Anti-Overlap Control as well as main inductor terminal. 27 GL 28 PGND Power Ground pin for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF directly between PGND and PVCC (Pin 29). 29 PVCC 5V Power Rail for High-Side and Low-Side MOSFET Drivers. Ensure to position a 1µF MLCC directly between PVCC and PGND (Pin 28). 30 THWN Thermal warning indicator. This is an open-drain output. When the temperature at the driver IC die reaches the Over Temperature Threshold, this pin is pulled low. 31 DISB# Output disable pin. When this pin is pulled to a logic low level, the IC is disabled. There is an internal pull-down resistor to AGND. Rev. 1.0 July 2019 Internally connected to VIN paddle. It can be left floating (no connect) or tied to VIN. This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 5). Power stage High Voltage Input (Drain connection of High-Side MOSFET). Low-Side MOSFET Gate connection. This is for test purposes only. www.aosmd.com Page 3 of 18 AOZ5312UQI Functional Block Diagram PVCC VCC SMOD# ZCD Select BOOT REF/BIAS UVLO HS Gate Driver Level Shifter Boot Enable DISB# HS Sequencing And Propagation Delay Control PHASE HS Gate Driver Logic VSWH PHASE Check LS Min On Control Logic LS VCC ZCD ZCD Detect PWM LS Gate PVCC Tri-State PWM PWM Tri-State Logic LS Gate Driver Thermal Monitor GL PGND AGND THWN Rev. 1.0 July 2019 VIN www.aosmd.com Page 4 of 18 AOZ5312UQI Absolute Maximum Ratings Recommended Operating Conditions Exceeding the Absolute Maximum ratings may damage the device. The device is not guaranteed to operate beyond the Maximum Recommended Operating Conditions. Parameter Rating Low Voltage Supply (VCC, PVCC) High Voltage Supply (VIN) Parameter -0.3V to 7V -0.3V to 25V Control Inputs (PWM, SMOD#, DISB#) -0.3V to (VCC+0.3V) Output (THWN) -0.3V to (VCC+0.3V) Bootstrap Voltage DC (BOOT-PGND) Bootstrap Voltage Transient (BOOT-PGND) -0.3V to 28V (1) -0.3V to 7V BOOT Voltage Transient(1) (BOOT-PHASE/VSWH) -0.3V to 9V Switch Node Voltage Transient(1) (PHASE/VSWH) High Voltage Supply (VIN) 2.5V to 20V Low Voltage / MOSFET Driver Supply (VCC, PVCC) 4.5V to 5.5V Control Inputs (PWM, SMOD#, DISB#) 0V to VCC Output (THWN) 0V to VCC Operating Frequency 200kHz to 2MHz -8V to 30V Bootstrap Voltage DC (BOOT-PHASE/VSWH) Switch Node Voltage DC (PHASE/VSWH) Rating -0.3V to 25V -8V to 33V Low-Side Gate Voltage DC (GL) (PGND-0.3V) to (PVCC+0.3V) Low-Side Gate Voltage Transient(1) (GL) (PGND-2.5V) to (PVCC+0.3V) VSWH Current DC 60A VSWH Current 10ms Pulse 80A VSWH Current 10us Pulse 120A Storage Temperature (TS) -65°C to 150°C Max Junction Temperature (TJ) (3) ESD Rating 150°C 2kV Notes: 1. Peak voltages can be applied for 10ns per switching cycle. 2..Peak voltages can be applied for 20ns per switching cycle. 3. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5 in series with 100pF. Rev. 1.0 July 2019 www.aosmd.com Page 5 of 18 AOZ5312UQI Electrical Characteristics(4) TJ = 0°C to 150°C, VIN = 12V, VOUT = 1V, PVCC = VCC = DISB# = 5V, unless otherwise specified. Min/Max values are guaranteed by test, design, or statistical correlation. Symbol Parameter Conditions Min. Typ. Max. Units 2.5 20 V 4.5 5.5 V GENERAL VIN Power Stage Power Supply VCC Low Voltage Bias Supply PVCC = VCC Thermal Resistance Reference to High-Side MOSFET temperature rise 2.5 Freq = 300kHz. AOS Demo Board. 12.5 VCC Rising 3.5 VCC Hysteresis 400 RJC(4) RJA (4) °C / W °C / W INPUT SUPPLY AND UVLO VCC_UVLO Undervoltage LockOut VCC_HYST DISB# = 0V IVCC IPVCC Control Circuit Shutdown Bias Current Drive Circuit Operating Current 3.9 V mV 1 SMOD# = 5V, PWM = 0V 550 SMOD# = 0V, PWM = 0V 535 SMOD# = 0V, PWM =1.65V 430 PWM = 400kHz, 20% Duty Cycle 15.5 mA 39 mA PWM = 1MHz, 20% Duty Cycle µA PWM INPUT VPWMH Logic High Input Voltage VPWML Logic Low Input Voltage IPWM_SRC IPWM_SNK VTRI VPWM_FLOAT PWM Pin Input Current 2.7 0.72 V PWM = 0V -150 µA PWM = 3.3V 150 µA PWM Tri-State Window PWM Tri-State Voltage Clamp V 1.35 PWM = Floating 1.95 1.65 V V DISB# INPUT VDISB#_ON Enable Input Voltage VDISB#_OFF Disable Input Voltage RDISB# DISB# Input Resistance 2.0 V 0.8 Pull-Down Resistor 850 V kΩ SMOD# IMPUT VSMOD#_H Logic High Input Voltage VSMOD#_L Logic Low Input Voltage RSMOD# SMOD# Input Resistance Rev. 1.0 July 2019 2.0 V 0.8 Pull-Down Resistor www.aosmd.com 850 V kΩ Page 6 of 18 AOZ5312UQI Electrical Characteristics(4) TJ = 0°C to 150°C, VIN = 12V, VOUT = 1V, PVCC = VCC = DISB# = 5V, unless otherwise specified. Min/Max values are guaranteed by test, design, or statistical correlation. Symbol Parameter Conditions Min. Typ. Max. Units GATE DRIVER TIMINGS tPDLU PWM to High-Side Gate PWM: H  L, VSWH: H  L 30 ns tPDLL PWM to Low-Side Gate PWM: L  H, GL: H  L 25 ns tPDHU LS to HS Gate Deadtime GL: H  L, GH(6): L  H 15 ns tPDHL HS to LS Gate Deadtime VSWH: H  1V, GL: L  H 13 ns tTSSHD Tri-State Shutdown Delay PWM: L  VTRI, GL: H  L and PWM: H  VTRI, VSWH: H  L 25 ns tTSEXIT Tri-State Propagation Delay PWM: VTRI  H, VSWH: L  H PWM: VTRI  L, GL: L  H 35 ns tLGMIN LS Minimum On Time SMOD# = L 350 ns Temperature Rising 150 °C 30 °C 60 mV 120 Ω THERMAL NOTIFICATION TJTHWN Junction Thermal Threshold TJHYST Junction Thermal Hysteresis VTHWN THWN Pin Output Low RTHWN THWN Pull-Down Resistance ITHWN = 0.5mA Notes: 4. All voltages are specified with respect to the corresponding AGND pin. 5. Characterization value. Not tested in production. 6. GH is an internal pin. Rev. 1.0 July 2019 www.aosmd.com Page 7 of 18 AOZ5312UQI Logic Table and Timing Diagrams Table 1: Input Control Truth Table DISB# SMOD# PWM(1) GH (Not a Pin) GL L X X L L H L H H L H L L L H, Forward IL L, Reverse IL H X Tri-State L L H H H H L H H L L H Note: 1.Diode emulation mode is activated when SMOD# is LOW and PWM transition from HIGH to Tri-State. Zero Cross Detection (ZCD) at IL*Rdson(LS) = 0.5mV to turn off GL. VPWMH PWM VPWML tPDLL tPDHL GL 1V 1V tPDLU 90% VSWH tPDHU 1V 1V Figure 1. PWM Logic Input Timing Diagram Rev. 1.0 July 2019 www.aosmd.com Page 8 of 18 AOZ5312UQI Logic Table andTiming Diagrams (Continued) PWM VTRI t TSSHD tTSSHD t TSSHD tTSSHD GL t TSEXIT TTSEXIT tTSEXIT t TSEXIT VSWH Figure 2. PWM Tri-State Hold Off and Exit Timing Diagram Rev. 1.0 July 2019 www.aosmd.com Page 9 of 18 AOZ5312UQI Typical Performance Characteristics TA = 25°C, VIN = 12V, VOUT = 1V, PVCC = VCC = DISB# = 5V, unless otherwise specified. 12 96% 94% VIN=12V, VOUT=1V, Freq=300kHz 10 VIN=12V, VOUT=1V, Freq=500kHz Power Loss (W) Efficiency (%) 92% 90% 88% VIN=12V, VOUT=1V, Freq=300kHz 86% VIN=12V, VOUT=1V, Freq=500kHz 8 6 4 84% 2 82% 80% 5 10 15 20 25 30 35 40 45 50 55 0 60 5 10 15 20 600 4.0 580 3.5 560 3.0 540 520 500 2.0 0.5 440 100 125 0.0 - 50 150 3.7 1.7 3.6 VCC Voltage (v) SMOD# Voltage (V) 60 Tri-State Window Logic Low Threshold - 25 0 25 50 75 100 125 150 Rising Threshold 3.5 Logic High Threshold 1.5 1.4 1.3 Logic Low Threshold 3.4 3.3 3.2 3.1 Falling Threshold 1.1 1.0 55 Figure 6. PWM Threshold vs. Temperature 1.8 1.2 50 Temperature (°C) Figure 5. Supply Current (IVCC) vs. Temperature 1.6 45 1.5 460 25 50 75 Temperature(°C) 40 Logic High Threshold 1.0 0 35 2.5 480 - 25 30 Figure 4. Power Loss vs. Load Current PWM Voltage (V) VCC Current (uA) Figure 3. Efficiency vs. Load Current -50 25 Load Current (A) Load Current (A) 3.0 - 50 - 25 0 25 50 75 Temperature (°C) 100 125 150 2.9 -50 -25 0 25 50 75 Temperature (C) 100 125 150 Figure 7. SMOD# Threshold vs. Temperature Figure 8. UVLO (VCC) Threshold vs. Temperature www.aosmd.com Page 10 of 18 Rev. 1.0 July 2019 AOZ5312UQI Typical Performance Characteristics TA = 25°C, VIN = 12V, VOUT = 1V, PVCC = VCC = DISB# = 5V, unless otherwise specified. 1.8 4.0 1.7 3.5 3.0 Logic High Threshold PWM Voltage (V) DISB# Voltage (V) 1.6 1.5 1.4 1.3 Logic Low Threshold 1.2 2.5 2.0 1.5 1.0 0.5 1.1 1.0 Logic High Threshold -50 - 25 0 25 50 75 100 125 150 Logic Low Threshold 0.0 4.5 Temperature (°C) 4.75 5 5.25 5.5 VVC Voltage (V) Figure 9. DISB# Threshold vs Temperature Figure 10. PWM Threshold vs VCC Voltage Figure 11. High-Side MOSFET SOA Figure 12. Low-Side MOSFET SOA Rev. 1.0 July 2019 www.aosmd.com Page 11 of 18 AOZ5312UQI Application Information AOZ5312UQI is a fully integrated power module designed to work over an input voltage range of 2.5V to 20V with a separate 5V supply for gate drive and internal control circuitry. The MOSFETs are individually optimized for efficient operation on both High-Side and Low-Side for a low duty cycle synchronous buck converter. High current MOSFET Gate Drivers are integrated in the package to minimize parasitic loop inductance for optimum switching efficiency. Powering the Module and the Gate Drives An external supply PVCC = 5V is required for driving the MOSFETs. The MOSFETs are designed with optimally customized gate threshold voltages to achieve the most advantageous compromise between high switching speed and minimal power loss. The integrated gate driver is capable of supplying large peak current into the LowSide MOSFET to achieve fast switching. A ceramic bypass capacitor of 1F or higher is recommended from PVCC (Pin 29) to PGND (Pin 28). The control logic supply VCC (Pin 3) can be derived from the gate drive supply PVCC (Pin 29) through an RC filter to bypass the switching noise (See Typical Application Circuit). The boost supply for driving the High-Side MOSFET is generated by connecting a small capacitor (100nF) between the BOOT (Pin 5) and the switching node PHASE (Pin 7). It is recommended that this capacitor CBOOT should be connected to the device across Pin 5 and Pin 7 as closely as possible. A bootstrap switch is integrated into the device to reduce external component count. An optional resistor RBOOT in series with CBOOT between 1Ω to 5Ω can be used to slow down the turn on speed of the High-Side MOSFET to achieve both short switching time and low VSWH switching node spikes at the same time. Under-voltage LockOut AOZ5312UQI starts up to normal operation when VCC rises above the Under-Voltage LockOut (UVLO) threshold voltage. The UVLO release is set at 3.5V typically. Since the PWM control signal is provided from an external controller or a digital processor, extra caution must be taken during start up. AOZ5312UQI must be powered up before PWM input is applied. Normal system operation begins with a soft start sequence by the controller to minimize in-rush current Rev. 1.0 July 2019 during start up. Powering the module with a full duty cycle PWM signal may lead to many undesirable consequences due to excessive power. AOZ5312UQI provides some protections such as UVLO and thermal monitor. For system level protection, the PWM controller should monitor the current output and protect the load under all possible operating and transient conditions. Disable (DISB#) Function The AOZ5312UQI can be enabled and disabled through DISB# (Pin 31). The driver output is disabled when DISB# input is connected to AGND. The module would be in standby mode with low quiescent current of less than 1uA. The module will be active when DISB# is connected to VCC Supply. The driver output will follow PWM input signal. A weak pull-down resistor is connected between DISB# and AGND. Power-up sequence design must be implemented to ensure proper coordination between the module and external PWM controller for soft start and system enable/ disable. It is recommended that the AOZ5312UQI should be disabled before the PWM controller is disabled. This would make sure AOZ5312UQI will be operating under the recommended conditions. Input Voltage VIN AOZ5312UQI is rated to operate over a wide input range from 2.5V to 20V. For high current synchronous buck converter applications, large pulse current at high frequency and high current slew rates (di/dt) will be drawn by the module during normal operation. It is strongly recommended to place a bypass capacitor very close to the package leads at the input supply (VIN) Both X7R or X5R quality surface mount ceramic capacitors are suitable. The High-Side MOSFET is optimized for fast switching by using a low gate charge (QG) device. When the module is operated at high duty cycle ratio, conduction loss from the High-Side MOSFET will be higher. The total power loss for the module is still relatively low but the High-Side MOSFET higher conduction loss may have higher temperature. The two MOSFETs have their own exposed pads and PCB copper areas for heat dissipation. It is recommended that worst case junction temperature be measured for both High-Side MOSFET and Low-Side MOSFET to ensure that they are operating within Safe Operating Area (SOA). www.aosmd.com Page 12 of 18 AOZ5312UQI PWM Input AOZ5312UQI is compatible with 3V and 5V (CMOS) PWM logic. Refer to Figure 1 for PWM logic timing and propagation delays diagram between PWM input and the MOSFET gate drives. AOZ5312UQI is compatible with 3V and 5V (CMOS) PWM logic. Refer to Figure 1 for PWM logic timing and propagation delays diagram between PWM input and the MOSFET gate drives. The PWM is also compatible with Tri-State input. When the PWM output from the external PWM controller is in high impedance or not connected both High-Side and Low-Side MOSFETs are turned off and VSWH is in high impedance state. Table 2 shows the thresholds level for high-to-low and low-to-high transitions as well as TriState window. There is a Holdoff Delay between the corresponding PWM Tri-State signal and the MOSFET gate drivers to prevent spurious triggering of Tri-State mode which may be caused by noise or PWM signal glitches. The Holdoff Delay is typically 25ns. Table 2: PWM Input and Tri-State Thresholds Thresholds  VPWMH VPWML VTRIH VTRIL AOZ5312UQI 2.7V 0.72V 1.35V 1.95V Note: See Figure 2 for propagation delays and Tri-State window. Diode Mode Emulation of Low-Side MOSFET (SMOD#) AOZ5312UQI can be operated in the diode emulation or pulse skipping mode using SMOD# (Pin 2). This enables the converter to operate in asynchronous mode during start up, light load or under pre-bias conditions. When SMOD# is high, the module will operate in Continuous Conduction Mode (CCM). The Driver logic will use the PWM signal and generate both the High-Side and Low-Side complementary gate drive outputs with minimal anti-overlap delays to avoid cross conduction. Rev. 1.0 July 2019 When SMOD# is low, the module can operate in Discontinuous Conduction Mode (DCM). The High-Side MOSFET gate drive output is not affected but Low-Side MOSFET will enter diode emulation mode. See Table 1 for all truth table for DISB#, SMOD# and PWM inputs. Gate Drives AOZ5312UQI has an internal high current high speed driver that generates the floating gate driver for the High-Side MOSFET and a complementary driver for the Low-Side MOSFET. An internal shoot through protection scheme is implemented to ensure that both MOSFETs cannot be turned on at the same time. The operation of PWM signal transition is illustrated as below. 1) PWM from logic Low to logic High When the falling edge of Low-Side Gate Driver output GL goes below 1V, the blanking period is activated. After a pre-determined value (tPDHU), the complementary HighSide Gate Driver output GH is turned on. 2) PWM from logic High to logic Low When the falling edge of switching node VSWH goes below 1V, the blanking period is activated. After a predetermined value (tPDHL), the complementary Low-Side Gate Driver output GL is turned on. This mechanism prevents cross conduction across the input bus line VIN and PGND. The anti-overlap circuit monitors the switching node VSWH to ensure a smooth transition between the two MOSFETs under any load transient conditions. Thermal Warning (THWN) The driver IC temperature is internally monitored and an thermal warning flag at THWN (Pin 30) is asserted if it exceeds 150°C. This warning flag is reset when the temperature drop back to 120°C. THWN is an open drain output that is pulled to AGND to indicate an overtemperature condition. It should be connected to VCC through a resistor for monitoring purpose. The device will not power down during the over temperature condition. www.aosmd.com Page 13 of 18 AOZ5312UQI PCB Layout Guidelines AOZ5312UQI is a high current module rated for operation up to 2MHz. This requires high switching speed to keep the switching losses and device temperatures within limits. An integrated gate driver within the package eliminates driver-to-MOSFET gate pad parasitic of the package or on PCB. To achieve high switching speeds, high levels of slew rate (dv/dt and di/dt) will be present throughout the power train which requires careful attention to PCB layout to minimize voltage spikes and other transients. As with any synchronous buck converter layout, the critical requirement is to minimize the path of the primary switching current loop formed by the High-Side MOSFET, Low-Side MOSFET, and the input bypass capacitor CIN. The PCB design is greatly simplified by the optimization of the AOZ5312UQI pin out. The power inputs of VIN and PGND are located adjacent to each other and the input bypass capacitors CIN should be placed as close as possible to these pins. The area of the secondary switching loop is formed by Low-Side MOSFET, output inductor L1, and output capacitor COUT is the next critical requirement. This requires second layer or “Inner 1” to be the PGND plane. VIAs should then be placed near PGND pads. While AOZ5312UQI is a highly efficient module, it still dissipates a significant amount of heat under high power conditions. Special attention is required for thermal design. MOSFETs in the package are directly attached to individual exposed pads (VIN and PGND) to simplify thermal management. Both VIN and VSWH pads should be attached to large areas of PCB copper. Thermal relief pads should be placed to ensure proper heat dissipation to the board. An inner power plane layer dedicated to VIN, typically the high voltage system input, is desirable and VIAs should be provided near the device to connect the VIN pads to the power plane. Significant amount of heat can also be dissipated through multiple PGND pins. A large copper area connected to the PGND pins in addition to the system ground plane through VIAs will further improve thermal dissipation. As shown on Figure 13, the top most layer of the PCB should comprise of wide and exposed copper area for the primary AC current loop which runs along VIN pad originating from the input capacitors C10, C11, and C12 that are mounted to a large PGND pad. They serve as thermal relief as heat flows down to the VIN exposed pad that fan out to a wider area. Adding VIAs will only help transfer heat to cooler regions of the PCB board through the other layers beneath but serve no purpose to AC activity as all the AC current sees the lowest impedance on the top layer only. Rev. 1.0 July 2019 Figure 13. Top Layer of Demo Board, VIN, VSWH and PGND Copper Pads As the primary and secondary (complimentary) AC current loops move through VIN to VSWH and through PGND to VSWH, large positive and negative voltage spikes appear at the VSWH terminal which are caused by the large internal di/dt produced by the package parasitic. To minimize the effects of this interference at the VSWH terminal, at which the main inductor L1 is mounted, size just enough for the inductor to physically fit. The goal is to employ the least amount of copper area for this VSWH terminal, only enough so the inductor can be securely mounted. To minimize the effects of switching noise coupling to the rest of the sensitive areas of the PCB, the area directly underneath the designated VSWH pad or inductor terminal is voided and the shape of this void is replicated descending down through the rest of the layers. Refer to Figure 14. Figure 14. Bottom layer of PCB Positioning VIAs through the landing pattern of the VIN and PGND thermal pads will help quickly facilitate the thermal build-up and spread the heat much more quickly www.aosmd.com Page 14 of 18 AOZ5312UQI towards the surrounding copper layers descending from the top layer. (See RECOMMENDED LANDING PATTERN AND VIA PLACEMENT section). The exposed pads dimensional footprint of the 5x5 QFN package is shown on the package dimensions page. For optimal thermal relief, it is recommended to fill the PGND and VIN exposed landing pattern with 10mil diameter VIAs. 10mil diameter is a commonly used VIA diameter as it is optimally cost effective based on the tooling bit used in manufacturing. Each via is associated with a 20mil diameter keep out. Maintain a 5mil clearance (127um) around the inside edge of each exposed pad in case of solder overflow, which could potentially short with the adjacent exposed thermal pad. Rev. 1.0 July 2019 www.aosmd.com Page 15 of 18 AOZ5312UQI Package Dimensions, QFN5x5A-31L, EP3_S RECOMMENDED LAND PATTERN UNIT: mm NOTE CONTROLLING DIMENSION IS MILLIMETER. CONVERTED INCH DIMENSIONS ARE NOT NECESSARILY EXACT. Rev. 1.0 July 2019 www.aosmd.com Page 16 of 18 AOZ5312UQI Tape and Reel Drawing, QFN5x5A-31L, EP3_S Rev. 1.0 July 2019 www.aosmd.com Page 17 of 18 AOZ5312UQI Part Marking AOZ5312UQI (5mm x 5mm QFN) BKU0 YWLT Year Code & Week Code Part Number Code Assembly Lot Code LEGAL DISCLAIMER Applications or uses as critical components in life support devices or systems are not authorized. AOS does not assume any liability arising out of such applications or uses of its products. AOS reserves the right to make changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the product for their intended application. Customer shall comply with applicable legal requirements, including all applicable export control rules, regulations and limitations. AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at: http://www.aosmd.com/terms_and_conditions_of_sale LIFE SUPPORT POLICY ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.0 July 2019 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 18 of 18