AOZ6605PI
EZBuckTM 5A Synchronous Buck Regulator
General Description
Features
The AOZ6605PI works from 4.5V to 18V input voltage
range, and provides up to 5A of continuous output
current with an output voltage adjustable down to 0.8V.
4.5V to 18V operating input voltage range
The AOZ6605PI comes in EPAD-SO8 package and is
rated over a -40°C to +85°C operating ambient
temperature range.
External program soft start
Synchronous Buck with internal low RDS(ON) (55m/
12m) high-side and low-side MOSFETs
U-PEM (pulse energy mode) enables 86% plus
efficiency with Io=10mA (Vin=12V, Vo=5V)
Adjacent pin short protection
Output voltage adjustable to 0.8V
Adjacent pin short protection
5A continuous output current
650kHz PWM operation
Cycle-by-cycle current limit
Pre-bias start-up
Extensive protection features
EPAD-SO8 package
Applications
High reliable DC/DC converters
High performance LCD TV
High performance cable modems
Typical Application
VIN
CVCC
CIN
VIN
VCC
BST
RBST
CBST
EN
AOZ6605PI
LX
COMP
RC
CC
FB
SS
CSS
VOUT
L1
3.3µH R1
GND
COUT
R2
Figure 1. 5A Synchronous Buck Regulator, Fs = 650kHz
Rev. 2.1 January 2020
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Page 1 of 15
AOZ6605PI
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ6605PI
-40°C to +85°C
8-Pin EPAD SO-8
Green Product
AOS Green Products use reduced levels of Halogens and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
SS
1
EN
2
LX
8
FB
7
COMP
VIN
3
6
VCC
GND
4
5
BST
Pin Description
Pin Number
Pin Name
Pin Function
1
SS
Soft Start Pin.
2
EN
Enable pin. Logic high to enable the device.
3
VIN
Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high, the
device starts up.
4
GND
Power ground.
5
BST
Bootstrap. Requires a capacitor connected between LX and BST to form a floating supply
across the high-side switch driver.
6
VCC
Internal LDO output.
7
COMP
External loop compensation pin. Connect a RC network between COMP and GND to compensate the control loop.
8
FB
Feedback input. The FB pin is used to set the output voltage via a resistive voltage divider
between the output and GND.
Exposed Pad
LX
Switching node. LX is the drain of the internal low-side power FETs.
Rev. 2.1 January 2020
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Page 2 of 16
AOZ6605PI
Absolute Maximum Ratings
Maximum Operating Ratings
Exceeding the Absolute Maximum Ratings may damage
the device.
The device is not guaranteed to operate beyond the
Maximum Operating ratings.
Parameter
Rating
Parameter
Supply Voltage (VIN), EN (VEN)
+20V
-0.7V to VIN+0.3V
LX to GND
Rating
Supply Voltage (VIN)
4.5V to 18V
Output Voltage Range
0.8V to 0.85*VIN
LX to GND (20ns)
-5V to 22V
Ambient Temperature (TA)
VCC, FB, COMP to GND
-0.3V to 6V
Package Thermal Resistance
EPAD SO8 (JA)(2)
VBST to LX
6V
Junction Temperature (TJ)
+150°C
Storage Temperature (TS)
-65°C to +150°C
ESD Rating(1)
2kV
Note:
-40°C to +85°C
40°C/W
Note:
2. The value of JA is measured with the device mounted on a 1-in2
FR-4 four layer board with 2oz copper and Vias, in a still air environment with TA = 25°C. The value in any given application depends on
the user’s specification board design.
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5k in series with 100pF.
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified. Specifications in BOLD indicate a temperature
range of -40°C to +85°C. These specifications are guaranteed by design.
Symbol
VIN
VUVLO
VCC
IIN
Parameter
Conditions
Supply Voltage
Min.
Typ.
4.5
Input Under-Voltage Lockout Threshold
VIN rising
VIN falling
3.3
VCC Regulator
4.0
3.7
Max
Units
18
V
4.45
V
V
5
V
VCC Load Regulator
ICC = 5mA
3
%
Supply Current (Quiescent)
IOUT = 0A
250
A
VEN = 0V
1
10
A
0.1
1
A
0.607
0.616
V
IOFF
Shutdown Supply Current
VFB
Feedback Voltage
TA = 25°C
RO
Load Regulation
PWM mode
1A < ILoad < 5A
0.5
%
SV
Line Regulation
4.5V < VIN < 18V
1
%
IFB
Feedback Voltage Input Current
VEN
EN Input Threshold
VHYS
EN Input Hysteresis
0.598
200
Off threshold
On threshold
-40°C < TJunction < 125°C
0.6
2
300
IEN
EN Input Current
VEN = 5V
tSS
SS Time
CSS = 22nF
nA
V
V
mV
A
5
2.5
ms
Modulator
Frequency
550
DMAX
Maximum Duty Cycle
85
TMIN
Controllable Minimum On-Time
fO
Rev. 2.1 January 2020
650
750
%
110
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kHz
ns
Page 3 of 16
AOZ6605PI
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified. Specifications in BOLD indicate a temperature
range of -40°C to +85°C. These specifications are guaranteed by design.
Symbol
Parameter
Conditions
Min.
Typ.
Max
Units
Gmcs
Current Sense Transconductance
8
A/V
Gma
Error Amplifier Transconductance
400
A/V
ICH
Charging Current of Error Amplifier
40
A
Protection
6
A
VOVP
Over Voltage Protection
Off threshold
On threshold
720
620
mV
TOTP
Over-temperature Shutdown LImit
TJ rising
TJ falling
150
100
°C
°C
RH
High-Side Switch On-Resistance
VBST-LX = 5V
55
m
RL
Low-Side Switch On-Resistance
VCC = 5V
12
m
ILIM
Current Limit
5.5
Output Stage
Rev. 2.1 January 2020
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Page 4 of 16
AOZ6605PI
Functional Block Diagram
BST
VCC
UVLO
&
POR
EN
5V LDO
REGULATOR
+
ISEN
-
REFERENCE
&
BIAS
SOFTSTART
+
+
EAMP
-
–
PWM
COMP
+
PWM
CONTROL
LOGIC
LEVEL SHIFTER
+
FET DRIVER
SS
0.6V
COMP
Q1
ILIMIT
SS
FB
VIN
LX
Q2
650kHz
OSCILLATOR
GND
Rev. 2.1 January 2020
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Page 5 of 16
AOZ6605PI
Efficiency
Efficiency vs. Load Current (VIN=5V)
100
100
90
90
Efficiency (%)
Efficiency (%)
Efficiency vs. Load Current (VIN=12V)
80
70
5V OUTPUT L=4.7µH
80
70
3.3V OUTPUT L=3.3µH
3.3V OUTPUT L=3.3µH
2.5V OUTPUT L=3.3µH
60
50
0.01
60
2.5V OUTPUT L=3.3µH
1.8V OUTPUT L=2.2µH
1.8V OUTPUT L=2.2µH
1.2V OUTPUT L=2.2µH
1.2V OUTPUT L=2.2µH
0.1
1
50
0.01
10
0.1
1
10
IO (A)
IO (A)
Thermal Derating with 12VIN
Thermal Derating with 5VIN
5.2
5.2
5.0
5.0
4.8
4.8
4.6
4.6
IO_max (A)
IO_max (A)
Thermal Derating
4.4
5.0 VO
4.2
4.2
3.3 VO
3.3 VO
4.0
1.2 VO
1.8 VO
3.8
1.2 VO
30
35
40
45
50
55
60
65
70
75
80
85
3.6
25
Temperature (°C)
Rev. 2.1 January 2020
2.5 VO
4.0
2.5 VO
3.8
3.6
25
4.4
30
35
40
45
50
55
60
65
70
75
80
85
Temperature (°C)
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Page 6 of 16
AOZ6605PI
Typical Characteristics
Circuit of Typical Application. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V, unless otherwise specified.
Light Load Operation
Full Load Operation
VLX
(10V/div)
VLX
(10V/div)
V O ripple
(50mV/div)
IL
(2A/div)
V O ripple
(50mV/div)
V IN ripple
(0.2V/div)
IL
(1A/div)
V IN ripple
(0.2V/div)
1µs/div
1µs/div
PWM to PEM Mode Change
PEM to PWM Mode Change
VLX
(10V/div)
VLX
(10V/div)
VO
(0.1V/div)
VO
(0.1V/div)
IL
(2A/div)
IL
(2A/div)
20µs/div
20µs/div
Short Protection
Short Protection Recovery
VLX
(10V/div)
VLX
(10V/div)
VO
(1V/div)
VO
(1V/div)
IL
(2A/div)
IL
(2A/div)
20ms/div
20ms/div
Rev. 2.1 January 2020
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Page 7 of 16
AOZ6605PI
Typical Characteristics (continued)
Circuit of Typical Application. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V, unless otherwise specified.
Start-up to Full Load
50% to 100% Load Transient
V IN
(5V/div)
VO
(0.1V/div)
VO
(1V/div)
IO
(2A/div)
IO
(2A/div)
2ms/div
Rev. 2.1 January 2020
100µs/div
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Page 8 of 16
AOZ6605PI
Detailed Description
The AOZ6605PI is a current-mode step down regulator
with integrated high-side NMOS switch and low-side
NMOS switch. It operates from a 4.5V to 18V input
voltage range and supplies up to 5A of load current.
Features include, enable control, Power-On Reset, input
under voltage lockout, output over voltage protection,
external soft-start and thermal shut down.
The AOZ6605PI is available in EPAD-SO8 package.
Enable and Soft Start
The AOZ6605PI has external soft start feature to limit inrush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. The soft start time is programmed by
external soft start capacitor, and can be calculated by
below equation:
Css nF x0.6V
T SS ms = ---------------------------------------5uA
The EN pin of the AOZ6605PI is active high. Connect the
EN pin to VIN if enable function is not used. Pull it to
ground will disable the AOZ6605PI. Do not leave it open.
The voltage on EN pin must be above 2 V to enable the
AOZ6605PI. When voltage on EN pin falls below 0.6V,
the AOZ6605PI is disabled.
signal, at PWM comparator input. If the current signal is
less than the error voltage, the internal high-side switch is
on. The inductor current flows from the input through the
inductor to the output. When the current signal exceeds
the error voltage, the high-side switch is off. The inductor
current is freewheeling through the internal low-side NMOSFET switch to output. The internal adaptive FET
driver guarantees no turn on overlap of both high-side
and low-side switch.
Comparing with regulators using freewheeling Schottky
diodes, the AOZ6605PI uses freewheeling NMOSFET to
realize synchronous rectification. It greatly improves the
converter efficiency and reduces power loss in the lowside switch.
The AOZ6605PI uses a N-Channel MOSFET as the
high-side switch. Since the NMOSFET requires a gate
voltage higher than the input voltage, a boost capacitor is
needed between LX pin and BST pin to drive the gate.
The boost capacitor is charged while LX is low.
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network. In the
application circuit shown in Figure 1. The T-type resistor
divider network includes R1 R2. Usually, a design is
started by picking a fixed R2 value and calculating the
required R1 with equation below.
R 1
V O = 0.6 1 + -------
R 2
Light Load and PWM Operation
Under low output current settings, the AOZ6605PI will
operate with pulse energy mode to obtain high efficiency.
In pulse energy mode, the PWM will not turn off until the
inductor current reaches to 800 mA and the current
signal exceeds the error voltage.
Some standard value of R1, R2 and most used output
voltage values are listed in Table 1.
VO (V)
R1 (k)
R2 (k)
1.0
10
15
Steady-State Operation
1.2
10
10
Under heavy load steady-state conditions, the converter
operates in fixed frequency and Continuous-Conduction
Mode (CCM).
1.5
15
10
1.8
20
10
2.5
31.6
10
3.3
68.1
15
5.0
110
15
The AOZ6605PI integrates an internal N-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error
voltage is compared against the current signal, which is
sum of inductor current signal and ramp compensation
Rev. 2.1 January 2020
Table 1.
Combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
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Page 9 of 16
AOZ6605PI
Protection Features
The AOZ6605PI has multiple protection features to
prevent system circuit damage under abnormal
conditions.
VO
VO
I CIN_RMS = I O --------- 1 – ---------
V IN
V IN
if let m equal the conversion ratio:
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ6605PI employs peak
current mode control, during over current conditions, the
peak inductor current is automatically limited to cycle-by
cycle, and if output drop to some level after current limit,
then the AOZ6605PI will shut down and auto restart with
hiccup mode.
Power-On Reset (POR)
VO
-------- = m
V IN
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure. 2 below. It can be seen that when VO is half of
VIN, CIN is under the worst current stress. The worst
current stress on CIN is 0.5·IO.
A power-on reset circuit monitors the VIN voltage. When
the VIN voltage exceeds 4V, the converter starts
operation. When VIN voltage falls below 3.7V, the
converter will be shut down.
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side NMOS if the junction temperature exceeds
150ºC. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100ºC.
0.4
ICIN_RMS(m) 0.3
IO
0.2
0.1
0
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
Application Information
The basic AOZ6605PI application circuit is show in
Figure 1. Component selection is explained below.
Input Capacitor
The input capacitor must be connected to the VIN pin and
GND pin of AOZ6605PI to maintain steady input voltage
and filter out the pulsing input current. The voltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below::
VO VO
IO
V IN = ----------------- 1 – --------- --------V IN V IN
f C IN
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
Rev. 2.1 January 2020
0.5
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN-RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics. Note
that the ripple current rating from capacitor manufactures
are based on certain amount of life time. Further derating may be necessary in practical design.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage inductance and switching frequency
together decide the inductor ripple current, which is:
VO
VO
I L = ----------- 1 – ---------
V IN
fL
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Page 10 of 16
AOZ6605PI
The peak inductor current is:
1
V O = I L ------------------------8fC
I L
I Lpeak = I O + -------2
O
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20% to
40% of output current.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
VO IL (ESRCO
1
)
8 f CO
V O = I L ESR CO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum are recommended
to be used as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It can
be calculated by:
I L
I CO_RMS = ---------12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
Loop Compensation
The AOZ6605PI employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
f p1
where CO is output capacitor value and ESRCO is the
Equivalent Series Resistor of output capacitor. When low
ESR ceramic capacitor is used as output capacitor, the
impedance of the capacitor at the switching frequency
dominates. Output ripple is mainly caused by capacitor
value and inductor ripple current. The output ripple
voltage calculation can be simplified to:
Rev. 2.1 January 2020
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
1
2 CO RL
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
fZ 1
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1
2 CO ESRCO
Page 11 of 16
AOZ6605PI
where
CO is the output filter capacitor;
Rc fC
RL is load resistor value;
ESRCO is the equivalent series resistance of output
capacitor;
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for the AOZ6605PI. For most cases
a series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ6605PI, FB pin and COMP pin are the
inverting input and the output of internal error amplifier.
A series R and C compensation network connected to
COMP provides one pole and one zero. The pole is:
fp 2
VFB is 0.6V;
GEA is the error amplifier transconductance,
GCS is the current sense circuit transconductance,
which is 8 A/V;
The compensation capacitor Cc and resistor Rc together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. C2 can is selected by:
Equation above can also be simplified to:
Cc
GVEA is the error amplifier voltage gain,
Cc is compensation capacitor in Figure 1;
The zero given by the external compensation network,
capacitor C2 and resistor R3, is located at:
1
2 Cc Rc
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter
bandwidth. Generally a higher bandwidth means faster
response to load transient. However, the bandwidth
should not be too high because of system stability
concern. When designing the compensation loop,
converter stability under all line and load condition must
be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency.
The strategy for choosing Rc and Cc is to set the cross
over frequency with Rc and set the compensator zero
with Cc. Using selected crossover frequency, fC, to
calculate R3:
Rev. 2.1 January 2020
CO RL
Rc
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
GEA is the error amplifier transconductance,
fZ 2
where fC is desired crossover frequency. For best
performance, fc is set to be about 1/10 of switching
frequency:
GEA
2 Cc GVEA
Where
VO
2 Co
VFB GEA GCS
Thermal Management and Layout
Consideration
In the AOZ6605PI buck regulator circuit high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors to the VIN pin, to the LX
pad, to the filter inductor to the output capacitor and load
and then return to the input capacitor through ground.
Current flows in the first loop when the high side switch is
on. The second loop starts from inductor, to the output
capacitors and load, to the low side NMOSFET. Current
flows in the second loop when the low side NMOSFET is
on.
In PCB layout minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input
capacitor, output capacitor and GND pin of the
AOZ6605PI.
In the AOZ6605PI buck regulator circuit, the major power
dissipating components are the AOZ6605PI and the
output inductor. The total power dissipation of converter
circuit can be measured by input power minus output
power.
P total_loss = V IN I IN – V O I O
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Page 12 of 16
AOZ6605PI
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
P inductor_loss = IO2 R inductor 1.1
The actual junction temperature can be calculated with
power dissipation in the AOZ6605PI and thermal
impedance from junction to ambient.
T junction = P total_loss – P inductor_loss JA
The maximum junction temperature of AOZ6605PI is
150ºC, which limits the maximum load current capability.
The thermal performance of the AOZ6605PI is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC will
operate under the recommended environmental
conditions.
Rev. 2.1 January 2020
1. The exposed pad (LX) is connected to internal
Highside FET source and Low-side FET drains.
Connect a large copper plane to LX pin to help thermal dissipation.
2. Do not use thermal relief connection to the VIN and
the GND pin. Pour a maximized copper area to the
GND pin and the VIN pin to help thermal dissipation.
3. Input capacitor should be connected to the VIN pin
and the GND pin as close as possible.
4. Make the current trace from LX pins to L to Co to the
GND as short as possible.
5. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
6. Keep sensitive signal trace away from the LX pad.
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Page 13 of 16
AOZ6605PI
Package Dimensions, SO-8 EP1
Gauge plane
0.2500
D0
C
L
L1
E2
E1
E3
E
L1'
D1
Note 5
D
θ
7 (4x)
A2
e
B
A
A1
Dimensions in millimeters
RECOMMENDED LAND PATTERN
3.70
2.20
5.74
2.71
2.87
0.80
1.27
0.635
UNIT: mm
Dimensions in inches
Symbols
A
Min.
1.40
Nom.
1.55
Max.
1.70
Symbols
A
A1
A2
B
0.00
1.40
0.31
0.05
1.50
0.406
0.10
1.60
0.51
A1
A2
B
C
D
0.17
4.80
—
4.96
C
D
D0
D1
E
e
E1
E2
E3
L
y
θ
| L1–L1' |
L1
3.20
3.10
5.80
—
3.80
2.21
0.25
5.00
3.60
3.50
6.20
—
4.00
2.61
3.40
3.30
6.00
1.27
3.90
2.41
0.40 REF
0.40
0.95
1.27
—
—
0.10
0°
—
3°
0.04
1.04 REF
8°
0.12
D0
D1
E
e
E1
E2
E3
L
y
θ
| L1–L1' |
L1
Min.
0.055
0.000
0.055
0.012
0.007
0.189
Nom.
0.061
Max.
0.067
0.002
0.059
0.016
0.004
0.063
0.020
—
0.010
0.195 0.197
0.126 0.134 0.142
0.122 0.130 0.138
0.228 0.236 0.244
—
0.050
—
0.150 0.153 0.157
0.087 0.095 0.103
0.016 REF
0.016 0.037 0.050
—
—
0.004
0°
3°
8°
—
0.002 0.005
0.041 REF
Notes:
1. Package body sizes exclude mold flash and gate burrs.
2. Dimension L is measured in gauge plane.
3. Tolerance 0.10mm unless otherwise specified.
4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
5. Die pad exposure size is according to lead frame design.
6. Followed from JEDEC MS-012
Rev. 2.1 January 2020
www.aosmd.com
Page 14 of 16
AOZ6605PI
Tape and Reel Dimensions, SO-8, EP1
Carrier Tape
P1
D1
P2
T
E1
E2
E
B0
K0
A0
D0
P0
Feeding Direction
UNIT: mm
Package
SO-8
(12mm)
A0
6.40
±0.10
B0
5.20
±0.10
K0
2.10
±0.10
D0
1.60
±0.10
D1
1.50
±0.10
E
12.00
±0.10
Reel
E1
1.75
±0.10
E2
5.50
±0.10
P0
8.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.10
T
0.25
±0.10
W1
S
G
N
M
K
V
R
H
W
UNIT: mm
W
N
Tape Size Reel Size
M
12mm
ø330
ø330.00 ø97.00 13.00
±0.10 ±0.30
±0.50
W1
17.40
±1.00
H
K
ø13.00
10.60
+0.50/-0.20
S
2.00
±0.50
G
—
R
—
V
—
Leader/Trailer and Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 2.1 January 2020
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min. or
125 empty pockets
Page 15 of 16
AOZ6605PI
Part Marking
AA00
YW LT
Part Number Code
Assembly Lot Code
Year & Week Code
LEGAL DISCLAIMER
Applications or uses as critical components in life support devices or systems are not authorized. AOS does not
assume any liability arising out of such applications or uses of its products. AOS reserves the right to make
changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the
product for their intended application. Customer shall comply with applicable legal requirements, including all
applicable export control rules, regulations and limitations.
AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at:
http://www.aosmd.com/terms_and_conditions_of_sale
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 2.1 January 2020
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
www.aosmd.com
Page 16 of 16
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