AOZ8804ADI

AOZ8804ADI Ultra-Low Capacitance TVS Diode General Description Features The AOZ8804ADI is a transient voltage suppressor array designed to protect high speed data lines such as HDMI, USB 3.0, MDDI, SATA, and Gigabit Ethernet from damaging ESD events.  ESD protection for high-speed data lines: – IEC 61000-4-2, level 4 (ESD) immunity test – Air discharge: ±15kV; contact discharge: ±15kV – IEC61000-4-4 (EFT) 40A (5/50nS) – IEC61000-4-5 (Lightning) 2.5A (8/20µS) – Human Body Model (HBM) ±24kV This device incorporates eight surge rated, low capacitance steering diodes and a TVS in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground.  Array of surge rated diodes with internal TVS diode  Small package saves board space  Protects four I/O lines  Low capacitance between I/O lines: 0.3pF The AOZ8804ADI provides a typical line to line capacitance of 0.3pF and low insertion loss up to 6GHz providing greater signal integrity making it ideally suited for HDMI 1.3 or USB 3.0 applications, such as Digital TVs, DVD players, Computing, set-top boxes and MDDI applications in mobile computing devices.  Low clamping voltage  Low operating voltage: 5.0V Applications  HDMI, USB 3.0, MDDI, SATA ports  Monitors and flat panel displays The AOZ8804ADI comes in a RoHS compliant and Halogen Free 2.5mm x 1.0mm x 0.55mm DFN-10 package and is rated -40°C to +85°C junction temperature range.  Set-top box  Video graphics cards  Digital Video Interface (DVI)  Notebook computers Typical Applications AOZ8804A AOZ8804A AOZ8802A TX2+ TX2D+ D- D+ D- RX2+ RX2- SSRX+ SSRX- SSRX+ SSRX- TX0+ TX0- RX1+ RX1HDMI Receiver RX0+ RX0- SSTX+ SSTX- SSTX+ SSTX- CLK+ CLK- CLK+ CLK- USB 3.0 Transceiver USB 3.0 Connector TX1+ TX1HDMI Transmitter Connector AOZ8804A AOZ8804A Figure 1. USB 3.0 Ports Rev. 6.0 June 2021 Connector AOZ8804A Figure 2. HDMI Ports www.aosmd.com Page 1 of 9 AOZ8804ADI Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ8804ADI -40°C to +85°C DFN-10 RoHS Compliant Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. Pin Configuration CH1 1 10 NC CH2 2 9 NC VN 3 8 VN CH3 4 7 NC CH4 5 6 NC DFN-10 (Top View) Absolute Maximum Ratings Exceeding the Absolute Maximum ratings may damage the device. Parameter Rating Storage Temperature (TS) -65°C to +150°C ESD Rating per IEC61000-4-2, contact ESD Rating per IEC61000-4-2, air (1) ±15kV (1) ±15kV ESD Rating per Human Body Model(2) ±24kV Notes: 1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330Ω. 2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5kΩ. Maximum Operating Ratings The device is not guaranteed to operate beyond the Maximum Operating ratings. Parameter Rating Junction Temperature (TJ) Rev. 6.0 June 2021 -40°C to +125°C www.aosmd.com Page 2 of 9 AOZ8804ADI Electrical Characteristics TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C. Symbol VRWM VBR Parameter Reverse Working Voltage Conditions Between I/O and VN Min. (4) Reverse Breakdown Voltage IT = 1mA, between I/O and VN IR Reverse Leakage Current VRWM = 5V, between I/O and VN VF Diode Forward Voltage IF = 15mA Channel Clamp Voltage Positive Transients Negative Transient VCL Cj Typ. Max. Units 5.0 V (3) 6.0 V 1 µA 1 V IPP = 1A, tp = 100ns, any I/O pin to Ground(5) 12.0 -3.0 V V Channel Clamp Voltage Positive Transients Negative Transient IPP = 5A, tp = 100ns, any I/O pin to Ground(5) 14.0 -5.0 V V Channel Clamp Voltage Positive Transients Negative Transient IPP = 12A, tp = 100ns, any I/O pin to Ground(5) 16.5 -7.0 V V Channel Clamp Voltage Any I/O Pin to Ground IPP = 1A, tp = 8/20µs 12.0 V Channel Input Capacitance 0.70 0.85 VR = 0V, f = 1MHz, between I/O pins 0.30 0.35 pF VR = 0V, f = 1MHz, any I/O pin to Ground 0.60 0.75 pF Notes: 3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level. 4. VBR is measured at the pulse test current IT. 5. Measurements performed using a 100ns Transmission Line Pulse (TLP) system. Rev. 6.0 June 2021 www.aosmd.com Page 3 of 9 AOZ8804ADI Typical Performance Characteristics Forward Voltage vs. Forward Peak Pulse Current I/O – Gnd Insertion Loss (S21) vs. Frequency (tperiod = 100ns, tr = 1ns) 8 0.00E+00 -5.00E+00 6 -1.00E+01 5 S21 (dB) Forward Voltage (V) 7 4 3 -1.50E+01 -2.00E+01 2 -2.50E+01 1 0 -3.00E+01 0 2 4 6 8 10 Forward Current, IPP (A) 12 1 14 (tperiod = 100ns, tr = 1ns) 10000 -20 14 Insertion Loss (dB) Clamping Voltage, VCL (V) 1000 0 16 12 10 8 6 -40 -60 -80 -100 4 2 -120 0 2 4 6 8 10 Peak Puse Current, IPP (A) 12 1 14 1E-12 Differential Signal (V) 8E-13 6E-13 4E-13 2E-13 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 Frequency (MHz) Rev. 6.0 June 2021 10 100 Frequency (MHz) 1000 10000 USB3.0 Eye Diagram with AOZ8804A (5Gbps) Capacitance vs. Frequency (IO to GND) Capacitance (F) 100 Frequency (MHz) Analog Crosstalk (I/O–I/O) vs. Frequency Clamping Voltage vs. Peak Pulse Current 18 10 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Unit Intervals www.aosmd.com Page 4 of 9 AOZ8804ADI TDR for HDMI 1.3 The AOZ8804ADI TDR test results indicates the minimal effect the low capacitance has on the HDMI 1.3 TDR measurements. Figure 3 and Figure 4 below are the graphs from the TDR measurements. The two graphs show the before and after results of the TDR differential data line of the HDMI when the AOZ8804ADI was populated onto the PCB. The use of "Skinny Traces" can further limit the TDR to within 100 ± 5. Below are the TDR measurements with the use of skinny traces to compensate the added capacitor from the AOZ8804. Figure 3 shows the increase in impedance from the skinny traces between M1 and M2 cursors. With the increase in impedance the AOZ8804ADI added capacitor will now reduce the TDR within the 100 ± 5. 125 125 120 120 115 115 110 110 105 105 100 100 95 95 90 90 85 85 80 80 75 -0.2500 ns (Step 2.56 ps) 0.2000 ns/ 75 1.7500 ns Figure 3. Compensated Stripe-Line -0.2500 ns (Step 2.56 ps) 0.2000 ns/ 1.7500 ns Figure 4. Compensated Stripe-Line with AOZ8804ADI Device on the Board Figure 5 shows the graphical representation of the scope photo of the TDR and the PCB board. The cursor M1 represent the edge of the connector in which the equipment was calibrated to. The cursor M2 represent the leveling off of the100 when the signal passes through the AOZ8804ADI. Compensated Stripe-Line M1 M1 Number of Layers 4 Copper Trace Thickness 1.4 mils Dielectric Constant, r 4.6 Overall Board Thickness 62 mils Dielectric Thickness Between Top and Ground Layer 10 mils AOZ8804A Figure 5. AOS HDMI Compensated Evaluation Board Rev. 6.0 June 2021 www.aosmd.com Page 5 of 9 AOZ8804ADI High Speed PCB Layout Guidelines Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. The location of the protection devices on the PCB is the simplest and most important design rule to follow. The AOZ8804ADI devices should be located as close as possible to the noise source. The placement of the AOZ8804ADI devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8804ADI devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8804ADI device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC’s signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS’s clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The AOZ8804ADI ultra-low capacitance TVS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. The AOZ8804ADI is designed for the ease of PCB layout by allowing the traces to run underneath the device. The pinout of the AOZ8804ADI is designed to simply drop onto the IO lines of a High Definition Multimedia Interface (HDMI) or USB 3.0 design without having to divert the signal lines that may add more parasitic inductance. Pins 1, 2, 4 and 5 are connected to the internal TVS devices and pins 6, 7, 9 and 10 are no connects. The no connects was done so the package can be securely soldered onto the PCB surface. Clock Clock SSRX+ SSRX+ Data0 Data0 SSRX– SSRX– Ground Ground Ground Data1 Data1 SSTX+ SSTX+ Data2 Data2 SSTX– SSTX– Ground Figure 6. Flow Through Layout for HDMI Rev. 6.0 June 2021 Figure 7. Flow Through Layout for USB 3.0 www.aosmd.com Page 6 of 9 AOZ8804ADI High Speed PCB Layout Guidelines (Continued) Based on the AOZ8804ADI DFN-10 package design a very straight forward layout can be achieved. To give the TDR an extra level of margin the traces may be compensated to have a nominal impedance of 90Ω for USB or 100Ω for HDMI throughout the differential pair. To make the design perfect the added capacitance of the device will have to be compensated by the use of “Skinny Traces”. The skinny traces are a narrow stripe line acting to lower the parasitic capacitance on the differential stripe line. The differential impedance of the transmission line becomes well centered to 90Ω or to 100Ω. A layout EM field simulator is recommended before fabrication to insure a perfect stripe line. With careful layout and placement of the device, the AOZ8804ADI can protect the USB 3.0 and HDMI data line effectively and safely and meet the ESD immunity requirements of the IEC61000-4-2, level 4, ±15kV air discharge, ±8kV contact discharge. Figure 8. USB 3.0 PCB Layout with Compensated Traces Number of Layers 4 Copper Trace Thickness 1.4 mils Dielectric Constant, r 4.6 Overall Board Thickness 62 mils Dielectric Thickness Between Top and Ground Layer 10 mils . Rev. 6.0 June 2021 www.aosmd.com Page 7 of 9 AOZ8804ADI Figure 9. HDMI PCB Layout with Compensated Traces Rev. 6.0 June 2021 Number of Layers 4 Copper Trace Thickness 1.4 mils Dielectric Constant, r 4.6 Overall Board Thickness 62 mils Dielectric Thickness Between Top and Ground Layer 10 mils www.aosmd.com Page 8 of 9 AOZ8804ADI LEGAL DISCLAIMER Applications or uses as critical components in life support devices or systems are not authorized. AOS does not assume any liability arising out of such applications or uses of its products. AOS reserves the right to make changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the product for their intended application. Customer shall comply with applicable legal requirements, including all applicable export control rules, regulations and limitations. AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at: http://www.aosmd.com/terms_and_conditions_of_sale LIFE SUPPORT POLICY ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 6.0 June 2021 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 9 of 9