AOZ8904CIL

AOZ8904CIL Ultra-Low Capacitance TVS Diode General Description Features The AOZ8904CIL is a transient voltage suppressor array designed to protect high speed data lines from Electro Static Discharge (ESD) and lightning. • ESD protection for high-speed data lines: This device incorporates eight surge rated, low capacitance steering diodes and a Transient Voltage Suppressor (TVS) in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (±15kV air, ±8kV contact discharge). The AOZ8904CIL comes in a Halogen Free and RoHS compliant SOT-23 and SC-70 packages. It is rated over a -40°C to +85°C ambient temperature range. – Exceeds: IEC 61000-4-2 (ESD) ±24kV (air), ±24kV (contact) – IEC 61000-4-5 (Lightning) 4A (8/20µs) – Human Body Model (HBM) ±24kV • Small package saves board space • Low insertion loss • Protects four I/O lines • Low clamping voltage • Low operating voltage: 5.0V Applications • USB 2.0 Power and Data Line Protection • Video Graphics Cards • Monitors and Flat Panel Displays • Digital Video Interface (DVI) Typical Application USB Host Controller +5V Downstream Ports VBUS RT D+ RT DVBUS GND AOZ8904 +5V VBUS RT D+ RT DGND Figure 1. 2 USB High Speed Ports Rev. 3.1 September 2021 www.aosmd.com Page 1 of 7 AOZ8904CIL Ordering Information Part Number Ambient Temperature Range AOZ8904CIL -40°C to +85°C AOZ8904HIL Package Environmental SOT-23-6 RoHS Compliant Green Product SC-70-6 AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. Pin Configuration CH1 1 6 CH4 VN 2 5 VP CH2 3 4 CH3 SOT-23-6 / SC-70-6 (Top View) Absolute Maximum Ratings Exceeding the Absolute Maximum ratings may damage the device. Parameter Rating VP – VN 6V Peak Pulse Current (IPP), tP = 8/20µs 4A Peak Power Dissipation (8 x 20µs@ 25°C) 50W Storage Temperature (TS) -65°C to +150°C ESD Rating per IEC61000-4-2, contact(1) ±24kV ESD Rating per IEC61000-4-2, air(2) ±24kV Model(2) ±24kV ESD Rating per Human Body Junction Temperature (TJ) -40°C to +125°C Notes: 1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330Ω. 2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5kΩ. Rev. 3.1 September 2021 www.aosmd.com Page 2 of 7 AOZ8904CIL Electrical Characteristics TA = 25°C unless otherwise specified Symbol VRWM VBR Parameter Reverse Working Voltage Conditions Between pin 5 and 2 Min. (5) Reverse Breakdown Voltage IT = 1mA, between pins 5 and 2 IR Reverse Leakage Current VRWM = 5V, between pins 5 and 2 VF Diode Forward Voltage If = 15mA VCL Channel Clamp Voltage Positive Transients Negative Transient IPP = 1A, tp = 100ns, any I/O pin to Ground(3)(6)(8) Channel Clamp Voltage Positive Transients Negative Transient IPP = 5A, tp = 100ns, any I/O pin to Ground(3)(6)(8) Channel Clamp Voltage Positive Transients Negative Transient IPP = 12A, tp = 100ns, any I/O pin to Ground(3)(6)(8) Junction Capacitance VR = 0V, f = 1Mhz, any I/O pin to Ground(3)(7) Cj Cj Channel Input Capacitance Matching Typ. (4) VR = 0V, f = 1Mhz, between I/O Units 5.5 V 6.6 0.7 pins(3)(7) Max. V 0.85 1 µA 0.95 V 11.00 -2.00 V V 14.00 -3.50 V V 18.00 -5.00 V V 1.25 1.3 pF 0.03 pF Notes: 3. These specifications are guaranteed by design. 4. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level. 5. VBR is measured at the pulse test current IT. 6. Measurements performed with no external capacitor on VP (Pin 5 floating). 7. Measurements performed with VP biased to 3.3 Volts (Pin 5 @ 3.3V). 8. Measurements performed using a 100 nSec Transmission Line Pulse (TLP) system. Rev. 3.1 September 2021 www.aosmd.com Page 3 of 7 AOZ8904CIL Typical Performance Characteristics I/O – Gnd Insertion Loss (S21) vs. Frequency Clamping Voltage vs. Peak Pulse Current (Vp = 3.3V) (tperiod = 100ns, tr = 1ns) 16 Insertion Loss (dB) Clamping Voltage, VCL (V) 17 15 14 13 12 11 10 9 0 2 4 6 8 10 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1 12 10 100 1000 Frequency (MHz) Peak Pulse Current, IPP (A) Forward Voltage vs. Forward Current Analog Crosstalk (I/O–I/O) vs. Frequency (tperiod = 100nS, tr = 1ns) 7 20 Insertion Loss (dB) Forward Voltage (V) 6 5 4 3 2 1 0 -20 -40 -60 -80 0 0 2 4 6 8 10 10 12 100 1000 Frequency (MHz) Forward Current, IPP (A) I/O – I/O Insertion Loss (S21) vs. Frequency Insertion Loss (dB) (Vp = Float) 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1 10 100 1000 Frequency (MHz) Rev. 3.1 September 2021 www.aosmd.com Page 4 of 7 AOZ8904CIL Application Information The AOZ8904CIL TVS is design to protect four data lines from fast damaging transient over-voltage by clamping it to a reference. When the transient on a protected data line exceed the reference voltage the steering diode is forward bias thus, conducting the harmful ESD transient away from the sensitive circuitry under protection. PCB Layout Guidelines Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. The location of the protection devices on the PCB is the simplest and most important design rule to follow. The AOZ8904CIL devices should be located as close as possible to the noise source. The placement of the AOZ8904CIL devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8904CIL devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8904CIL device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC’s signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS’s clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The AOZ8904CIL ultra-low capacitance TVS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: 1. Place the TVS near the IO terminals or connectors to restrict transient coupling. 2. Fill unused portions of the PCB with ground plane. 3. Minimize the path length between the TVS and the protected line. 4. Minimize all conductive loops including power and ground loops. 5. The ESD transient return path to ground should be kept as short as possible. 6. Never run critical signals near board edges. 7. Use ground planes whenever possible. 8. Avoid running critical signal traces (clocks, resets, etc.) near PCB edges. 9. Separate chassis ground traces from components and signal traces by at least 4mm. 10. Keep the chassis ground trace length-to-width ratio