PA08

PA08 • PA08A Power Operational Amplifier RoHS COMPLIANT FEATURES • • • • Wide Supply Range — ±15V to ±150V Programmable Output Current Limit Output Current — Up to ±150mA Low Bias Current — FET Input APPLICATIONS • • • • High Voltage Instrumentations Electrostatic Transducers & Deflection Programmable Power Supplies up to 290V Analog Simulators 4 - 20mA DESCRIPTION The PA08 is a high voltage operational amplifier designed for output voltage swings of up to ±145V with a dual (±) supply or 290V with a single supply. High accuracy is achieved with a cascode input circuit configuration. All internal biasing is referenced to a zener diode fed by a FET constant current source. As a result, the PA08 features an unprecedented supply range and excellent supply rejection. The output stage is biased-on for linear operation. Internal phase compensation assures stability at all gain settings. The safe operating area (SOA) can be observed with all types of loads by choosing the appropriate current limiting resistors. For operation into inductive loads, two external flyback pulse protection diodes are recommended. A heatsink may be necessary to maintain the proper case temperature under normal operating conditions. This hybrid integrated circuit utilizes beryllia (BeO) substrate, thick film resistors, ceramic capacitors and semiconductor chips to maximize reliability, minimize size and give top performance. Ultrasonically bonded aluminum wires provide reliable interconnections at all operating temperatures. The 8-pin TO-3 package is hermetically sealed and electrically isolated. The use of compressible thermal isolation washers and/or improper mounting torque will void the product warranty. Please see Application Note 1, “General Operating Considerations.” Figure 1: Equivalent Schematic 3 7 D1 C1 Q2 Q1 Q3 Q4 C3 Q5 Q6 2 Q8 Q9 Q7 C2 1 C4 Q10 Q11 Q19 5 8 4 Q12A Q12B Q17 Q16 Q15 D2 6 www.apexanalog.com © Apex Microtechnology Inc. All rights reserved JAN 2018 PA08U Rev Q PA08 • PA08A TYPICAL CONNECTIONS Figure 2: Typical Connections RS = (| +V S| + | -V S| ) RT/1.6 RF +V S 100nF * RI RCL+ +V S + V OUT +CL OUT -CL PA08 RCL- BAL -V S RL RS RT 100nF * -V S Note: Input offset voltage trim optional. RT = 10 kΩ MAX. * Use 10μF per Amp of output current. 2 PA08U Rev Q PA08 • PA08A PINOUT AND DESCRIPTION TABLE Figure 3: External Connections Pin Number Name Description 1 OUT The output. Connect this pin to load and to the feedback resistors. 2 +CL Connect to the sourcing current limit resistor. Output current flows out of this pin through RCL+. The output pin and the load are connected to the other side of RCL+. 3 +Vs The positive supply rail. 4 +IN The non-inverting input. 5 -IN The inverting input. 6 -Vs The negative supply rail. 7 BAL Balance Control pin. Adjusts voltage offset. See applicable section. 8 -CL Connect to the sinking current limit resistor. Output current flows into this pin through RCL-. The output pin and the load are connected to the other side of RCL-. PA08U Rev Q 3 PA08 • PA08A SPECIFICATIONS The power supply voltage specified under typical (TYP) applies unless otherwise noted. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Max Units +Vs to -Vs 300 V Output Current, within SOA IO 200 mA Power Dissipation, internal @ Tc = 25°C PD 17.5 W Supply Voltage, total Input Voltage, differential Input Voltage, common mode Min VIN (Diff) -50 50 V Vcm -VS VS V 350 °C 175 °C -65 +150 °C -55 +125 °C Temperature, pin solder, 10s max. Temperature, junction 1 TJ Temperature Range, storage TC Operating Temperature Range, case 1. Long term operation at the maximum junction temperature will result in reduced product life. Derate power dissipation to achieve high MTTF. CAUTION The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or subject to temperatures in excess of 850°C to avoid generating toxic fumes. INPUT Parameter Test Conditions PA08 Min PA08A Typ Max Min Typ Max Units Offset Voltage, initial Tc =25°C ±0.5 ±2 ±0.25 ±0.5 mV Offset Voltage vs. Temperature Tc =-25 to +85°C ±15 ±30 ±5 ±10 µV/°C Offset Voltage vs. Supply Tc =25°C ±0.5 * 2 µV/V Offset Voltage vs. Time Tc =25°C ±75 * Bias Current, initial 1 Tc =25°C 5 Bias Current vs. Supply Tc =25°C 0.01 Offset Current, initial 1 Tc =25°C ±2.5 Input Impedance, DC Tc =25°C 1011 * Ω Input Capacitance Tc =25°C 4 * pF Common Mode Voltage Range2 Tc =-25 to +85°C ±Vs-10 Common Mode Rejection, DC Tc =-25 to +85°C, VCM= ±90V 50 3 µV/√kh 10 * ±50 ±1.5 * 130 pA pA/V ±10 pA V * dB 1. Doubles for every 10°C of temperature increase. 2. +VS and –VS denote the positive and negative power supply rail respectively. 4 PA08U Rev Q PA08 • PA08A GAIN Parameter Test Conditions Open Loop Gain @ 10 Hz Tc = 25°C, RL= ∞ Open Loop Gain @ 10 Hz Tc = 25°C, RL = 1.2 kΩ Gain Bandwidth Product at 1MHz Tc = 25°C, RL = 1.2 kΩ Power Bandwidth Phase Margin PA08 Min Typ PA08A Max Min 118 Typ Max Units * dB * dB 5 * MHz Tc = 25°C, RL= 1.2 kΩ 90 * kHz Tc =-25 to +85°C 60 * ° Test Conditions PA08 PA08A 96 111 * OUTPUT Parameter Min Typ Max Min Typ Max Units Voltage Swing 1 Tc = 25°C, IO= 150mA ±Vs-15 ±Vs-8 * * V Voltage Swing 1 Tc =-25 to +85°C, ±Vs-10 IO= ±75mA ±Vs-5 * * V Voltage Swing 1 Tc =-25 to +85°C, IO= ±20mA ±Vs-3 * * V Current, peak Tc = 85°C Slew rate Tc = 25°C Capacitive Load, AV = 1 Tc =-25 to +85°C 10 * Capacitive Load, AV > 4 Tc =-25 to +85°C SOA * Settling Time to 0.1% Tc = 25°C, RL= 1.2 kΩ, 2V step ±Vs-5 150 * 30 20 1 mA * V/µs * nF µs 1. +VS and –VS denote the positive and negative power supply rail respectively. POWER SUPPLY PA08 PA08A Test Conditions Min Typ Max Min Typ Max Voltage Tc=-55 to +125°C ±15 ±100 ±150 * * * V Current, quiescent Tc = 25°C 6 8.5 * * mA Parameter PA08U Rev Q Units 5 PA08 • PA08A THERMAL Parameter Test Conditions PA08 Min Typ Resistance, AC, junction to case1 Tc=-55 to +125°C F > 60 Hz 4.26 Resistance, DC, junction to case Tc=-55 to +125°C F < 60 Hz 6.22 Resistance, junction to air Tc=-55 to +125°C 30 Temperature Range, case Meets full range specification -25 PA08A Max Min Typ Max * 8.57 * °C/W * * 85 * Units °C/W °C/W * °C 1. Rating applies only if output current alternates between both output transistors at a rate faster than 60 Hz. Note: * The specification of PA08A is identical to the specification for PA08 in applicable column to the left. 6 PA08U Rev Q PA08 • PA08A TYPICAL PERFORMANCE GRAPHS Figure 4: Power Derating Figure 5: Current Limit 250 17.5 200 Current Limit, ILIM (mA) /ŶƚĞƌŶĂůWŽǁĞƌŝƐƐŝƉĂƟŽŶ͕WD (W) 20 15 12.5 10 7.5 5 100 RCLсϭϬɏ 50 2.5 0 0 25 50 75 100 125 0 -55 150 -25 0 25 50 75 100 Case Temperature, TC (°C) Case Temperature, TC (°C) Figure 6: Small Signal Response Figure 7: Phase Response 125 0 120 RLсϭ͘ϮŬɏ 100 RLсϭ͘ϮŬɏ -30 -60 80 Phase, ˇ;Σ) Open Loop Gain, AOL (dB) RCLсϰ͘ϳɏ 150 60 40 -90 -120 20 -150 0 -180 -20 1 10 100 1k 10k 0.1M 1M 10M Frequency, F (Hz) PA08U Rev Q -210 0 10 100 1k 10k 0.1M 1M 10M &ƌĞƋƵĞŶĐLJ͕&;,njͿ 7 PA08 • PA08A Figure 8: Open Loop Gain Figure 9: Power Response 300 R>сϭ͘ϮŬɏ 4 T = C 25° TC = C 85° 2 C 0 TC = -25 °C -2 100 60 |+VS| + |–VS| = 100V 30 -4 -6 30 50 100 150 200 250 15 50k 300 .1M .2M .3M .5M .7M 1M Total Supply Voltage, VS (V) Frequency, F (Hz) Figure 10: Pulse Response Figure 11: Slew Rate 6 1.6 4 1.4 Normalized Slew Rate (X) Output Voltage, VO (V) |+VS| + |–VS| = 300V 200 Output Voltage, VO (VP-P) ZĞůĂƟǀĞKƉĞŶ>ŽŽƉ'ĂŝŶ͕;ĚͿ 6 2 0 -2 -4 RLсϭ͘ϮŬɏ 1.2 1.0 0.8 0.6 VIN = ±5V, tr = 100ns -6 0 0.5 1 1.5 Time, t (μs) 8 2.0 2.5 0.4 30 50 100 150 200 250 300 Total Supply Voltage, VS (V) PA08U Rev Q PA08 • PA08A Figure 12: Input Noise Figure 13: Common Mode Rejection 140 ŽŵŵŽŶDŽĚĞZĞũĞĐƟŽŶ͕DZ;Ě) Input Noise Voltage, VN (Ŷsͬя,nj) 20 15 10 6 4 120 100 80 60 40 20 0 2 10 100 1k 10k 1 0.1M 10 1k 10k 0.1M 1M Frequency, F (Hz) Frequency, F (Hz) Figure 14: Power Supply Rejection Figure 15: Common Mode Voltage 300 Common Mode Voltage, VCM (VP-P) 140 WŽǁĞƌ^ƵƉƉůLJZĞũĞĐƟŽŶ͕W^Z;Ě) 100 120 100 80 +VS 60 –VS 40 20 0 1 10 100 1k 10k Frequency, F (Hz) PA08U Rev Q 0.1M 1M |+VS| + |–VS| = 300V 200 100 60 |+VS| + |–VS| = 100V 30 15 10k 20k 50k 0.1M 0.2M 0.5M 1M Frequency, F (Hz) 9 PA08 • PA08A SAFE OPERATING AREA (SOA) The output stage of most power amplifiers has two distinct limitations: 1. The current handling capability of the transistor geometry and the wire bonds. 2. The second breakdown effect which occurs whenever the simultaneous collector current and collectoremitter voltage exceeds specified limits. The SOA curves combine the effect of these limits. For a given application, the direction and magnitude of the output current should be calculated or measured and checked against the SOA curves. This is simple for resistive loads but more complex for reactive and EMF generating loads. However, the guidelines on the next page may save extensive analytical efforts. Figure 16: SOA t= 150 t= 100 50 1m s 0. 2m s 0. 5m s s 80 t= 5m st ea dy t= Output Current From +VS or - VS (mA) 200 st at e 40 30 20 80 100 120 150 170 200 250 300 ^ƵƉƉůLJƚŽKƵƚƉƵƚŝīĞƌĞŶƟĂů͕VS-VO (V) 10 PA08U Rev Q PA08 • PA08A 1. Under transient conditions, the following capacitive and inductive loads are safe with the current limits set to the maximum: ±VS C (Max) L (Max) 150V 0.4µF 280 mH 125V 0.9µF 380 mH 100V 2μF 500 mH 75V 10μF 1200 mH 50V 100μF 13 H 2. The amplifier can handle any EMF generating or reactive load and short circuits to the supply rails or simple shorts to common if the current limits are set as follows: ±VS Short to C, L, or EMF Load Short to Common 150V 20mA 67mA 125V 27mA 90mA 100V 42mA 130mA 75V 67mA 200mA 50V 130mA 200mA These simplified limits may be exceeded with further analysis using the operating conditions for a specific application. 3. The output stage is protected against transient flyback. However, for protection against sustained, high energy flyback, external fast-recovery diodes should be used. PA08U Rev Q 11 PA08 • PA08A GENERAL Please read Application Note 1 “General Operating Considerations” which covers stability, supplies, heat sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www.apexanalog.com for Apex Microtechnology’s complete Application Notes library, Technical Seminar Workbook, and Evaluation Kits. TYPICAL APPLICATION Figure 17: Typical Application (ATE Pin Driver) The PA08 as a pin driver is capable of supplying high test voltages to a device under test (DUT). Due to the possibility of short circuits to any terminal of the DUT, current limit must be set to be safe when limiting with a supply to output voltage differential equal to the amplifier supply plus the largest magnitude voltage applied to any other pin of the DUT. In addition, flyback diodes are recommended when the output of the amplifier exits any equipment enclosure to prevent damage due to electrostatic discharges. Refer to Application Note 7 for details on accuracy considerations of this circuit. INDUCTIVE LOADS Two external diodes as shown in Figure 18, are required to protect these amplifiers from flyback (kickback) pulses exceeding the supply voltages of the amplifier when driving inductive loads. For component selection, these external diodes must be very quick, such as ultra fast recovery diodes with no more than 200 nanoseconds of reverse recovery time. The diode will turn on to divert the flyback energy into the supply rails thus protecting the output transistors from destruction due to reverse bias. A note of caution about the supply. The energy of the flyback pulse must be absorbed by the power supply. As a result, a transient will be superimposed on the supply voltage, the magnitude of the transient being a function of its transient impedance and current sinking capability. If the supply voltage plus transient exceeds the maximum supply rating or if the AC impedance of the supply is unknown, it is best to clamp the output and the supply with a zener diode to absorb the transient. 12 PA08U Rev Q PA08 • PA08A INPUT PROTECTION The input is protected against common mode voltages up to the supply rails and differential voltages up to ±50V. Increased protection against differential input voltages can be obtained by adding 2 resistors, 2 capacitors and 4 diode connected FETs as shown in Figure 19. Figure 18: Protection, Inductive Load Figure 19: Protection, Overvoltage CURRENT LIMITING Proper operation requires the use of two current limit resistors, connected as shown in the typical connection diagram. The minimum value for RCL is 3.24 Ω. However, for optimum reliability it should be set as high as possible. Refer to Application Note 1 and 9 for current limit adjust details. BALANCE CONTROL (OFFSET NULL) The input biasing of PA08 can be adjusted externally to provide better input offset voltage (VOS) characteristics on a part-to-part basis. Use the equations in the Typical Connection Diagram (figure 2) to determine values for RT(trim-pot) and RS(static resistor). RS will have a value many times that of RT, meaning RS will PA08U Rev Q 13 PA08 • PA08A experience almost the entire supply voltage. Rate for proper power dissipation. Adjust the wiper on RT until input offset voltage is reduced to a minimum. If offset nulling is not required for the application, pin 7 should be left open. Omit RS and RT. 14 PA08U Rev Q PA08 • PA08A PACKAGE OPTIONS PACKAGE DESIGN CE NEED TECHNICAL HELP? CONTACT APEX SUPPORT! For all Apex Microtechnology product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact apex.support@apexanalog.com. International customers can also request support by contacting their local Apex Microtechnology Sales Representative. To find the one nearest to you, go to www.apexanalog.com IMPORTANT NOTICE Apex Microtechnology, Inc. has made every effort to insure the accuracy of the content contained in this document. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (expressed or implied). Apex Microtechnology reserves the right to make changes without further notice to any specifications or products mentioned herein to improve reliability. This document is the property of Apex Microtechnology and by furnishing this information, Apex Microtechnology grants no license, expressed or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. 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