PA240CX

PA240 PA240 P r oo dd uPA240 u cc tt IInnnnoovvaatti ioonn FFr roomm High Voltage Power Operational Amplifier FEATURES DDPAK PKG. STYLE CC • RoHS COMPLIANT • MONOLITHIC MOS TECHNOLOGY • LOW COST • HIGH VOLTAGE OPERATION—350V • LOW QUIESCENT CURRENT TYP.—2.2mA • NO SECOND BREAKDOWN • HIGH OUTPUT CURRENT—120 mA PEAK TO-220 STAGGERED LEADS PKG. STYLE CX APPLICATIONS • TELEPHONE RING GENERATOR • PIEZO ELECTRIC POSITIONING • ELECTROSTATIC TRANSDUCER & DEFLECTION • DEFORMABLE MIRROR FOCUSING • PACKAGING OPTIONS 7 TO-220 with staggered Lead Form (PA240CX) 7 DDPAK Surface Mount Package (PA240CC) DESCRIPTION The PA240 is a high voltage monolithic MOSFET operational amplifier achieving performance features previously found only in hybrid designs while increasing reliability. Inputs are protected from excessive common mode and differential mode voltages. The safe operating area (SOA) has no second breakdown limitations. External compensation provides the user flexibility in choosing optimum gain and bandwidth for the application. The PA240 is packaged in two standard package designs. The surface mount version of the PA240, the PA240CC, is an industry standard non-hermetic plastic 7-pin DDPAK. The through hole version of the PA240, the PA240CX, is an industry standard non-hermetic plastic 7-pin TO-220 package. The PA240CX is a staggered lead formed option that offers industry standard 100 mil spacing. This allows for easier PC board layout. (Please refer to package drawings for outline dimensions.) 3 Q1 VIN 20R +175 +175 CC 10pF CC 10pF A1 PA240 A2 PA240 PIEZO TRANSDUCER CN LOW COST 660V p-p PIEZO DRIVE EXTERNAL CONNECTIONS RN –175 PA240CX PA240CC I OUT Q5 Q6 D5 COMP Q8 Q12 Q13 D4 2 7 Q11 Q10 Q14 –VS 4 SUB www.cirrus.com A -IN +IN +Vs -Vs OUT COMP (Cc) COMP (Cc) 6 COMP –IN A 5 -IN +IN +Vs -Vs OUT COMP (Cc) COMP (Cc) Q4 1 PA240U 20R 20R R Q2 Q3 +IN Reference Application Notes 3, 20 and 25 +VS D1 D3 TYPICAL APPLICATION –175 EQUIVALENT SCHEMATIC D2 High voltage considerations should be taken when designing board layouts for the PA240. The PA240 may require a derate in supply voltage depending on the spacing used for board layout. The 15-mil and 14-mil minimum spacing of the 7 TO-220 and 7 DDPAK respectively is adequate to standoff the 350V rating of the PA240. However, a supply voltage derate to 250V is required if the spacing of circuit board artwork is less than 11 mils. In cases where the PA240 is used to its maximum voltage rating, the PA240CX is recommended given that the staggered lead form allows for 100-mil standard spacing. The metal tabs of both the PA240CC and PA240CX packages are directly tied to -Vs. For CC values, see graph on page 3. Note: CC must be rated for full supply voltage. Copyright © Cirrus Logic, Inc. 2010 (All Rights Reserved) AUG 20101 APEX − PA240UREVG PA240 Product Innovation From ABSOLUTE MAXIMUM RATINGS SUPPLY VOLTAGE, +VS to –VS OUTPUT CURRENT, continuous within SOA OUTPUT CURRENT, peak3 POWER DISSIPATION, continuous @ TC = 25°C INPUT VOLTAGE, differential INPUT VOLTAGE, common mode TEMPERATURE, pin solder – 10 sec TEMPERATURE, junction2 TEMPERATURE, storage TEMPERATURE RANGE, powered (case) SPECIFICATIONS PARAMETER TEST CONDITIONS1 INPUT OFFSET VOLTAGE, initial OFFSET VOLTAGE, vs. temperature3 OFFSET VOLTAGE, vs. temperature3 OFFSET VOLTAGE, vs supply OFFSET VOLTAGE, vs time BIAS CURRENT, initial BIAS CURRENT, vs supply OFFSET CURRENT, initial INPUT IMPEDANCE, DC INPUT CAPACITANCE COMMON MODE, voltage range COMMON MODE, voltage range COMMON MODE REJECTION, DC NOISE, broad band NOISE, low frequency GAIN OPEN LOOP at 15Hz BANDWIDTH, gain bandwidth product POWER BANDWIDTH OUTPUT VOLTAGE SWING CURRENT, peak3 CURRENT, continuous SETTLING TIME to .1% SLEW RATE RESISTANCE4, 1mA RESISTANCE4, 40 mA 25°C to 85°C -25°C to 25°C VCM = ±90V DC 10kHz BW, RS = 1K 1-10 Hz RL = 5K 280V p-p IO = 40mA 10V step, A V = –10 CC = 3.3pF RCL = 0 RCL = 0 POWER SUPPLY VOLTAGE CURRENT, quiescent THERMAL RESISTANCE, AC junction to case RESISTANCE, DC junction to case RESISTANCE, junction to air (CX) RESISTANCE, junction to air (CC)5 TEMPERATURE RANGE, case NOTES: 1. 2. 3. 4. 5. CAUTION 2 F > 60Hz F < 60Hz Full temperature range Full temperature range Meets full range specifications MIN PA240 TYP 350V 60 mA 120 mA 14W ±16 V ±VS 220°C 150°C –65 to +150°C –40 to +125°C MAX UNITS 40 250 500 +VS–14 -VS+12 84 25 100 270 3 70 50 2 50 1011 6 94 50 125 mV µV/°C µV/°C µV/V µV/kh pA pA/V pA Ω pF V V dB µV RMS µV p-p 90 96 3 30 dB MHz kHz ±VS–12 120 60 ±VS–10 V mA mA µs V/µs Ω Ω ±50 ±150 2.2 ±175 2.5 V mA –25 5.9 7.7 60 27 25 6.85 8.9 °C/W °C/W °C/W °C/W °C 130 200 200 2 30 150 5 +85 Unless otherwise noted TC = 25°C, CC = 6.8pF. DC input specifications are ± value given. Power supply voltage is typical rating. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to achieve high MTTF. For guidance, refer to heatsink data sheet. Guaranteed but not tested. Since the PA240 has no current limit, load impedance must be large enough to limit output current to 120mA. Heat tab attached to 3/32" FR-4 board with 2oz. copper. Topside copper area (heat tab directly attached) = 1000 sq. mm, backside copper area = 2500 sq. mm, board area = 2500 sq. mm. The PA240 is constructed from MOSFET transistors. ESD handling procedures must be observed. PA240U PA240 14 10 VDROP FROM VS, (V) 12 12 10 8 6 4 OPEN LOOP GAIN, A (dB) VDROP+ @85°C 8 6 VDROP+ @25°C VDROP- @25°C 4 0 125 SMALL SIGNAL RESPONSE 10 15pF 20 68pF -120 .75pF -130 -140 68pF 6.8pF -150 -160 0 -170 100 -180 10K 1K 10K 100K 1M 10M FREQUENCY, F (Hz) 10M SLEW RATE HARMONIC DISTORTION 10 100K 1M FREQUENCY, F (Hz) 30V P-P 60V P-P 0.1 180V P-P 0.01 AV = 20 CC = 15pF RL = 2K 0.001 100 120 1K 10K FREQUENCY, F (Hz) COMMON MODE REJECTION 100 80 60 40 20 0 10 PA240U 10K 100 1K FREQUENCY, F (Hz) 100K 25 15 0 0 10 20 30 40 50 60 70 COMPENSATION CAPACITANCE, CC (pF) 100K POWER SUPPLY REJECTION, PSR (dB) 1 SLEW RATE, (V/µs) 35 100 TC = 85°C TC = 55°C 1 TC = 25°C 1000 15pF -110 60 40 PHASE RESPONSE -100 6.8pF -20 10 DISTORTION, (%) TC = 125°C 0.1 1 20 40 60 80 100 120 OUTPUT CURRENT, IO (mA) -90 .75pF 80 0 OUTPUT VOLTAGE, (VOUT)(p-p) 25 50 75 100 TEMPERATURE, T (°C) GAIN AND COMPENSATION VDROP- @85°C NORMALIZED QUIESCENT CURRENT (%) 0 100 COMMON MODE REJECTION, CMR (dB) 100 2 2 0 OUTPUT VOLTAGE SWING COMPENSATION, pF POWER DERATING 16 PHASE, Ф (°) INTERNAL POWER DISSIPATION, P(W) Product Innovation From 10 GAIN 100 POWER RESPONSE .75pF 6.8pF 15pF 33pF 100 10 10K 68pF 100K FREQUENCY, F (Hz) 1M QUIESCENT CURRENT 120 115 110 105 100 95 °C) I Q (85 °C) I Q (25 ) IQ (-25°C 90 85 80 100 150 200 250 300 350 TOTAL SUPPLY VOLTAGE, (V) POWER SUPPLY REJECTION 90 NEGATIVE 80 70 POSITIVE 60 50 40 10 100 1K 10K FREQUENCY, F (Hz) 100K 3 Product Innovation From GENERAL Please read Application Note 1 "General Operating Considerations" which covers stability, power supplies, heat sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www.Cirrus.com for design tools that help automate tasks such as calculations for stability, internal power dissipation, current limit, heat sink selection, Apex Precision Power's complete Application Notes library, Technical Seminar Workbook and Evaluation Kits. PHASE COMPENSATION Open loop gain and phase shift both increase with increasing temperature. The PHASE COMPENSATION typical graph shows closed loop gain and phase compensation capacitor value relationships for four case temperatures. The curves are based on achieving a phase margin of 50°. Calculate the highest case temperature for the application (maximum ambient temperature and highest internal power dissipation) before choosing the compensation. Keep in mind that when working with small values of compensation, parasitics may play a large role in performance of the finished circuit. The compensation capacitor must be rated for at least the total voltage applied to the amplifier and should be a temperature stable type such as NPO or COG. OTHER STABILITY CONCERNS There are two important concepts about closed loop gain when choosing compensation. They stem from the fact that while "gain" is the most commonly used term, β (the feedback factor) is really what counts when designing for stability. 1. Gain must be calculated as a non-inverting circuit (equal input and feedback resistors can provide a signal gain of -1, but for calculating offset errors, noise, and stability, this is a gain of 2). 2. Including a feedback capacitor changes the feedback factor or gain of the circuit. Consider Rin=4.7k, Rf=47k for a gain of 11. Compensation of 4.7 to 6.8pF would be reasonable. Adding 33pF parallel to the 47k rolls off the circuit at 103kHz, and at 2MHz has reduced gain from 11 to roughly 1.5 and the circuit is likely to oscillate. As a general rule the DC summing junction impedance (parallel combination of the feedback resistor and all input resistors) should be limited to 5k ohms or less. The amplifier input capacitance of about 6pF, plus capacitance of connecting traces or wires and (if used) a socket will cause undesirable circuit performance and even oscillation if these resistances are too high. In circuits requiring high resistances, measure or estimate the total sum point capacitance, multiply by Rin/Rf, and parallel Rf with this value. Capacitors included for this purpose are usually in the single digit pF range. This technique results in equal feedback factor calculations for AC and DC cases. It does not produce a roll off, but merely keeps β constant over a wide frequency range. Paragraph 6 of Application Note 19 details suitable stability tests for the finished circuit. 4 SAFE OPERATING AREA The MOSFET output stage of the PA240 is not limited by second breakdown considerations as in bipolar output stages. However there are still three distinct limitations: 1. Voltage withstand capability of the transistors. 2. Current handling capability of the die metallization. 3. Temperature of the output MOSFETS. OUTPUT CURRENT FROM +VS OR –VS, (A) PA240 SOA 1.0 0.5 0.3 0.2 200mS 300mS 0.1 0.05 0.03 0.02 0.01 DC, T C = 25°C DC, T C = 85°C 0.005 0.003 0.002 0.001 10 20 30 50 100 200 300 500 1K SUPPLY TO OUTPUT DIFFERENTIAL, V S - V O, (V) These limitations can be seen in the SOA (see Safe Operating Area graphs). Note that each pulse capability line shows a constant power level (unlike second breakdown limitations where power varies with voltage stress). These lines are shown for a case temperature of 25°C. Pulse stress levels for other case temperatures can be calculated in the same manner as DC power levels at different temperatures. The output stage is protected against transient flyback by the parasitic diodes of the output stage MOSFET structure. However, for protection against sustained high energy flyback external fast-recovery diodes must be used. HEATSINKING The PA240CC 7-pin DDPAK surface mountable package has a large exposed integrated copper heatslug to which the monolithic amplifier is directly attached. The PA240CC requires surface mount techniques of heatsinking. A solder connection to a copper foil area as defined in Note 5 of Page 2 is recommended for circuit board layouts. This may be adequate heatsinking but the large number of variables suggests temperature measurements to be made on the top of the package. Do not allow the temperature to exceed 85°C. PA240U PA240 Product Innovation From +Vs +Vs -IN Q1 +IN Z1 OUT Q2 -Vs -Vs Z2 FIGURE 1 OVERVOLTAGE PROTECTION Although the PA240 can withstand differential input voltages up to 16V, in some applications additional external protection may be needed. Differential inputs exceeding 16V will be clipped by the protection circuitry. However, if more than a few milliamps of current is available from the overload source, the protection circuitry could be destroyed. For differential sources above 16V, adding series resistance limiting input current to 1mA will prevent damage.Alternatively, 1N4148 signal diodes connected anti-parallel across the input pins is usually sufficient. In more demanding applications where bias current is important, diode connected JFETs such as 2N4416 will be required. See Q1 and Q2 in Figure 1. In either case the differential input voltage will be clamped to 0.7V. This is sufficient overdrive to produce the maximum power bandwidth. In the case of inverting circuits where the +IN pin is grounded, the diodes mentioned above will also afford protection from excessive common mode voltage. In the case of non-inverting circuits, clamp diodes from each input to each supply will provide protection. Note that these diodes will have substantial reverse bias voltage under normal operation and diode leakage will produce errors. Some applications will also need over-voltage protection devices connected to the power supply rails. Unidirectional zener diode transient suppressors are recommended. The zeners clamp transients to voltages within the power supply rating and also clamp power supply reversals to ground. Whether the zeners are used or not the system power supply should be evaluated for transient performance including poweron overshoot and power-off polarity reversals as well as line regulation. See Z1 and Z2 in Figure 1. APPLICATION REFERENCES: For additional technical information please refer to the following Application Notes: AN01: General Operating Considerations AN03: Bridge Circuit Drives AN25: Driving Capacitive Loads AN38: Loop Stability with Reactive Loads CONTACTING CIRRUS LOGIC SUPPORT For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact apex.support@cirrus.com. International customers can also request support by contacting their local Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). 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