PA83

PA83 • PA83A High Voltage Power Operational Amplifiers RoHS COMPLIANT FEATURES • • • Low Bias Current, Low Noise — FET Input Fully Protected Input — Up to ±150V Wide Supply Range — ±15V to ±150V APPLICATIONS • • • • High Voltage Instrumentation Electrostatic Transducers & Deflection Programmable Power Supplies up to 290V Analog Simulators DESCRIPTION The PA83 is a high voltage operational amplifier designed for output voltage swings up to ±145V with a dual (±) supply or 290V with a single supply. Its input stage is protected against transient and steady state overvoltages up to and including the supply rails. High accuracy is achieved with a cascode input circuit con‐ figuration. All internal biasing is referenced to a zener diode fed by a FET constant current source. As a result, the PA83 features an unprecedented supply range and excellent supply rejection. The output stage is biased in the class A/B mode for linear operation. Internal phase compensation assures stability at all gain settings without need for external components. Fixed current limits protect these amplifiers against shorts to com‐ mon at supply voltages up to 120V. For operation into inductive loads, two external flyback pulse protection diodes are recommended. However, a heatsink may be necessary to maintain the proper case temperature under normal operating conditions. This hybrid circuit utilizes beryllia (BeO) substrates, thick (cermet) film resistors, ceramic capacitors and silicon semiconductor chips to maximize reliability, minimize size and give top performance. Ultrasonically bonded aluminum wires provide reliable interconnections at all operating temperatures. The 8‐pin TO‐3 package is hermetically sealed and electrically isolated. The use of compressible thermal isolation washers and/or improper mounting torque voids product warranty. Please see Application Note 1 “General Operating Considerations.” Figure 1: Equivalent Schematic 4 2 C1 D1 3 Q3 Q2 Q1 Q4 Q5 C3 C2 Q8 C5 C4 Q9 Q10 Q12B Q6 Q7 Q11 1 Q12A 5 Q13 Q14 Q16 Q15 6 C6 Q17 D2 7 www.apexanalog.com © Apex Microtechnology Inc. All rights reserved Dec 2015 PA83U Rev Y PA83 • PA83A TYPICAL CONNECTION Figure 2: Typical Connection 2 PA83U Rev Y PA83 • PA83A PINOUT AND DESCRIPTION TABLE Figure 3: External Connections Pin Number Name Description 1 OUT The output. Connect this pin to load and to the feedback resistors. 2 +Vs The positive supply rail. 3 BAL Balance Control pin. Adjusts voltage offset. See applicable section. 4 BAL Balance Control pin. Adjusts voltage offset. See applicable section. 5 ‐IN The inverting input. 6 +IN The non‐inverting input. 7 ‐Vs The negative supply rail. 8 NC No connection. PA83U Rev Y 3 PA83 • PA83A SPECIFICATIONS The power supply voltage for all tests is the TYP rating, unless otherwise noted as a test condition. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min +Vs to ‐Vs Supply Voltage, total Max Units 300 V Output Current, within SOA IO Power Dissipation, continuous @ Tc = 25°C 1 PD 17.5 W VIN (Diff) ±300 V Vcm ±300 V 350 °C 175 °C ‐65 +150 °C ‐55 +125 °C Input Voltage, differential Input Voltage, common mode Internally Limited Temperature, pin solder, 10s max. TJ Temperature, junction Temperature Range, storage TC Operating Temperature Range, case 1. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dis‐ sipation to achieve high MTTF. CAUTION The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or subject to temperatures in excess of 850°C to avoid generating toxic fumes. INPUT Parameter Test Conditions PA83 Min PA83A Typ Max ±1.5 ±3 ±25 Min Units Typ Max ±0.5 ±1 mV ±5 ±10 µV/°C Offset Voltage, initial TC = 25°C Offset Voltage vs. Temperature Full temp range ±10 Offset Voltage vs. Supply TC = 25°C ±0.5 ±0.2 µV/V Offset Voltage vs. Time TC = 25°C ±75 * µV/√kh TC = 25°C 5 Bias Current vs. Supply TC = 25°C .01 Offset Current, initial 1 TC = 25°C ±2.5 Offset Current vs. Supply TC = 25°C ±.01 * pA/V Input Impedance, DC TC = 25°C 1011 * Ω Input Capacitance Full temp range 6 * pF Common Mode Voltage Range 2 Full temp range Common Mode Rejection, DC Full temp range Bias Current, initial 1 ±VS–10 50 3 10 * ±50 ±1.5 pA/V ±10 * 130 pA pA V * dB 1. Doubles for every 10°C of temperature increase. 2. +VS and –VS denote the positive and negative supply rail respectively. Total VS is measured from +VS to –VS. 4 PA83U Rev Y PA83 • PA83A GAIN Parameter Test Conditions PA83 Min Typ 96 PA83A Max Max Units Min Typ 116 * * dB Open Loop @ 10 Hz TC = 25°C, RL = 2 kΩ Unity Gain Crossover Frequency TC = 25°C, RL = 2 kΩ 5 3 * MHz Power Bandwidth TC = 25°C, RL = 10 kΩ 60 40 * kHz Phase Margin Full temp range 60 * ° Test Conditions PA83 PA83A OUTPUT Parameter Min Typ Max Min Typ Max Units Voltage Swing 1, full load Full temp range, ±VS–10 ±VS–5 IO = 75mA * * V Voltage Swing 1 Full temp range, IO = 15mA * * V Current, peak TC = 25°C Current, short circuit TC = 25°C Slew Rate 2 TC = 25°C, RL = 2 kΩ ±VS–5 ±VS–3 75 * 100 20 30 * mA * mA * V/µs Capacitive Load, unity gain Full temp range 10 * nF Capacitive Load, gain > 4 Full temp range SOA * µF Settling Time to 0.1% TC = 25°C, RL = 2 kΩ, 10V step 12 * µs 1. +VS and –VS denote the positive and negative supply rail respectively. Total VS is measured from +VS to –VS. 2. Signal slew rates at pins 5 and 6 must be limited to less than 1V/ns to avoid damage. When faster waveforms are unavoid‐ able, resistors in series with those pins, limiting current to 150mA will protect the amplifier from damage. POWER SUPPLY PA83 PA83A Test Conditions Min Typ Max Min Typ Max Voltage TC= ‐55 to 125°C ±15 ±150 ±150 * * * V Current, quiescent TC = 25°C 6 8.5 * * mA Parameter PA83U Rev Y Units 5 PA83 • PA83A THERMAL Parameter Test Conditions PA83 Min Typ Resistance, AC, junction to case 1 F > 60 Hz 4.26 Resistance, DC, junction to case F < 60 Hz 6.22 Resistance, case to air Temperature Range, case PA83A Max Min ‐25 Max * 8.57 * 30 Meets full range specs Typ °C/W * * +85 * Units °C/W °C/W * °C 1. Rating applies if the output current alternates between both output transistors at a rate faster than 60 Hz. Note: * The specification of PA83A is identical to the specification for PA83 in applicable column to the left. 6 PA83U Rev Y PA83 • PA83A TYPICAL PERFORMANCE GRAPHS Figure 4: Power Derating Figure 5: Current Limit 250 17.5 200 15 Current Limit, ILIM (A) /ŶƚĞƌŶĂůWŽǁĞƌŝƐƐŝƉĂƟŽŶ͕WD (W) 20 12.5 10 7.5 5 150 100 50 2.5 0 0 25 50 75 100 125 0 –55 150 –25 0 25 50 75 Case Temperature, TC (°C) Temperature, T (°C) Figure 6: Small Signal Response Figure 7: Phase Response 120 0 RLсϮŬɏ 100 –30 80 –60 Phase, ɭ (°) Open Loop Gain, AOL (dB) RLсϮŬɏ 60 40 –90 –120 20 –150 0 –180 –20 1 10 100 1k 10k 100k 1M 10M Frequency, F (Hz) PA83U Rev Y 100 125 –210 1 10 100 1k 10k .1M 1M 10M Frequency, F (Hz) 7 PA83 • PA83A Figure 8: Output Voltage Swing Figure 9: Power Response 300 | +VS | + | –VS | = 300V 200 7 Output Voltage, VO (VP-P) Voltage From Supply, VS-VO (V) 8 C 6 = TC °C ° 25 5 5 = –2 TC 4 = TC C 5° 8 RLсϮŬɏ 100 60 30 | +VS | + | –VS | = 100V 3 2 0 20 40 60 80 100 15 50k 120 .1M Output Current, IO (mA) .2M .3M Frequency, F (Hz) Figure 10: Pulse Response Figure 11: Slew Rate vs. Supply 6 1.6 RLсϮŬɏ RLсϮŬɏ Normalized Slew Rate (X) Output Voltage, VO (VP) 4 2 0 –2 –4 –6 –0.5 VIN = ±5V, tr =100ns 0 0.5 1 1.5 Time, t (μs) 8 .5M .7M 1M 2.0 2.5 3.0 1.4 1.2 1.0 0.8 0.6 0.4 30 50 100 150 200 250 300 Total Supply Voltage, VS (V) PA83U Rev Y PA83 • PA83A Figure 12: Input Noise Figure 13: Common Mode Rejection 140 ŽŵŵŽŶDŽĚĞZĞũĞĐƟŽŶ͕DZ;ĚͿ INput Noise Voltage, VN (nV/яHz) 20 15 10 6 4 2 10 100 10k 1k 120 100 80 60 40 20 0 1 .1M 10 10k 1k .1M 1M Frequency, F (Hz) Frequency, F (Hz) Figure 14: Power Supply Rejection Figure 15: Common Mode Voltage 140 300 120 200 | +VS | + | –VS | = 300V 100 100 80 +VS 60 40 –VS ѐVout(mV) WŽǁĞƌ^ƵƉƉůLJZĞũĞĐƟŽŶ͕W^Z;ĚͿ 100 60 30 | +VS | + | –VS | = 100V 20 0 1 10 100 1k 10k Frequency, F (Hz) PA83U Rev Y .1M 1M 15 10k 20k 50k .1M .2M .5M 1M Temperature (°C) 9 PA83 • PA83A SAFE OPERATING AREA (SOA) The bipolar output stage of this high voltage amplifier has two distinct limitations. 1. The internal current limit, which limits maximum available output current. 2. The second breakdown effect, which occurs whenever the simultaneous collector current and collector‐ emitter voltage exceed specified limits. The SOA curves combine the effect of these limits. For a given application, the direction and magnitude of the output current should be calculated or measured and checked against the SOA curves. This is simple for resistive loads but more complex for reactive and EMF generating loads. However, the following guidelines may save extensive analytical efforts: 1. The following capacitive and inductive loads are safe: ±VS C(MAX) L(MAX) 150V 0.7 F 1.5 H 125V 2.0µF 2.5 H 100V 5.0µF 6.0 H 75V 60µF 30 H 50V ALL ALL 2. Short circuits to ground are safe with dual supplies up to 120V or single supplies up to 120V. 3. Short circuits to the supply rails are safe with total supply voltages up to 120V, e.g. ±60V. 4. The output stage is protected against transient flyback. However, for protection against sustained, high energy flyback, external fast‐recovery diodes should be used. Figure 16: SOA 150 100 /EdZE>hZZEd>/D/d ƚс 200 250 ϭ  Ɛ ƚс Z ŵ ƚĞ  ϱ ƚĂ  с  ƚ LJƐ ĂĚ ƐƚĞ Ɛ E ŵ t ͘ϱ Ϭ ŵƐ