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PA93

PA93

  • 厂商:

    APEX

  • 封装:

    SIP12

  • 描述:

    IC OPAMP POWER 1 CIRCUIT 12SIP

  • 数据手册
  • 价格&库存
PA93 数据手册
PA93 High Voltage Power Operational Amplifiers RoHS COMPLIANT FEATURES • • • • High Voltage — 400V (±200V) Low Quiescent Current — 10mA High Output Current — 8A Programmable Current Limit APPLICATIONS • • • • Piezoelectric Positioning High Voltage Instrumentation Electrostatic Transducers Programmable Power Supplies up to 390V DESCRIPTION The PA93 is a high voltage, low quiescent current MOSFET operational amplifier designed as a low cost solution for driving continuous output currents up to 8A and pulse currents up to 14A. The safe operating area (SOA) has no second breakdown limitations and can be observed for all type loads by choosing an appropriate current limiting resistor. The MOSFET output stage is biased AB for linear operation. External compensation provides flexibility in choosing bandwidth and slew rate for the application. Apex Microtechnology’s Power SIP uses a minimum of board space allowing for high density circuit boards. The Power SIP is electrically isolated. Figure 1: Equivalent Schematic +VS R1A C1 R1B Q1 R3 Q3 Q2 R4 Q4 Q6 CC2 Q5 Q14A CC1 Q14B R8 R9 Q12 OUT Q13 R15 +IN Q15 www.apexanalog.com R7 Q11 R6 –IN R5 –VS ICL Q8 R11 Q18 Q16 R12 © Apex Microtechnology Inc. All rights reserved Sep 2020 PA93U Rev V PA93 TYPICAL CONNECTIONS Figure 2: Typical Connections RF 100k +V S * 100nF RC CC RF +V S + 1k CC1 PA93 V OUT CC2 CL -V S RCL RL -V S * Use 10μF per Amp of Output Current. 100nF * ** 2 * * Connect in one point PA93U Rev V PA93 PINOUT AND DESCRIPTION TABLE Figure 3: External Connections Pin Number Name Description 1 2 -IN +IN 3 IQ 4 CC1 The inverting input. The non-inverting input. Quiescent current reduction pin. Connect to pin 5 to disable the AB bias. See applicable section Compensation Resistor connection, select value based on Phase Compensation. See applicable section 5 CC2 6 7, 8 OUT -VS 9, 10 CL 11, 12 +VS PA93U Rev V Compensation Capacitive connection, select value based on Phase Compensation. See applicable section The output. Connect this pin to load and to the feedback resistors. The negative supply rail. Pins 7 and 8 are internally connected. Connect to the current limit resistor. Output current flows into/out of these pins through RCL. The output pin and the load are connected to the other side of RCL. Pins 9 and 10 are internally connected. The positive supply rail. Pins 11 and 12 are internally connected. 3 PA93 SPECIFICATIONS Unless otherwise noted: TC = 25°C, DC input specifications are ± value given. Power supply voltage is typical rating. RC = 100 CC = 220pF. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Supply Voltage, total Output Current, source, sink, peak, within SOA Power Dissipation, continuous @ Tc = 25°C Input Voltage, differential Input Voltage, common mode Min Max Units +Vs to -Vs 400 V IOUT 14 A PD 125 W VIN (Diff) -20 +20 V VCM -VS +VS V +260 °C +150 °C -55 +125 °C -40 +85 °C Temperature, pin solder, 10s max. Temperature, junction Temperature Range, storage TJ Operating Temperature Range, case TC 1 1. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to achieve high MTTF. CAUTION The PA93 is constructed from MOSFET transistors. ESD handling procedures must be observed. The substrate contains beryllia (BeO). Do not crush, machine, or subject to temperatures in excess of 850°C to avoid generating toxic fumes. INPUT Parameter Test Conditions Offset Voltage, initial Offset Voltage vs. Temperature Offset Voltage vs. Supply Offset Voltage vs. Time Bias Current, initial Bias Current vs. Supply Offset Current, initial Min Full temp range Input Impedance, DC Input Capacitance Common Mode Voltage Range 1 Typ Max Units 2 15 10 75 200 4 50 10 50 25 mV µV/°C µV/V µV/kh pA pA/V pA VCM = ±90V Noise 100 kHz BW, RS = 1 kΩ, CC = 10pF 80 500 1011 Ω 4 pF V ±Vs ∓15 Common Mode Rejection, DC 2000 98 dB 1 µV RMS 1. +VS and –VS denote the positive and negative power supply rail respectively. 4 PA93U Rev V PA93 GAIN Parameter Min Typ 94 111 dB Gain Bandwidth Product @ 1 MHz RL = 2 kΩ, CC = 10pF 12 MHz Power Bandwidth RL = 2 kΩ, CC = 10pF 30 kHz Phase Margin Full temp range 60 ° Open Loop @ 15 Hz Test Conditions RL = 2 kΩ, CC = 10pF Max Units OUTPUT Parameter Test Conditions IOUT = 8A Voltage Swing 1 Current, continuous Slew Rate, AV = 100 CC = 10pF Capacitive Load, AV = +1 Full temp range Settling Time to 0.1% CC = 10pF, 2V step Min Typ ±VS ∓12 ±VS ∓10 Max V 8 A 50 V/µs 1 Resistance, no load Units nF 1 µs 10 Ω 1. +VS and –VS denote the positive and negative power supply rail respectively. POWER SUPPLY Parameter Test Conditions Min Typ Max Units ±40 ±150 ±200 V 10 14 mA Max Units Full temp range, F > 60 Hz 0.7 °C/W Full temp range, F < 60 Hz Full temp range Meets full range specifications 1 °C/W °C/W +85 °C Voltage1 Current, quiescent 1. Derate max supply rating 0.625 V/°C below 25°C case. No derating needed above 25°C case. THERMAL Parameter Resistance, AC, junction to case1 Resistance, DC, junction to case Resistance, junction to air Temperature Range, case Test Conditions Min Typ 30 -25 1. Rating applies if the output current alternates between both output transistors at a rate faster than 60 Hz. PA93U Rev V 5 PA93 TYPICAL PERFORMANCE GRAPHS Figure 4: Power Derating Figure 5: Normalized Quiescent Current 1.8 Normalized Quiescent Current, IQ(X) /ŶƚĞƌŶĂůWŽǁĞƌŝƐƐŝƉĂƟŽŶ͕W;tͿ 125 100 75 50 25 25 50 75 100 1.4 1.2 1.0 25 0 0 1.6 125 50 Case Temperature, TC (°C) 90 CC = 220pF CC = 100pF CC = 47pF CC = 10pF 40 30 135 Phase, ˇ(°) Open loop Gain, A (dB) 125 Figure 7: Phase Response 50 20 10 180 225 0 1M Frequency F (Hz) 6 100 Case Temperature, TC (°C) Figure 6: Small Signal Response -10 100k 75 10M 270 100k CC = 220pF CC = 100pF CC = 47pF CC = 10pF 1M 10M Frequency F (Hz) PA93U Rev V PA93 Figure 8: Output Voltage Swing Figure 9: Power Response 400 Output Voltage, VOUT (VP-P) Voltage Drop from Supply, VS – VOUT (V) 9 8 7 6 100 CC = 10pF CC = 47pF CC = 100pF CC = 220pF 10 5 0 2 4 6 8 1k 10k Output Current, IOUT (A) 1M Frequency (Hz) Figure 10: Slew Rate Figure 11: Harmonic Distortion 60 0.1 PO = 1W PO = 20W PO = 62W 40 30 ŝƐƚŽƌƟŽŶ;й) 20 Slew Rate ;sͬʅƐ) 100k 10 8 6 4 3 0.01 2 1 10 0.001 20 30 40 60 100 200 300 džƚ͘ŽŵƉĞŶƐĂƟŽŶĂƉĂĐŝƚŽƌ͕CC (pF) PA93U Rev V 100 1k 10k Frequency, F (Hz) 7 PA93 Figure 12: Input Noise Voltage Figure 13: Current Limit 8 15 Current Limit, ICL(AͿ Input Noise Voltage, VN;Ŷsя,njͿ 20 10 7 5 4 2 3 2 10 0 100 1k Frequency, F (Hz) 8 6 10k 100k 0 0.1 0.2 0.3 0.4 0.5 0.6 Resistor Value, RCL ;ɏͿ PA93U Rev V PA93 SAFE OPERATING AREA (SOA) The safe operating area curves define the maximum additional internal power dissipation the amplifier can tolerate when it produces the necessary output to drive an external load. The MOSFET output stage of this power operational amplifier has two distinct limitations: 1. The current handling capability of the MOSFET geometry and the wire bonds. 2. The junction temperature of the output MOSFETs. Note: The output stage is protected against transient flyback. However, for protection against sustained, high energy flyback, external fast-recovery diodes should be used. Figure 14: SOA 20 S KƵƚƉƵƚƵƌƌĞŶƚĨƌŽŵнs KZʹs ͕;Ϳ ͕dC = 25°C 10 8 6 ϮϬϬŵƐ S 4 3 ϭϬ Ϭŵ 2  ͕d 1 0.8 0.6 C  ͕d C Ɛ =8 5°C =1 25 °C 0.4 0.3 0.2 0.1 0.08 0.06 10 20 30 40 60 80 100 200 300 ^ƵƉƉůLJƚŽKƵƚƉƵƚŝīĞƌĞŶƟĂů͕s ʹs S PA93U Rev V OUT 500 ;sͿ 9 PA93 GENERAL Please read Application Note 1 “General Operating Considerations” which covers stability, supplies, heat sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www.apexanalog.com for Apex Microtechnology’s complete Application Notes library, Technical Seminar Workbook, and Evaluation Kits. TYPICAL APPLICATION LOW POWER, PIEZOELECTRIC POSITIONING Piezo positioning may be applied to the focusing of segmented mirror systems. The composite mirror may be composed of hundreds of elements, each requiring focusing under computer control. In such complex systems the PA93 reduces the costs of power supplies and cooling with its advantages of low cost and low quiescent power consumption while increasing circuit density with the SIP package. Figure 15: Typical Application PHASE COMPENSATION Gain CC* RC ≥1 ≥2 ≥4 ≥17 220pF 100pF 47pF 10pF 100 Ω 100 Ω 0Ω 0Ω *CC Never to be

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