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PB50

PB50

  • 厂商:

    APEX

  • 封装:

    TO3-8

  • 描述:

    IC OPAMP POWER 1 CIRCUIT TO3-8

  • 数据手册
  • 价格&库存
PB50 数据手册
PB50 Power Booster Amplifier RoHS COMPLIANT FEATURES • • • • • • • Wide Supply Range — ±30V to ±100V High Output Current — Up to 2A Continuous Voltage and Current Gain High Slew Rate —50V/µs Minimum Programmable Output Current Limit High Power Bandwidth — 160 kHz Minimum Low Quiescent Current — 12mA Typical APPLICATIONS • • • High Voltage Instrumentation Electrostatic Transducers & Deflection Programmable Power Supplies up to 180VP-P DESCRIPTION The PB50 is a high voltage, high current amplifier designed to provide voltage and current gain for a small signal, general purpose op amp. Including the power booster within the feedback loop of the driver amplifier results in a composite amplifier with the accuracy of the driver and the extended output voltage range and current capability of the booster. The PB50 can also be used without a driver in some applications, requiring only an external current limit resistor to function properly. The output stage utilizes complementary MOSFETs, providing symmetrical output impedance and eliminating secondary breakdown limitations imposed by Bipolar Junction Transistors. Internal feedback and gainset resistors are provided for a pin-strappable gain of 3. Additional gain can be achieved with a single external resistor. Compensation is not required for most driver/gain configurations, but can be accomplished with a single external capacitor. Although the booster can be configured quite simply, enormous flexibility is provided through the choice of driver amplifier, current limit, supply voltage, voltage gain, and compensation. This hybrid circuit utilizes a beryllia (BeO) substrate, thick film resistors, ceramic capacitors and semiconductor chips to maximize reliability, minimize size and give top performance. Ultrasonically bonded aluminum wires provide reliable interconnections at all operating temperatures. The 8-pin TO-3 package is electrically isolated and hermetically sealed using one-shot resistance welding. The use of compressible isolation washers voids the warranty. www.apexanalog.com © Apex Microtechnology Inc. All rights reserved Aug 2015 PB50U Rev N PB50 TYPICAL CONNECTIONS Figure 1: Typical Connections 2 PB50U Rev N PB50 PINOUT AND DESCRIPTION TABLE Figure 2: External Connections Pin Number Name 1 OUT The output. Connect this pin to load and to the feedback resistors. 2 CL Connect to the current limit resistor. Output current flows into/out of this pin through RCL. The output pin and the load are connected to the other side of RCL. 3 +Vs The positive supply rail. 4 IN The input. 5 GND Ground. Connect to same ground as referenced by input amplifier. 6 -Vs The negative supply rail. 7 GAIN Gain resistor pin. Connect RGAIN between GAIN and OUT. This will specify the gain for the power booster itself, not the composite amplifier. See applicable section. 8 CC Compensation capacitor connection. Select value based on Phase Compensation. See applicable section. PB50U Rev N Description 3 PB50 SPECIFICATIONS The power supply voltage specified under typical (TYP) applies, TC = 25°C unless otherwise noted. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Supply Voltage, total Output Current, within SOA Power Dissipation, internal @ Tc = 25°C1 Max Units +Vs to -Vs 200 V IO 2 A PD 35 W +15 V 350 °C 150 °C -65 +150 °C -55 +125 °C Vcm Input Voltage, referred to common Min -15 Temperature, pin solder, 10s max. Temperature, junction 1 TJ Temperature, storage TC Operating Temperature Range, case 1. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to achieve high MTTF (Mean Time to Failure). CAUTION The PB50 is constructed from MOSFET transistors. ESD handling procedures must be observed. The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or subject to temperatures in excess of 850°C to avoid generating toxic fumes. INPUT Parameter Test Conditions Min Offset Voltage, initial Offset Voltage vs. temperature Full temp range Input Impedance, DC 25 Input Capacitance Closed Loop Gain Range 3 Typ Max Units ±.75 ±1.75 V -4.5 -7 mV/°C 50 kΩ 3 pF 10 25 V/V Gain Accuracy, internal Rg, Rf AV = 3 ±10 ±15 % Gain Accuracy, external Rf AV = 10 ±15 ±25 % F = 10 kHz, AVCL= 10, CC= 22pF 10 ° F =200 kHz, AVCL=10, CC= 22pF 60 ° Phase Shift 4 PB50U Rev N PB50 OUTPUT Parameter Test Conditions Min Typ Max Units Voltage Swing Io = 2A ±VS – 11 ±VS – 9 V Voltage Swing Io = 1A ±VS – 10 ±VS – 7 V Voltage Swing Io = 0.1A ±VS – 8 ±VS – 5 V Current, continuous 2 Slew Rate Full temp range Capacitive Load Full temp range Settling Time to 0.1% RL = 100 Ω, 2V step Power Bandwidth VC = 100Vpp Small Signal Bandwidth CC = 22pF, AV = 25, ±VS = ±100V Small Signal Bandwidth CC = 22pF, AV = 3, ±VS = ±30V 50 160 A 100 V/µs 2200 pF 2 µs 320 kHz 100 kHz 1 MHz POWER SUPPLY Parameter Min Typ Max Units ±30 2 ±60 ±100 V VS = ±30 9 12 mA VS = ±60 12 18 mA VS = ±100 17 25 mA Typ Max Units Full temp range, F > 60 Hz 1.8 2 °C/W Resistance, DC junction to case Full temp range, F < 60 Hz 3.2 3.5 °C/W Resistance, junction to air Full temp range 30 Temperature Range, case Meets full range specifications Voltage, ±VS 1 Current, quiescent Test Conditions Full temp range 1. +VS and –VS denote the positive and negative supply rail respectively. 2. +VS must be at least 15V above COM, –VS must be at least 30V below COM. THERMAL Parameter Resistance, AC junction to case 1 Test Conditions Min -25 25 °C/W 85 °C 1. Rating applies if the output current alternates between both output transistors at a rate faster than 60 Hz. PB50U Rev N 5 PB50 TYPICAL PERFORMANCE GRAPHS Figure 3: Power Derating Figure 4: Current Limit 2 RC с L Ϭ͘ϯϯɏ 30 Current Limit, ILIM (A) 20 10 0 -25 0 25 50 75 100 1.5 RCLсϬ͘Ϯϳɏ RC с Ϭ͘ϲ L 1 ϴɏ RCL сϭ͘ϱɏ 0.5 0 -25 125 0 Case Temperature, TC (°C) 75 100 125 Figure 6: Small Signal Response (Open Loop Gain and Phase) Open Loop Gain, A (dB) 10 Voltage Drop From Supply, VS - VO (V) 50 Case Temperature, TC (°C) Figure 5: Output Voltage Swing 8 6 VO – 4 80 0 60 -45 40 -90 Phase Gain 20 -135 VO + 2 0.01 0.02 0.1 0.2 Output Current, IO (A) 6 25 Open Loop Phase, ˇ;ΣͿ /ŶƚĞƌŶĂůWŽǁĞƌŝƐƐŝƉĂƟŽŶ͕W;t) 40 1 2 0 100 1k 10k 100k 1M -180 10M Frequency, F (Hz) PB50U Rev N PB50 Figure 7: Small Signal Response (Closed Loop Gain) Figure 8: Small Signal Response (Closed Loop Phase) 30 0 AVCL = 3 Closed Loop Phase, ˇ;ΣͿ Closed Loop Gain, A (dB) AVCL = 25 20 AVCL = 10 10 AVCL = 3 0 -45 AVCL = 10 AVCL = 25 -90 -135 CC = 22pF -10 1k 10k CC = 22pF 1M 100k -180 1k 10M 10k Frequency, F (Hz) Figure 10: Input Offset Voltage 0.5 Vs = ±100V /ŶƉƵƚKīƐĞƚsŽůƚĂŐĞ͕sOS (sͿ Quiescent Current, IO (mA) 20 15 Vs = ±60V Vs = ±30V 10 5 0 25 50 75 100 Case Temperature, TC (°C) PB50U Rev N 10M Frequency, F (Hz) Figure 9: Quiescent Current 0 -25 1M 100k 125 0 dDW͘ -0.5 -1 -1.5 -25 ^hWW>z 0 25 50 75 100 125 ĂƐĞdĞŵƉĞƌĂƚƵƌĞ͕dC (°Ϳ 7 PB50 Figure 11: Slew Rate vs. Temperature Figure 12: Power Response 400 360 +SLEW VQ (V), P-P Slew Rate, SR (V/μs) 180 300 200 90 45 –SLEW 100 22 0 -25 0 25 50 75 100 11 1k 125 3k 10k Case Temperature, TC (°C) 1M 0.1 NO DRIVER VS = ±60V VO = 80VP-P ŝƐƚŽƌƟŽŶ͕d,;йͿ ŝƐƚŽƌƟŽŶ͕d,;йͿ 300k Figure 14: Harmonic Distortion 1 RLсϮϱɏ 0.1 0.03 0.01 300 RLсϭŬɏ 1k 0.03 Z/sZсd>ϬϳϬ VS = ±60V VO = 95VP-P RLсϮϱɏ 0.01 0.003 RLсϭŬɏ 3k 10k Frequency, F (Hz) 8 100k Frequency, F (Hz) Figure 13: Harmonic Distortion (No Driver) 0.3 30k 30k 0.001 300 1k 3k 10k 30k Frequency, F (Hz) PB50U Rev N PB50 SAFE OPERATING AREA (SOA) Note: The output stage is protected against transient flyback. However, for protection against sustained, high energy flyback, external fast-recovery diodes should be used. Figure 15: SOA Output Current From +VS or - VS (A) 3 2 ST E 1 ST E AD Y ST E AD Y t= ST AT E AD Y m s s s ST AT E ST AT E C 20 50 m 10 0 0m T = C T C T t= t= = 25 85 °C °C = 12 5 °C 0.1 10 20 30 40 50 100 200 300 ^ƵƉƉůLJƚŽKƵƚƉƵƚŝīĞƌĞŶƟĂů sŽůƚĂŐĞVS - VO (V) PB50U Rev N 9 PB50 GENERAL Please read Application Note 1 “General Operating Considerations” which covers stability, supplies, heat sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www.apexanalog.com for Apex Microtechnology’s complete Application Notes library, Technical Seminar Workbook, and Evaluation Kits. TYPICAL APPLICATIONS Figure 16: Typical Applications CURRENT LIMIT For proper operation, the current limit resistor (RCL) must be connected as shown in the typical connection diagram. The minimum value is 0.27Ω with a maximum practical value of 47Ω. For optimum reliability the resistor value should be set as high as possible. The value is calculated as follows: +IL= 0.65V I CL = -------------- + 0.01A R CL 0.65V – I CL = -------------R CL COMPOSITE AMPLIFIER CONSIDERATIONS Cascading two amplifiers within a feedback loop has many advantages, but also requires careful consideration of several amplifier and system parameters. The most important of these are gain, stability, slew rate, and output swing of the driver. Operating the booster amplifier in higher gains results in a higher slew rate and lower output swing requirement for the driver, but makes stability more difficult to achieve. 10 PB50U Rev N PB50 GAIN SET R G =   Av – 1   3.1k  – 6.2k R G + 6.2k Av = ------------------------ + 1 3.1k The booster’s closed-loop gain is given by the equation above. The composite amplifier’s closed loop gain is determined by the feedback network, that is: –Rf/Ri (inverting) or 1+Rf/Ri (non-inverting). The driver amplifier’s “effective gain” is equal to the composite gain divided by the booster gain. Example: Inverting configuration (figure 1) with R i = 2 k, R f = 60 k, R gain = 0: Av (booster) = (6.2 k/3.1 k) + 1 = 3 Av (composite) = 60 k /2 k = - 30 Av (driver) = - 30/3 = -10 STABILITY 1. 2. 3. 4. Stability can be maximized by observing the following guidelines: Operate the booster in the lowest practical gain. Operate the driver amplifier in the highest practical effective gain. Keep gain-bandwidth product of the driver lower than the closed loop bandwidth of the booster. Minimize phase shift within the loop. A good compromise for (1) and (2) is to set booster gain from 3 to 10 with total (composite) gain at least a factor of 3 times booster gain. Guideline (3) implies compensating the driver as required in low composite gain configurations. Phase shift within the loop (4) is minimized through use of booster and loop compensation capacitors Cc and Cf when required. Typical values are 5pF to 33pF. Stability is the most difficult to achieve in a configuration where driver effective gain is unity (ie; total gain = booster gain). For this situation, Table 1 gives compensation values for optimum square wave response with the op amp drivers listed. TABLE 1: TYPICAL VALUES FOR CASE WHERE OP AMP EFFECTIVE GAIN = 1. DRIVER CCH CF CC FPBW SR OP07 - 22p 22p 4kHz 1.5 741 - 18p 10p 20kHz 7 LF155 - 4.7p 10p 60kHz >60 LF156 - 4.7p 10p 80kHz >60 TL070 22p 15p 10p 80kHz >60 For: RF = 33 k, RI = 3.3 k, RG = 22 k PB50U Rev N 11 PB50 Figure 17: Non-inverting Composite Amplifier SLEW RATE The slew rate of the composite amplifier is equal to the slew rate of the driver times the booster gain, with a maximum value equal to the booster slew rate. OUTPUT SWING The maximum output voltage swing required from the driver op amp is equal to the maximum output swing from the booster divided by the booster gain. The Vos of the booster must also be supplied by the driver, and should be subtracted from the available swing range of the driver. Note also that effects of Vos drift and booster gain accuracy should be considered when calculating maximum available driver swing. 12 PB50U Rev N PB50 PACKAGE OPTIONS PACKAGE STYLE CE NEED TECHNICAL HELP? CONTACT APEX SUPPORT! For all Apex Microtechnology product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact apex.support@apexanalog.com. International customers can also request support by contacting their local Apex Microtechnology Sales Representative. To find the one nearest to you, go to www.apexanalog.com IMPORTANT NOTICE Apex Microtechnology, Inc. has made every effort to insure the accuracy of the content contained in this document. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (expressed or implied). Apex Microtechnology reserves the right to make changes without further notice to any specifications or products mentioned herein to improve reliability. This document is the property of Apex Microtechnology and by furnishing this information, Apex Microtechnology grants no license, expressed or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Apex Microtechnology owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Apex Microtechnology integrated circuits or other products of Apex Microtechnology. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. APEX MICROTECHNOLOGY PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN PRODUCTS USED FOR LIFE SUPPORT, AUTOMOTIVE SAFETY, SECURITY DEVICES, OR OTHER CRITICAL APPLICATIONS. PRODUCTS IN SUCH APPLICATIONS ARE UNDERSTOOD TO BE FULLY AT THE CUSTOMER OR THE CUSTOMER’S RISK. Apex Microtechnology, Apex and Apex Precision Power are trademarks of Apex Microtechnology, Inc. All other corporate names noted herein may be trademarks of their respective holders. PB50U Rev N 13

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