SA303
3 Phase Switching Amplifier
RoHS
COMPLIANT
FEATURES
•
•
•
•
•
•
•
•
Low Cost 3 Phase Intelligent Switching Amplifier
Directly Connects to Most Embedded Microcontrollers and Digital
Signal Controllers
Integrated Gate Driver Logic with Dead-Time Generation and
Shoot-through Prevention
Wide Power Supply Range (8.5V To 60V)
Over 10A Peak Output Current per Phase
Independent Current Sensing for each Output
User Programmable Cycle-by-Cycle Current Limit Protection
Over-Current and Over-Temperature Warning Signals
APPLICATIONS
•
•
•
3 Phase Brushless DC motors
Multiple DC Brush Motors
3 Independent Solenoid Actuators
DESCRIPTION
The SA303 is a fully integrated switching amplifier designed primarily to drive three-phase Brushless DC
(BLDC) motors. Three independent half bridges provide over 10 amperes peak output current under microcontroller or DSC control. Thermal and short circuit monitoring is provided, which generates fault signals for
the microcontroller to take appropriate action.
Additionally, cycle-by-cycle current limit offers user programmable hardware protection independent of
the microcontroller. Output current is measured using an innovative low loss technique. The SA303 is built
using a multi-technology process allowing CMOS logic control and complementary DMOS output power
devices on the same IC. Use of P-channel high side FETs enables 60V operation without bootstrap or charge
pump circuitry.
The HSOP surface mount package balances excellent thermal performance with the advantages of a low
profile surface mount package.
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© Apex Microtechnology Inc.
All rights reserved
Mar 2019
SA303U Rev H
SA303
TYPICAL CONNECTION
Figure 1: Typical Connection
VS +
VDD
100nF
1μF
VDD
VS A
VS B/C
CL/DIS 1
DIS 2
SC
TEMP
Fault
WƌŽƚĞĐƟŽŶ
VS
OUT A
IA
IB
IC
Current
monitor
signals
VS
GND
SA303
Ab
At
PWM
Signals
100μF
OUT B
LOAD
Bt
Bb
Ct
Cb
VS
Microcontroller
or DSC
OUT C
HS
SGND
PGND A/B
PGND C
GND
2
SA303U Rev H
SA303
PINOUT AND DESCRIPTION TABLE
Figure 2: External Connections
1 NC
2 NC
,^ 44
NC 43
W'E 42
3 NC
4 NC
5 Cb
41
W'E
W'E 40
Khd 39
6 ƚ
7 /
8 SC
9 /
10 CL/DIS1
11 SGND
12 ƚ
13 Bb
14 Ab
15 ƚ
16 s
DD
17
18
19
/
DIS2
TEMP
20 NC
21 NC
22 NC
SA303U Rev H
Khd 38
s _B/C 37
S
SA303
(ŽƩŽŵsŝĞǁ͕
KƉƉŽƐŝƚĞ,ĞĂƚ
Slug)
sS_B/C 36
s _B/C 35
S
Khd 34
33
Khd
32
W'Eͬ
W'Eͬ 31
30
W'Eͬ
Khd 29
Khd 28
s _A 27
S
sS_A 26
sS_A 25
24
NC
,^ 23
3
SA303
4
Pin Number
Name
Description
5
Cb
Logic high commands C phase lower (bottom) FET to turn on.
6
Ct
Logic high commands C phase upper (top) FET to turn on.
7
IC
Phase C current sense output. Outputs a current proportional to ID of the upper
(top) FET of channel C. Connect to a sense resistor to SGND to monitor current.
8
SC
Short circuit output. When a short circuit condition is experienced on any channel,
this pin will go high for 200ns. This does not disable the outputs.
9
IB
Phase B current sense output. Outputs a current proportional to ID of the upper
(top) FET of channel B. Connect to a sense resistor to SGND to monitor current.
10
CL/DIS1
Logic high places all outputs in a high impedance state. Pulling to logic low disables
cycle-by-cycle current limit. If unconnected, cycle-by-cycle current limit will be
allowed to operate.
11
SGND
Signal ground. Reference all locic circuitry to this pin. Connect to PGND A/B and
PGND C as close to the amplifier as possible.
12
Bt
Logic high commands B phase upper (top) FET to turn on.
13
Bb
Logic high commands B phase lower (bottom) FET to turn on.
14
Ab
Logic high commands A phase lower (bottom) FET to turn on.
15
At
Logic high commands A phase upper (top) FET to turn on.
16
Vdd
Voltage supply for logic circuit. Connect 5 V supply. The ground terminal of the supply must be connected to SGND.
17
IA
Phase A current sense output. Outputs a current proportional to ID of the upper
(top) FET of channel A. Connect to a sense resistor to SGND to monitor current.
18
DIS2
Logic high places all outputs in a high impedance state. This pin may be left unconnected.
19
TEMP
This pin will go logic high when the die temperature reaches 135°C. This does not
diasble the outputs.
23, 44
HS
These pins are internally connected to the heat slug. Connect to PGND. Neither the
heatslug nor these pins should carry current.
25, 26, 27
Vs A
Voltage supply for channel A.
28, 29
OUT A
The output connection for channel A.
30, 31, 32
PGND A/B
Power ground. These pins are directly connected to the bottom FETs of channels A
and B. Connect to SGND and PGND C as close to the amplifier as possible.
33, 34
OUT B
The output connection for channel B.
35, 36, 37
Vs B/C
Voltage supply for channels B and C.
38, 39
OUT C
The output connection for channel C.
40, 41, 42
PGND C
Power ground. These pins are directly connected to the bottom FET of channel C.
Connect to SGND and PGND B/C as close to the amplifier as possible.
All Others
NC
No connection.
SA303U Rev H
SA303
PIN DESCRIPTIONS
VS: Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high
frequency characteristics is recommended) to the PGND pins. The decoupling capacitor should be located
as close to the VS and PGND pins as possible. Additional capacitance will be required at the VS pins to
handle load current peaks and potential motor regeneration. Refer to the applications section of this
datasheet for additional discussion regarding bypass capacitor selection. Note that VS (phase A) carry
only the phase A supply current. VS (phase B&C) carry supply current for phases B & C. Phase A may be
operated at a different supply voltage from phases B & C. Both VS voltages are monitored for
undervoltage conditions.
OUT A, OUT B, OUT C: These pins are the power output connections to the load. NOTE: When driving an
inductive load, it is recommended that two Schottky diodes with good switching characteristics (fast tRR
specs) be connected to each pin so that they are in parallel with the parasitic back-body diodes of the
output FETs. (See “External Flyback Diodes” Section)
PGND: Power Ground. This is the ground return connection for the output FETs. Return current from the load
flows through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See
section “Layout Considerations” of this datasheet for more details.
SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input
commands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for
approximately 200ns during switching transitions but in high current applications, short glitches may
appear on the SC pin. A high state on the SC output will not automatically disable the device. The SC pin
includes an internal 12 kΩ series resistor.
Ab, Bb, Cb: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or
lower N-channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low
turns the low side N-channel FET off. If Ab, Bb, or Cb is high at the same time that a corresponding At, Bt,
or Ct input is high, protection circuitry will turn off both FETs in order to prevent shoot-through on that
output phase. Protection circuitry also includes a dead-time generator, which inserts dead time in the
outputs in the case of simultaneous switching of the top and bottom input signals.
At, Bt, Ct: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or
upper P-channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns
the top P-channel FET off.
Ia, Ib, Ic: Current sense pins. The SA303 supplies a positive current to these pins which is proportional to the
current flowing through the top side P-channel FET for that phase. Commutating currents flowing
through the backbody diode of the P-channel FET or through external Schottky diodes are not registered
on the current sense pins. Nor do currents flowing through the low side N-channel FET, in either
direction, register at the current sense pins. A resistor connected from a current sense pin to SGND
creates a voltage signal representation of the phase current that can be monitored with ADC inputs of a
processor or external circuitry.
The current sense pins are also internally compared with the current limit threshold voltage reference,
Vth. If the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages.
Details of this functionality are described in the applications section of this datasheet.
CL/DIS1: This pin is directly connected to the disable circuitry of the SA303. Pulling this pin to logic high
places OUT A, OUT B, and OUT C in a high impedance state. This pin is also connected internally to the
output of the current limit latch through a 12 kΩ resistor and can be monitored to observe the function of
the cycle-by-cycle current limit feature. Pulling this pin to a logic low effectively disables the cycle-bycycle current limit feature.
SGND: This is the ground return connection for the VDD logic power supply pin. All internal analog and logic
SA303U Rev H
5
SA303
circuitry is referenced to this pin. PGND is internally connected to GND through a resistance of a few
ohms. However, it is highly recommended to connect the GND pin to the PGND pins externally as close
to the device as possible. Failure do to this may result in oscillations on the output pins during rising or
falling edges.
VDD: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in
the SA303. This pin requires decoupling (at least 0.1μF capacitor with good high frequency characteristics
is recommended) to the SGND pin.
DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT A, OUT B, and OUT C in a high
impedance state when pulled high. DIS2 has an internal 12 kΩ pull-down resistor and may therefore be
left unconnected.
TEMP: This logic level output goes high when the die temperature of the SA303 reaches approximately 135°C.
This pin WILL NOT automatically disable the device. The TEMP pin includes a 12 kΩ series resistor.
HS: These pins are internally connected to the thermal slug on the reverse of the package. They should be
connected to GND. Neither the heat slug nor these pins should be used to carry high current.
NC: These “no-connect” pins should be left unconnected.
6
SA303U Rev H
SA303
SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TC = 25°C. Output current rating may be limited by duty cycle, ambient temperature, and
heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Max
Units
Supply Voltage
Vs
60
V
Supply Voltage
VDD
5.5
V
(VDD+0.5)
V
IO
10
A
PD
100
W
260
°C
150
°C
-65
+125
°C
-25
+85
°C
Logic Input Voltage
(-0.5)
Output Current, peak, 10ms
1
Power Dissipation, average, 25°C 1
Temperature, solder, 10s max.
Temperature, junction
1
TJ
Temperature Range, storage
Operating Temperature Range, case
TC
1. Long term operation at elevated temperature will result in reduced product life. De-rate internal power dissipation to
achieve high MTBF.
LOGIC
Parameter
Test Conditions
Min
Typ
Input Low
Input High
Output Current (SC, Temp, CL/
DIS1)
SA303U Rev H
Units
1
V
1.8
V
Output Low
Output High
Max
0.3
3.7
V
V
50
mA
7
SA303
POWER SUPPLY
Parameter
Test Conditions
VS
Min
Typ
Max
Units
UVLO
50
60
V
VS Undervoltage Lockout, (UVLO)
8.3
VDD
4.5
V
5.5
V
Supply Current, VS
20 kHz (One phase switching
at 50% duty cycle), VS=50V,
VDD=5V
25
30
mA
Supply Current, VDD
20 kHz (One phase switching
at 50% duty cycle), VS=50V,
VDD=5.5V
5
6.5
mA
Typ
Max
Units
CURRENT LIMIT
Parameter
Test Conditions
Min
Current Limit Threshold (Vth)
3.75
V
Vth Hysteresis
100
mV
OUTPUT
Parameter
Test Conditions
Min
Typ
Max
3
Units
Current, continuous
25°C Case Temperature
Rising Delay, TD (rise)
See Figure 19
270
ns
Falling Delay, TD (fall)
See Figure 19
270
ns
Disable Delay, TD (dis)
See Figure 19
200
ns
Enable Delay, TD (dis)
See Figure 20
200
ns
Rise Time, t (rise)
See Figure 20
50
ns
50
ns
3A Load
400
mΩ
On Resistance Sinking (N-Channel) 3A Load
400
mΩ
Fall Time, t (fall)
On Resistance Sourcing (P-Channel)
A
THERMAL
Parameter
Test Conditions
Min
Typ
Max
Units
Thermal Warning
135
°C
Thermal Warning Hysteresis
40
°C
Resistance, junction to case
Full temperature range
Temperature Range, case
Meets Specs
8
1.25
-25
1.5
°C/W
+85
°C
SA303U Rev H
SA303
TYPICAL PERFORMANCE GRAPHS
Figure 3: VS Supply Current
Figure 4: VS Supply Current
25
180
20
VS Supply Currrent (mA)
VS Supply Currrent (mA)
160
125°C
15
25°C
10
5
0
10
One Phase Switching
Frequency = 20 kHz
50% Duty Cycle
20
30
40
140
120
100
80
60
40
One Phase Switching @
50% Duty Cycle; Vs = 50V
20
50
0
0
60
50
150
200
250
300
Frequency, F (kHz)
VS Supply Voltage (V)
Figure 5: Current Sense
Figure 6: VDD Supply Current
8
10
One Phase Switching
Frequency = 20 kHz
50% Duty Cycle
VDD Supply Currrent (mA)
7.5
Load Current (A)
100
1
7
6.5
6
125°C
5.5
25°C
5
4.5
0.1
0.01
0.1
1
Sense Current (mA)
SA303U Rev H
10
4
10
20
30
40
50
60
VS Supply Voltage (V)
9
SA303
Figure 7: VDD Supply Current
Figure 8: Power Derating
120
WŽǁĞƌŝƐƐŝƉĂƟŽŶ͕WD (W)
VDD Supply Currrent (mA)
5
4.9
4.8
4.7
4.6
One Phase Switching @
50% Duty Cycle; Vs = 50V
4.5
0
50
100
200
150
250
VS=13
VS=15
VS=17
VS>22
4
5
6
IOUT, (A)
10
RDS (on), (ё)
RDS (on), (ё)
VS=11
3
7
40
20
0
40
80
120
Figure 10: On Resistance - Top FET
(N-Channel)
2
60
Case Temperature, TC (°C)
Figure 9: On Resistance - Bottom FET
1
80
0
-40
300
Frequency, F (kHz)
0.8
0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0
100
8
9
10
0.8
0.75 (P-Channel)
0.7
0.65
0.6
VS=11
0.55
VS=13
0.5
0.45
VVSS=15
=15
0.4
0.35
0.3
VS>17
0.25
0.2
0.15
0 1 2 3 4 5 6 7 8 9 10
IOUT, (A)
SA303U Rev H
SA303
Figure 11: Diode Forward Voltage Bottom FET
Figure 12: Diode Forward Voltage Top FET
5
5
(P-Channel)
(N-Channel)
4
Current, (A)
Current, (A)
4
3
2
0.7
0.9
1.1
Forward Voltage, (V)
SA303U Rev H
2
1
1
0
0.5
3
1.3
1.5
0
0.5
0.7
0.9
1.1
1.3
1.5
Forward Voltage, (V)
11
SA303
GENERAL
Please read Application Note 1 “General Operating Considerations” which covers stability, supplies, heat
sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www.apexanalog.com for Apex Microtechnology’s complete Application Notes library, Technical Seminar Workbook, and
Evaluation Kits.
SA303 OPERATION
The SA303 is designed primarily to drive three phase motors. However, it can be used for any application
requiring three high current outputs. The signal set of the SA303 is designed specifically to interface with a
DSP or microcontroller. A typical system block diagram is shown in the figure below. Over-temperature,
Short-Circuit and Current Limit fault signals provide important feedback to the system controller which can
safely disable the output drivers in the presence of a fault condition. High side current monitors for all three
phases provide performance information which can be used to regulate or limit torque.
Figure 13: System Diagram
VDD
Current
monitor
signals
VS (phase B&C)
35-37
VS (phase A)
25-27
16
8
19
10
SC
TEMP
CL/DIS 1
VS +
17
8
6
IA
IB
IC
GND
PWM
Signals
DIS 2
18
At
Ab
Bt
Bb
15
14
12
13
Ct
Cb
5
4
SGND
Microcontroller
or DSC
Brushless
Motor
28, 29
33, 34
38, 39
11
GND
Sensing
Circuits
12
40-42
PGND (C)
30-32
PGND (A&B)
SGND
OUT A
OUT B
OUT C
Sensor- Hall Sensors
or
Sensorless- Input from Stator leads
SA303U Rev H
SA303
The block diagram in Figure 14 illustrates the features of the input and output structures of the SA303.
For simplicity, a single phase is shown.
Figure 14: Input and Output Structure for a Single Phase
TRUTH TABLE
At, Bt, Ab, Ia, Ib,
Ct
Bb, Cb
Ic
ILIM/
DIS1
DIS2
Out A, Out B, Out
C
Comments
0
0
X
X
X
High-Z
Top and Bottom output FETs for that phase are
turned off.
0
1