SA53-IHZ

SA53 SA53 SA53 P r o dd uu cc tt IInnnnoovvaatti ioonn FFr roomm Switching Amplifier FEATURES ♦ Low Cost Intelligent Switching Amplifier ♦ Directly Connects to Most Embedded Microcontrollers and Digital Signal Controllers ♦ Integrated Gate Driver Logic with Dead-time Generation and Shoot-through Prevention ♦ Wide Power Supply Range (8.5 V To 60 V) ♦ Over 10A Peak Output Current per Phase ♦ Independent Current Sensing for each Output ♦ User Programmable Cycle-by-cycle Current Limit Protection ♦ Over-Current and Over-Temperature Warning Signals APPLICATIONS ♦ Bidirectional DC Brush Motors ♦ 2 Unidirectional DC Brush Motors ♦ 2 Independent Solenoid Actuators ♦ Stepper Motors DESCRIPTION The SA53 is a fully integrated switching amplifier designed primarily to drive DC brush motors. Two independent half bridges provide over 10 amperes peak output current under microcontroller or DSC control. Thermal and short circuit monitoring is provided, which generates fault signals for the microcontroller to take appropriate action. A block diagram is provided in Figure 1. Additionally, cycle-by-cycle current limit offers user programmable hardware protection independent of the microcontroller. Output current is measured using an innovative low loss technique. The SA53 is built using a multi-technology process allowing CMOS logic control and complementary DMOS output power devices on the same IC. Use of P-channel high side FETs enables 60V operation without bootstrap or charge pump circuitry. The HSOP surface mount package balances excellent thermal performance with the advantages of a low profile surface mount package. FIGURE 1. BLOCK DIAGRAM VS + VDD SC TEMP ILIM/D IS 1 I1 I2 Fault Logic I1' VS 2 VDD VDD I1' I2' I2' D IS 2 Gate Control 1t 1b P ha se 1 PWM Signals V S1 O ut 1 O ut 2 Control Logic 2t 2b P ha se 2 SGND SA53 Switching Amplifier PGND 1 PGND 2 GND SA53U www.cirrus.com Copyright © Cirrus Logic, Inc. 2010 (All Rights Reserved) JUN 20101 APEX − SA53UREVC SA53 Product Innovation From 1. CHARACTERISTICS AND SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units SUPPLY VOLTAGE VS 60 V SUPPLY VOLTAGE VDD 5.5 V (VDD+0.5) V LOGIC INPUT VOLTAGE (-0.5) OUTPUT CURRENT, peak, 10ms (NOTE 2) IOUT 10 A POWER DISSIPATION, avg, 25ºC (NOTE 2) PD 100 W TS 260 °C TEMPERATURE, solder, 10sec TEMPERATURE, junction (NOTE 2) TEMPERATURE RANGE, storage OPERATING TEMPERATURE, case 150 °C TSTG TJ −55 +125 °C TA −25 +85 °C SPECIFICATIONS PARAMETER TEST CONDITIONS (Note 1) MIN TYP MAX UNITS 1 V LOGIC INPUT LOW INPUT HIGH 1.8 V OUTPUT LOW 0.3 OUTPUT HIGH 3.7 OUTPUT CURRENT (SC, Temp, ILIM/DIS1) V V 50 mA POWER SUPPLY VS UVLO VS UNDERVOLTAGE LOCKOUT, (UVLO) 50 60 8.3 VDD 4.5 V V 5.5 V SUPPLY CURRENT, VS 20 kHz (One phase switching at 50% duty cycle) , VS=50V, VDD=5V 25 30 mA SUPPLY CURRENT, VDD 20 kHz (One phase switching at 50% duty cycle) , VS=50V, VDD=5.5V 5 6.5 mA CURRENT LIMIT CURRENT LIMIT THRESHOLD (Vth) 3.75 V Vth HYSTERESIS 100 mV OUTPUT CURRENT, CONTINUOUS 25ºC Case Temperature RISING DELAY, TD (RISE) See Figure 10 270 ns FALLING DELAY, TD (FALL) See Figure 10 270 ns DISABLE DELAY, TD (DIS) See Figure 10 200 ns ENABLE DELAY, TD (DIS) See Figure 10 200 ns RISE TIME, T (RISE) See Figure 11 50 ns FALL TIME, T (FALL) See Figure 11 50 ns ON RESISTANCE SOURCING (P-CHANNEL) 3A Load 400 mΩ ON RESISTANCE SINKING (N-CHANNEL) 3A Load 400 mΩ 2 3 A SA53U SA53 Product Innovation From SPECIFICATIONS, continued PARAMETER TEST CONDITIONS (Note 1) MIN TYP MAX UNITS THERMAL THERMAL WARNING 135 ºC THERMAL WARNING HYSTERESIS 40 ºC RESISTANCE, junction to case Full temperature range TEMPERATURE RANGE, case Meets Specifications 1.25 −25 1.5 ºC/W +85 ºC NOTES: 1. (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TC = 25°C). 2. Long term operation at elevated temperature will result in reduced product life. De-rate internal power dissipation to achieve high MTBF. 3. Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. FIGURE 2A. 44-pin HSOP Slug Up, Package Style HU SA53U FIGURE 2B. 64-pin QFP, Package Style HQ 3 SA53 10 5 8 7.5 7 ONE PHASE SWITCHING FREQUENCY = 20kHz 50% DUTY CYCLE 20 30 40 50 VS SUPPLY VOLTAGE (V) VDD SUPPLY CURRENT ONE PHASE SWITCHING FREQUENCY = 20kHz 50% DUTY CYCLE 6.5 6 125°C 5.5 25°C 5 4.5 4 10 20 30 40 50 VS SUPPLY VOLTAGE (V) RDS(on),(Ω) RDS(on),(Ω) 40 ONE PHASE SWITCHING @ 50% DUTY CYCLE; VS=50V 20 0 50 VDD SUPPLY CURRENT 120 4.8 4.7 4.6 ONE PHASE SWITCHING @ 50% DUTY CYCLE; VS=50V 50 1 0.1 0.01 100 150 200 250 300 FREQUENCY (kHz) 4.9 5 (N-Channel) 100 150 200 250 300 FREQUENCY (kHz) 0.1 1 SENSE CURRENT (mA) 10 POWER DERATING 100 80 60 40 20 0 -40 0 40 80 120 CASE TEMPERATURE, TC DIODE FORWARD VOLTAGE - TOP FET (P-Channel) 4 CURRENT (A) CURRENT (A) 60 ON RESISTANCE - TOP FET 4 3 2 1 4 80 0.8 0.75 (P-Channel) 0.7 0.65 0.6 VS=11 0.55 VS=13 0.5 0.45 VS=15 0.4 0.35 0.3 VS>17 0.25 0.2 0.15 0 1 2 3 4 5 6 7 8 9 10 IOUT,(A) DIODE FORWARD VOLTAGE - BOTTOM FET 0 0.5 100 4.5 0 ON RESISTANCE - BOTTOM FET 5 120 5 60 0.8 0.75 (N-Channel) 0.7 0.65 0.6 0.55 VS=11 0.5 VS=13 0.45 VS=15 0.4 0.35 VS=17 0.3 0.25 0.2 VS>22 0.15 0 1 2 3 4 5 6 7 8 9 10 IOUT,(A) 140 0 60 CURRENT SENSE 160 LOAD CURRENT (A) 25°C 10 POWER DISSIPATION, PD VS SUPPLY CURRENT (mA) 125°C 15 VS SUPPLY CURRENT 180 20 0 10 VDD SUPPLY CURRENT (mA) VS SUPPLY CURRENT VDD SUPPLY CURRENT (mA) VS SUPPLY CURRENT (mA) 25 Product Innovation From 3 2 1 0.7 0.9 1.1 1.3 FORWARD VOLTAGE (V) 1.5 0 0.5 0.7 0.9 1.1 1.3 FORWARD VOLTAGE (V) 1.5 SA53U SA53 Product Innovation From FIGURE 3A. EXTERNAL CONNECTIONS - 44-pin HSOP TOP (SLUG) VIEW 23 SA53HU-IH XXXXXXXXXXXX COO 22 NC NC NC TEMP DIS1 I1 Vdd 1t 1b SGND SGND SGND Ilim/DIS1 SGND SC I2 2t 2b NC NC NC NC 44 1 PGND/SLUG NC VS1 VS1 NC OUT1 OUT1 NC PGND1 PGND1 NC NC VS2 VS2 NC OUT2 OUT2 NC PGND2 PGND2 NC PGND/SLUG PIN #1 ID’s: CHAMFER, ESD Triangle TABLE 1A. PIN DESCRIPTIONS - 44-pin HSOP Pin # Pin Name Signal Type VS (phase 1) OUT 2 PGND (phase 2) SC 2b 2t I2 10 ILIM/DIS1 9,11,12,13 14 15 16 17 18 19 35,36 28,29 31,32 23,44 1,2,3,4,20, 21,22,24,27, 30,33,34,37, 40,43 SGND 1b 1t VDD I1 DIS2 TEMP VS (phase 2) OUT 1 PGND (phase 1) HS High Voltage Supply (8.5-60V) supplies phase 1 only Half Bridge 2 Power Output High Current GND Return Path for Power Output 2 Indication of a short of an output to supply, GND or another phase Logic high commands 2 phase lower FET to turn on Logic high commands 2 phase upper FET to turn on Phase 2 current sense output As an output, logic high indicates cycle-by-cycle current limit, and logic low indicates normal operation. As an input, logic high places Logic Input/Output all outputs in a high impedance state and logic low disables the cycle-by-cycle current limit function. Power Analog and digital GND – internally connected to PGND Logic Input Logic high commands 1 phase lower FET to turn on Logic Input Logic high commands 1 phase upper FET to turn on Power Logic Supply (5V) Analog Output Phase 1 current sense output Logic Input Logic high places all outputs in a high impedance state Logic Output Thermal indication of die temperature above 135ºC Power High Voltage Supply phase 2 Power Output Half Bridge 1 Power Output Power High Current GND Return Path for Power Outputs 1 & 2 Mechanical Pins connected to the package heat slug NC --- SA53U Power Power Output Power Logic Output Logic Input Logic Input Analog Output Simplified Pin Description 25,26 38,39 41,42 8 5 6 7 Do Not Connect 5 SA53 Product Innovation From 33 TABLE 1B. PIN DESCRIPTIONS - 64-pin QFP Pin # Pin Name OUT 2 OUT 2 NC VS2 VS2 VS2 VS2 NC NC NC NC NC PGND 1 PGND 1 PGND 1 PGND 1 NC OUT 1 OUT 1 OUT 1 HS NC VS1 VS1 VS1 NC I1 NC DIS2 NC TEMP HS 1 21 I2 NC SC NC SGND NC ILIM/DIS1 NC SGND NC SGND NC SGND NC 1b NC 1t NC VDD NC 53 NC 2t NC 2b NC HS HS PGND 2 PGND 2 PGND 2 NC OUT 2 FIGURE 3B. EXTERNAL CONNECTIONS - 64-pin QFP Signal Type VS (phase 1) OUT 2 PGND (phase 2) SC 2b 2t I2 7 ILIM/DIS1 5,9,11,13 15 17 19 21 23 25 46,47,48,49 33,34,35 37,38,39,40 26,27,58,59 2,4,6,8,10, 12,14,16,18, 20,22,24,28, 32,36,41,42, 43,44,45,50, 54,60,62,64 SGND 1b 1t VDD I1 DIS2 TEMP VS (phase 2) OUT 1 PGND (phase 1) HS High Voltage Supply (8.5-60V) supplies phase 1 only Half Bridge 2 Power Output High Current GND Return Path for Power Output 2 Indication of a short of an output to supply, GND or another phase Logic high commands 2 phase lower FET to turn on Logic high commands 2 phase upper FET to turn on Phase 2 current sense output As an output, logic high indicates cycle-by-cycle current limit, and logic low indicates normal operation. As an input, logic high places Logic Input/Output all outputs in a high impedance state and logic low disables the cycle-by-cycle current limit function. Power Analog and digital GND – internally connected to PGND Logic Input Logic high commands 1 phase lower FET to turn on Logic Input Logic high commands 1 phase upper FET to turn on Power Logic Supply (5V) Analog Output Phase 1 current sense output Logic Input Logic high places all outputs in a high impedance state Logic Output Thermal indication of die temperature above 135ºC Power High Voltage Supply phase 2 Power Output Half Bridge 1 Power Output Power High Current GND Return Path for Power Outputs 1 & 2 Mechanical Pins connected to the package heat slug NC --- 6 Power Power Output Power Logic Output Logic Input Logic Input Analog Output Simplified Pin Description 29,30,31 51,52,53 55,56,57 3 61 63 1 Do Not Connect SA53U Product Innovation From SA53 1.2 Pin Descriptions VS: Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high frequency characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to the VS and PGND pins as possible. Additional capacitance will be required at the VS pins to handle load current peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional discussion regarding bypass capacitor selection. Note that VS pins 29-31 carry only the phase 1 supply current. Pins 46-49 carry supply current for phase 2. Phase 1 may be operated at a different supply voltage from phase 2. Both VS voltages are monitored for undervoltage conditions. OUT 1, OUT 2: These pins are the power output connections to the load. NOTE: When driving an inductive load, it is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be connected to each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6) PGND: Power Ground. This is the ground return connection for the output FETs. Return current from the load flows through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1 of this datasheet for more details. SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input commands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately 200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal 12kΩ series resistor. 1b, 2b: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower Nchannel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low side N-channel FET off. If 2b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection circuitry will turn off both FETs in order to prevent shoot-through on that output phase. Protection circuitry also includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching of the top and bottom input signals. 1t, 2t: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper Pchannel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top Pchannel FET off. I1, I2: Current sense pins. The SA53 supplies a positive current to these pins which is proportional to the current flowing through the top side P-channel FET for that phase. Commutating currents flowing through the backbody diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins. Nor do currents flowing through the low side N-channel FET, in either direction, register at the current sense pins. A resistor connected from a current sense pin to SGND creates a voltage signal representation of the phase current that can be monitored with ADC inputs of a processor or external circuitry. The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this functionality are described in the applications section of this datasheet. ILIM/DIS1: This pin is directly connected to the disable circuitry of the SA53. Pulling this pin to logic high places OUT 1 and OUT 2 in a high impedance state. This pin is also connected internally to the output of the current limit latch through a 12kΩ resistor and can be monitored to observe the function of the cycle-by-cycle current limit feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature. SGND: This is the ground return connection for the VDD logic power supply pin. All internal analog and logic circuitry is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it is highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible. Failure do to this may result in oscillations on the output pins during rising or falling edges. VDD: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the SA53. This pin requires decoupling (at least 0.1μF capacitor with good high frequency characteristics is recommended) to the SGND pin. DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT 1 and OUT 2 in a high impedance state when pulled high. DIS2 has an internal 12kΩ pull-down resistor and may therefore be left unconnected. SA53U 7 SA53 Product Innovation From TEMP: This logic level output goes high when the die temperature of the SA53 reaches approximately 135ºC. This pin WILL NOT automatically disable the device. The TEMP pin includes a 12kΩ series resistor. HS: These pins are internally connected to the thermal slug on the reverse of the package. They should be connected to GND. Neither the heat slug nor these pins should be used to carry high current. NC: These “no-connect” pins should be left unconnected. 2. SA53 OPERATION The SA53 is designed primarily to drive DC brush motors. However, it can be used for any application requiring two high current outputs. The signal set of the SA53 is designed specifically to interface with a DSP or microcontroller. A typical system block diagram is shown in the figure below. Over-temperature, Short-Circuit and Current Limit fault signals provide important feedback to the system controller which can safely disable the output drivers in the presence of a fault condition. High side current monitors for both phases provide performance information which can be used to regulate or limit torque. VDD SC TEMP ILIM/D IS 1 VS + VS 1 VS 2 Fault Logic Current I1 monitor Signals I2 GND DC BRUSH MOTOR D IS 2 1t 1b Control Logic PWM Signals Gate Control OUT 1 1 2 OUT 2 2t 2b SGND M icrocontroller or DSC SA53 Switching Amplifier PGND 2 PGND 1 SGND GND FIGURE 4. SYSTEM DIAGRAM The block diagram in Figure 5 illustrates the features of the input and output structures of the SA53. For simplicity, a single phase is shown. 8 SA53U SA53 Product Innovation From 12k SC Current Sense SC Logic VDD _ Ref 12k I LIM/DIS1 Vth + TEMP Temp Sense _ + 12k I1' Lim 1 Lim 2 I1 UVLO DIS2 12k VS 1t Gate Control OUT 1 1b PGND SGND FIGURE 5. INPUT AND OUTPUT STRUCTURES FOR A SINGLE PHASE X X >Vth X X X X X X X X X X X X SA53U DIS2 OUT 1 OUT 2 I1, I2 0 X 1