SA53HU

SA53 RoHS Switching Amplifier COMPLIANT FEATURES • • • • • • • • Low Cost Intelligent Switching Amplifier Directly Connects to Most Embedded Microcontrollers and Digital Sig‐ nal Controllers Integrated Gate Driver Logic with Dead‐time Generation and Shoot‐ through Prevention Wide Power Supply Range (8.5 V To 60 V) Over 10A Peak Output Current per Phase Independent Current Sensing for each Output User Programmable Cycle‐by‐Cycle Current Limit Protection Over‐Current and Over‐Temperature Warning Signals APPLICATIONS • • • • Bidirectional DC Brush Motors 2 Unidirectional DC Brush Motors 2 Independent Solenoid Actuators Stepper Motors DESCRIPTION The SA53 is a fully integrated switching amplifier designed primarily to drive DC brush motors. Two inde‐ pendent half bridges provide over 10 amperes peak output current under microcontroller or DSC control. Thermal and short circuit monitoring is provided, which generates fault signals for the microcontroller to take appropriate action. Additionally, cycle‐by‐cycle current limit offers user programmable hardware protection independent of the microcontroller. Output current is measured using an innovative low loss technique. The SA53 is built using a multi‐technology process allowing CMOS logic control and complementary DMOS output power devices on the same IC. Use of P‐channel high side FETs enables 60V operation without bootstrap or charge pump circuitry. The HSOP surface mount package balances excellent thermal performance with the advantages of a low profile surface mount package. Figure 1: Block Diagram VS+ VDD SC TEMP ILIM/DIS1 I1 I2 Fault Logic PWM Signals 1t 1b 2t 2b I1' I2' VDD VDD I2' I1' Gate Control DIS2 VS2 VS1 Out 1 Phase 1 Out 2 Control Logic Phase 2 SGND ^ϱϯ^ǁŝƚĐŚŝŶŐŵƉůŝĮĞƌ PGND 1 PGND 2 GND www.apexanalog.com © Apex Microtechnology Inc. All rights reserved Mar 2019 SA53U Rev G SA53 TYPICAL CONNECTION Figure 2: Typical Connection VS + VDD 100nF 1μF VDD Fault WƌŽƚĞĐƟŽŶ CL/DIS 1 DIS 2 SC TEMP Current monitor signals I1 I2 VS 2 VS 1 VS OUT 1 GND SA53 VS 1t 1b PWM Signals 220μF LOAD OUT 2 2t 2b HS SGND PGND 1 PGND 2 Microcontroller or DSC GND 2 SA53U Rev G SA53 PINOUT AND DESCRIPTION TABLE Figure 3: External Connections 1 NC 2 NC 3 NC HS 44 NC 43 PGND 2 42 41 PGND 2 NC 40 OUT 2 39 4 NC 5 2b 6 2t OUT 2 38 NC 37 7 I2 8 SC 9 SGND 10 CL/DIS1 11 SGND 12 SGND 13 SGND 14 1b 15 1t 16 V 17 18 19 DD I1 DIS2 TEMP 20 NC 21 NC 22 NC SA53 ;ŽƩŽŵsŝĞǁ͕ ŽƉƉŽƐŝƚĞŚĞĂƚƐůƵŐ) VS_2 36 V _2 35 S NC 34 33 NC PGND 1 32 PGND 1 31 30 NC OUT 1 29 28 OUT 1 27 NC VS_1 26 VS_1 25 24 NC HS 23 Case tied to Pins 23 and 44. Allow no current in case. Bypassing of supplies is required. Pin Number Name Description 5 2b Logic high commands phase 2 lower (bottom) FET to turn on. 6 2t Logic high commands phase 2 upper (top) FET to turn on. 7 I2 Phase 2 current sense output. Outputs a current proportional to ID of the upper (top) FET of channel 2. Connect to a sense resistor to SGND to monitor current. 8 SC Short circuit output. When a short circuit condition is experienced on either chan‐ nel, this pin will go high for 200ns. This does not disable the outputs. 9, 11, 12, 13 SGND Signal ground. Reference all logic circuitry to these pins. Connect to PGND 1 and PGND 2 as close to the amplifier as possible. 10 CL/DIS1 Logic high places both outputs in a high impedance state. Pulling to logic low dis‐ ables cycle‐by‐cycle current limit. If unconnected, cycle‐by‐cycle current limit will be allowed to operate. 14 1b Logic high commands phase 1 lower (bottom) FET to turn on. 15 1t Logic high commands phase 1 upper (top) FET to turn on. 16 Vdd Voltage supply for logic circuit. Connect 5 V supply. The ground terminal of the sup‐ ply must be connected to SGND. SA53U Rev G 3 SA53 Pin Number Name Description 17 I1 Phase 1 current sense output. Outputs a current proportional to ID of the upper (top) FET of channel 1. Connect to a sense resistor to SGND to monitor current. 18 DIS2 Logic high places both outputs in a high impedance state. This pin may be left unconnected. 19 TEMP This pin will go logic high when the die temperature reaches 135°C. This does not disable the outputs. 23, 44 HS These pins are internally connected to the heat slug. Connect to PGND. Neither the heatslug nor these pins should carry current. 25, 26 Vs 1 Voltage supply for channel 1. 28, 29 OUT 1 The output connection for channel 1. 31, 32 PGND 1 Power ground. These pins are directly connected to the bottom FET of channel 1. Connect to SGND and PGND 2 as close to the amplifier as possible. 35, 36 Vs 2 Voltage supply for channel 2. 38, 39 OUT 2 The output connection for channel 2. 41, 42 PGND 2 Power ground. These pins are directly connected to the bottom FET of channel 2. Connect to SGND and PGND 1 as close to the amplifier as possible. All Others NC No connection. PIN DESCRIPTIONS VS: Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high frequency characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to the VS and PGND pins as possible. Additional capacitance will be required at the VS pins to handle load current peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional discussion regarding bypass capacitor selection. Note that VS pins 25‐26 carry only the phase 1 supply current. Pins 35‐36 carry supply current for phase 2. Phase 1 may be operated at a different supply voltage from phase 2. Both VS voltages are monitored for undervoltage conditions. OUT 1, OUT 2: These pins are the power output connections to the load. NOTE: When driving an inductive load, it is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be connected to each pin so that they are in parallel with the parasitic back‐body diodes of the output FETs. PGND: Power Ground. This is the ground return connection for the output FETs. Return current from the load flows through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1 of this datasheet for more details. SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input commands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately 200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal 12 kΩ series resistor. 1b, 2b: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower N‐channel output FETs on and off. Logic high turns the bottom N‐channel FET on, and a logic low turns the low side N‐channel FET off. If 1b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection circuitry will turn off both FETs in order to prevent shoot‐through on that output phase. Protection circuitry also includes a dead‐time generator, which inserts dead time in the outputs in the case of simultaneous switching of the top and bottom input signals. 1t, 2t: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper 4 SA53U Rev G SA53 P‐channel FET outputs on and off. Logic high turns the top P‐channel FET on, and a logic low turns the top P‐channel FET off. I1, I2: Current sense pins. The SA53 supplies a positive current to these pins which is proportional to the cur rent flowing through the top side P‐channel FET for that phase. Commutating currents flowing through the backbody diode of the P‐channel FET or through external Schottky diodes are not registered on the current sense pins. Nor do currents flowing through the low side N‐channel FET, in either direction, register at the current sense pins. A resistor connected from a current sense pin to SGND creates a voltage signal representation of the phase current that can be monitored with ADC inputs of a processor or external circuitry. The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this functionality are described in the applications section of this datasheet. CL/DIS1: This pin is directly connected to the disable circuitry of the SA53. Pulling this pin to logic high places  OUT 1 and OUT 2 in a high impedance state. This pin is also connected internally to the output of the  current limit latch through a 12 kΩ resistor and can be monitored to observe the function of the cycle‐ by‐cycle current limit feature. Pulling this pin to a logic low effectively disables the cycle‐by‐cycle current limit feature. SGND: This is the ground return connection for the VDD logic power supply pin. All internal analog and logic circuitry is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms. However, it is highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible. Failure do to this may result in oscillations on the output pins during rising or falling edges. VDD: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the SA53. This pin requires decoupling (at least 0.1μF capacitor with good high frequency characteristics is recommended) to the SGND pin. DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT 1 and OUT 2 in a high impedance state when pulled high. DIS2 has an internal 12 kΩ pull‐down resistor and may therefore be left unconnected. TEMP: This logic level output goes high when the die temperature of the SA53 reaches approximately 135°C. This pin WILL NOT automatically disable the device. The TEMP pin includes a 12 kΩ series resistor. HS: These pins are internally connected to the thermal slug on the reverse of the package. They should be connected to GND. Neither the heat slug nor these pins should be used to carry high current. NC: These “no‐connect” pins should be left unconnected. SA53U Rev G 5 SA53 SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typi‐ cal performance characteristics and specifications are derived from measurements taken at typical supply voltages and TC = 25°C ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units Supply Voltage Vs 60 V Supply Voltage VDD 5.5 V (VDD+0.5) V Logic Input Voltage (‐0.5) Output Current, peak, 10ms 1 IO 10 A 1 PD 100 W 260 °C 150 °C ‐65 +125 °C ‐25 +85 °C Power Dissipation, avg. 25°C Temperature, pin solder, 10s max. Temperature, junction 1 TJ Temperature Range, storage Operating Temperature Range, case TC 1. Long term operation at elevated temperature will result in reduced product life. De‐rate internal power dissipation to achieve high MTBF. LOGIC Parameter Test Conditions Min Typ Input Low Input High Max Units 1 V 1.8 V Output Low 0.3 Output High 3.7 Output Current (SC, Temp, CL/ DIS1) V V 50 mA POWER SUPPLY Parameter Test Conditions VS Min Typ Max Units UVLO 50 60 V VS Undervoltage Lockout, (UVLO) 8.3 VDD 4.5 V 5.5 V Supply Current, VS 20 kHz (One phase switching at 50% duty cycle), VS=50V, VDD=5V 25 30 mA Supply Current, VDD 20 kHz (One phase switching at 50% duty cycle), VS=50V, VDD=5.5V 5 6.5 mA 6 SA53U Rev G SA53 CURRENT LIMIT Parameter Test Conditions Min Typ Max Units Current Limit Threshold (Vth) 3.75 V Vth Hysteresis 100 mV OUTPUT Parameter Test Conditions Min Typ Max 3 Units Current, continuous 25°C Case Temperature A Rising Delay, TD (rise) See Figure 20 270 ns Falling Delay, TD (fall) See Figure 20 270 ns Disable Delay, TD (dis) See Figure 20 200 ns Enable Delay, TD (dis) See Figure 20 200 ns Rise Time, t (rise) See Figure 21 50 ns Fall Time, t (fall) See Figure 21 50 ns On Resistance Sourcing (P‐Chan‐ nel) 5A Load 400 mΩ On Resistance Sinking (N‐Channel) 5A Load 400 mΩ THERMAL Parameter Test Conditions Min Typ Max Units Thermal Warning 135 °C Thermal Warning Hysteresis 40 °C Resistance, junction to case Full temp range Temperature Range, case Meets Specs 1.25 ‐25 1.5 °C/W +85 °C Note: Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. SA53U Rev G 7 SA53 TYPICAL PERFORMANCE GRAPHS Figure 4: Vs Supply Current Figure 5: Vs Supply Current 25 180 20 VS Supply Currrent (mA) VS Supply Currrent (mA) 160 125°C 15 25°C 10 5 0 10 ONE PHASE SWITCHING FREQUENCY = 20 kHz 50% DUTY CYCLE 20 30 40 140 120 100 80 60 40 ONE PHASE SWITCHING @ 50% DUTY CYCLE; VS = 50V 20 50 0 0 60 50 100 VS Supply Voltage (V) 200 250 300 Frequency, F (kHz) Figure 6: Current Sense Figure 7: VDD Supply Current 10 8 VDD Supply Currrent (mA) 7.5 Load Current (A) 150 1 7 ONE PHASE SWITCHING FREQUENCY = 20 kHz 50% DUTY CYCLE 6.5 6 125°C 5.5 25°C 5 4.5 0.1 0.01 0.1 1 Sense Current (mA) 8 10 4 10 20 30 40 50 60 VS Supply Voltage (V) SA53U Rev G SA53 Figure 8: VDD Supply Current Figure 9: Power Derating 120 WŽǁĞƌŝƐƐŝƉĂƟŽŶ͕WD (W) VDD Supply Currrent (mA) 5 4.9 4.8 4.7 4.6 ONE PHASE SWITCHING @ 50% DUTY CYCLE; VS=50V 4.5 0 50 100 200 150 250 100 80 60 40 20 0 -40 300 0 Frequency, F (kHz) VS=13 VS=15 VS=17 VS>22 3 4 5 6 IOUT, (A) SA53U Rev G RDS (on), (ё) RDS (on), (ё) VS=11 2 7 120 Figure 11: On Resistance - Top FET (N-Channel) 1 80 Case Temperature, TC (°C) Figure 10: On Resistance - Bottom FET 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0 40 8 9 10 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0 (P-Channel) VS=11 VS=13 VS=15 VS>17 1 2 3 4 5 6 7 8 9 10 IOUT, (A) 9 SA53 Figure 12: Diode Forward Voltage Bottom FET Figure 13: Diode Forward Voltage Top FET 5 5 (P-Channel) (N-Channel) 4 Current, (A) Current, (A) 4 3 2 1 0 0.5 2 1 0.7 0.9 1.1 Forward Voltage, (V) 10 3 1.3 1.5 0 0.5 0.7 0.9 1.1 1.3 1.5 Forward Voltage, (V) SA53U Rev G SA53 GENERAL Please read Application Note 1 “General Operating Considerations” which covers stability, supplies, heat sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www.apexana‐ log.com for Apex Microtechnology’s complete Application Notes library, Technical Seminar Workbook, and Evaluation Kits. SA53 OPERATION The SA53 is designed primarily to drive DC brush motors. However, it can be used for any application requiring two high current outputs. The signal set of the SA53 is designed specifically to interface with a DSP or microcontroller. A typical system block diagram is shown in the figure below. Over‐temperature, Short‐Cir‐ cuit and Current Limit fault signals provide important feedback to the system controller which can safely dis‐ able the output drivers in the presence of a fault condition. High side current monitors for both phases provide performance information which can be used to regulate or limit torque. Figure 14: System Diagram VDD 8 19 10 SC TEMP CL/DIS 1 Current monitor signals 1t 1b VS 2 35, 36 VS 1 25, 26 17 7 I1 I2 DIS 2 16 VS + GND 18 DC Brush Motor 15 14 PWM Signals 2t 2b SGND Microcontroller or DSC OUT 1 38, 39 OUT 2 6 5 11, 12, 13 SGND SA53U Rev G 28, 29 41, 42 PGND 2 31, 32 PGND 1 GND 11 SA53 The block diagram in Figure 15 illustrates the features of the input and output structures of the SA53. For simplicity, a single phase is shown. Figure 15: Input And Output Structures For A Single Phase Layout Considerations 12 SA53U Rev G SA53 TRUTH TABLE At, Bt, Ab, Ia, Ib, Ct Bb, Cb Ic 0 0 ILIM/ DIS1 DIS2 Out A, Out B, Out C X X X High‐Z Top and Bottom output FETs for that phase are turned off. Bottom output FET for that phase is turned on. Comments 0 1