AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Features
Document No: AX58400/V1.02/03/17/23
⚫ Voltage scaling in Run and Stop mode (6
configurable ranges)
⚫ Backup regulator (~0.9 V)
⚫ Voltage reference for analog peripheral/VREF+
⚫ 1.2 to 3.6 V VBAT supply
⚫ Low-power modes: Sleep, Stop, Standby and
VBAT supporting battery charging
A System-in-Package (SiP) product based on
STSTM32H755 microcontroller and ASIX EtherCAT
slave controller
STM32H755 Dual-Core ARM® Cortex® -M7 &
Cortex® -M4 microcontroller
⚫ 32-bit Arm® Cortex® -M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/ 2.14
DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
⚫ 32-bit Arm® 32-bit Cortex® -M4 core with
FPU, Adaptive real-time accelerator (ST ART
Accelerator™) for internal Flash memory and
external memories, frequency up to 240 MHz,
MPU, 300 DMIPS/1.25 DMIPS /MHz
(Dhrystone 2.1), and DSP instructions
Low-power consumption
⚫ VBAT battery operating mode with charging
capability
⚫ CPU and domain power state monitoring pins
⚫ 2.95 μA in Standby mode (Backup SRAM
OFF, RTC/LSE ON)
Clock management
⚫ Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 KHz LSI
⚫ External oscillators: 4-48 MHz HSE, 32.768
KHz LSE
⚫ 3× PLLs (1 for the system clock, 2 for kernel
clocks) with Fractional mode
Memories
⚫ 2 Mbytes of dual bank Flash memory with
read-while-write support
⚫ 1 Mbyte of RAM: 192 Kbytes of TCM RAM
(inc. 64 Kbytes of ITCM RAM + 128 Kbytes
of DTCM RAM for time critical routines), 864
Kbytes of user SRAM, and 4 Kbytes of SRAM
in Backup domain
⚫ Dual mode Quad-SPI memory interface
running up to 133 MHz
⚫ Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND Flash
memory clocked up to 125 MHz in
Synchronous mode
⚫ CRC calculation unit
Interconnect matrix
⚫ 3 bus matrices (1 AXI and 2 AHB)
⚫ Bridges (5× AHB2-APB, 2× AXI2-AHB)
4 DMA controllers to unload the CPU
⚫ 1× high-speed master direct memory access
controller (MDMA) with linked list support
⚫ 2× dual-port DMAs with FIFO
⚫ 1× basic DMA with request router capabilities
Up to 35 communication peripherals
⚫ 4× I2Cs FM+ interfaces (SMBus/PMBus)
⚫ 4× USARTs/4x UARTs (ISO7816 interface,
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
⚫ 6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
⚫ 4x SAIs (serial audio interface)
⚫ SPDIFRX interface
⚫ SWPMI single-wire protocol master I/F
⚫ MDIO Slave interface
⚫ 2× SD/SDIO/MMC interfaces (up to 125 MHz)
⚫ 2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
⚫ 2× USB OTG interfaces (1FS, 1HS/FS) crystalless solution with LPM and BCD
⚫ Ethernet MAC interface with DMA controller
⚫ HDMI-CEC
⚫ 8- to 14-bit camera interface (up to 80 MHz)
Security
⚫ ROP, PC-ROP, active tamper, secure firmware
upgrade support, Secure access mode
General-purpose input/outputs (GPIO)
⚫ Up to 97 I/O ports with interrupt capability
Reset and power management
⚫ 3 separate power domains which can be
independently clock-gated or switched off:
⚫ D1: high-performance capabilities
⚫ D2: communication peripherals and timers
⚫ D3: reset/clock control/power management
⚫ 1.62 to 3.6 V application supply and I/Os
⚫ POR, PDR, PVD and BOR
⚫ Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs
⚫ Embedded regulator (LDO) to supply the
digital circuitry
⚫ High power-efficiency SMPS step-down
converter regulator to directly supply VCORE
and/or external circuitry
ASIX Electronics Corporation
4F, No.8, Hsin Ann Rd.,
Hsinchu Science Park,
Hsinchu, Taiwan 30078
11 analog peripherals
⚫ 3× ADCs with 16-bit max. resolution (up to 36
channels, up to 3.6 MSPS)
⚫ 1× temperature sensor
1
Released Date: 03/17/2023
TEL: +886-3-579-9500
FAX: +886-3-579-9558
https://www.asix.com.tw/
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
⚫
⚫
⚫
⚫
⚫ HASH (MD5, SHA-1, SHA-2), HMAC
⚫ True random number generators
2× 12-bit D/A converters (1 MHz)
2× ultra-low-power comparators
2× operational amplifiers (7.3 MHz bandwidth)
1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
Debug mode
⚫ SWD & JTAG interfaces
⚫ 4 Kbytes Embedded Trace Buffer
Graphics
⚫ LCD-TFT controller up to XGA resolution
⚫ ST Chrom-ART graphical hardware
Accelerator™ (DMA2D) to reduce CPU load
⚫ Hardware JPEG Codec
96-bit Unique Identifier (UID)
EtherCAT Slave Controller (ESC) Sub-system
2 Integrated Fast Ethernet PHYs
3rd Ethernet MII Port for flexible EtherCAT
network configuration
8 Fieldbus Memory Management Units
(FMMUs)
8 Sync Managers
64-bit distributed clock support allows
synchronization with other EtherCAT devices
9K bytes RAM
Step & Direction Controller
Incremental and Hall Encoder Interface
SPI Master Controller
Emergency Stop Input
Configurable Watchdog for Outputs and Inputs
Monitoring
20 GPIOs controled by EtherCAT direclty
Up to 22 timers and watchdogs
⚫ 1× high-resolution timer (2.1 ns max
resolution)
⚫ 2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
⚫ 2× 16-bit advanced motor control timers (up to
240 MHz)
⚫ 10× 16-bit general-purpose timers (up to 240
MHz)
⚫ 5× 16-bit low-power timers (up to 240 MHz)
⚫ 4× watchdogs (independent and window)
⚫ 2× SysTick timers
⚫ RTC with sub-second accuracy and hardware
calendar
225LD EHS-TFBGA 13x13 mm, 0.8-mm pitch,
RoHS Compliant Package
Cryptographic acceleration
⚫ AES 128, 192, 256, TDES,
Operating Temperature Range: -40 to +85°C
Target Applications
EtherCAT IO-Link Master
EtherCAT Junction Slave Module
Communication Module
Operator HMI Interfaces
Motion/Motor Control
Digital I/O Control
Robotics
Sensors Data Acquisition
Typical Applications Diagram
ASIX Electronics Corporation
4F, No.8, Hsin Ann Rd.,
Hsinchu Science Park,
Hsinchu, Taiwan 30078
2
Released Date: 03/17/2023
TEL: +886-3-579-9500
FAX: +886-3-579-9558
https://www.asix.com.tw/
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Functional Block Diagram
3
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Copyright © 2021 ASIX Electronics Corporation. All rights reserved.
Copyright © 2019 STMicroelectronics – All rights reserved for STM32H755 microcontroller.
DISCLAIMER
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may
make changes to the product specifications and descriptions in this document at any time, without notice.
ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without
limitation warranties of merchantability, fitness for a particular purpose, and non-infringement.
Designers must not rely on the absence or characteristics of any features or registers marked “reserved”, “undefined”
or “NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting
a design of ASIX products.
TRADEMARKS
ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the
property of their respective owners.
EtherCAT® is a registered trademark and patented technology, licensed by Beckhoff Automation GmbH, Germany.
STM32, ART Accelerator™, Chrom-ART graphical hardware Accelerator™ are registered trademarks and patented
technologies, licensed by STMicroelectronics International N.V.
Arm® and Cortex® are registered trademarks and patented technologies, licensed by Arm Limited (or its subsidiaries).
4
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Table of Contents
1
INTRODUCTION ............................................................................................................................................... 13
GENERAL DESCRIPTION .................................................................................................................................. 13
BLOCK DIAGRAM............................................................................................................................................ 17
PINOUT DIAGRAM ........................................................................................................................................... 18
SIGNAL DESCRIPTION ..................................................................................................................................... 19
1.4.1
Main System Pin Description ................................................................................................................. 19
1.4.2
ESC Sub-system Pin Description ........................................................................................................... 53
1.4.3
Power/Ground Pin Description ............................................................................................................. 57
2
FUNCTION DESCRIPTION.............................................................................................................................. 58
DUAL STM32 ARM® CORTEX® CORES ........................................................................................................... 58
2.1.1
Arm® Cortex® -M7 with FPU .................................................................................................................. 58
2.1.2
Arm® Cortex® -M4 with FPU .................................................................................................................. 59
MEMORY PROTECTION UNIT (MPU) ............................................................................................................... 59
MEMORIES ...................................................................................................................................................... 60
2.3.1
Embedded Flash memory ....................................................................................................................... 60
2.3.2
Secure access mode ................................................................................................................................ 60
2.3.3
Embedded SRAM.................................................................................................................................... 60
™
2.3.4
ST ART accelerator ............................................................................................................................ 61
BOOT MODES .................................................................................................................................................. 63
POWER SUPPLY MANAGEMENT ....................................................................................................................... 63
2.5.1
Power supply scheme ............................................................................................................................. 63
2.5.2
Power supply supervisor ........................................................................................................................ 64
2.5.3
Voltage regulator (SMPS step-down converter and LDO) .................................................................... 65
2.5.4
SMPS step-down converter .................................................................................................................... 65
LOW-POWER STRATEGY .................................................................................................................................. 66
RESET AND CLOCK CONTROLLER (RCC) ......................................................................................................... 67
2.7.1
Clock management ................................................................................................................................. 67
2.7.2
System reset sources............................................................................................................................... 67
GENERAL-PURPOSE INPUT/OUTPUTS (GPIOS) ................................................................................................. 68
BUS-INTERCONNECT MATRIX .......................................................................................................................... 68
DMA CONTROLLERS....................................................................................................................................... 69
ST CHROM-ART ACCELERATOR™ (DMA2D)............................................................................................... 69
NESTED VECTORED INTERRUPT CONTROLLER (NVIC) .................................................................................... 70
EXTENDED INTERRUPT AND EVENT CONTROLLER (EXTI)............................................................................... 70
CYCLIC REDUNDANCY CHECK CALCULATION UNIT (CRC) ............................................................................. 70
FLEXIBLE MEMORY CONTROLLER (FMC) ....................................................................................................... 71
QUAD-SPI MEMORY INTERFACE (QUADSPI)................................................................................................. 71
ANALOG-TO-DIGITAL CONVERTERS (ADCS) .................................................................................................. 71
TEMPERATURE SENSOR ................................................................................................................................... 72
VBAT OPERATION .......................................................................................................................................... 72
DIGITAL-TO-ANALOG CONVERTERS (DAC) .................................................................................................... 73
ULTRA-LOW-POWER COMPARATORS (COMP) ................................................................................................ 73
OPERATIONAL AMPLIFIERS (OPAMP) ............................................................................................................ 73
DIGITAL FILTER FOR SIGMA-DELTA MODULATORS (DFSDM) ......................................................................... 74
DIGITAL CAMERA INTERFACE (DCMI) ........................................................................................................... 75
LCD-TFT CONTROLLER ................................................................................................................................. 76
JPEG CODEC (JPEG) ...................................................................................................................................... 76
RANDOM NUMBER GENERATOR (RNG) .......................................................................................................... 77
CRYPTOGRAPHIC ACCELERATION (CRYP AND HASH) .................................................................................. 77
TIMERS AND WATCHDOGS .............................................................................................................................. 77
2.29.1
High-resolution timer (HRTIM1) ........................................................................................................... 79
5
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
2.29.2
Advanced-control timers (TIM1, TIM8) ................................................................................................. 79
2.29.3
General-purpose timers (TIMx) ............................................................................................................. 80
2.29.4
Basic timers TIM6 and TIM7 ................................................................................................................. 80
2.29.5
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5).................................................... 80
2.29.6
Independent watchdogs .......................................................................................................................... 81
2.29.7
Window watchdogs ................................................................................................................................ 81
2.29.8
SysTick timer .......................................................................................................................................... 81
REAL-TIME CLOCK (RTC), BACKUP SRAM AND BACKUP REGISTERS ............................................................. 82
INTER-INTEGRATED CIRCUIT INTERFACE (I2C) ............................................................................................... 83
UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS RECEIVER TRANSMITTER (USART) ......................................... 84
LOW-POWER UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (LPUART) ........................................... 85
SERIAL PERIPHERAL INTERFACE (SPI)/INTER-INTEGRATED SOUND INTERFACES (I2S) .................................... 85
SERIAL AUDIO INTERFACES (SAI) ................................................................................................................... 85
SPDIFRX RECEIVER INTERFACE (SPDIFRX) ................................................................................................ 86
SINGLE WIRE PROTOCOL MASTER INTERFACE (SWPMI) ................................................................................. 86
MANAGEMENT DATA INPUT/OUTPUT (MDIO) SLAVES .................................................................................. 87
SD/SDIO/MMC CARD HOST INTERFACES (SDMMC) .................................................................................... 87
CONTROLLER AREA NETWORK (FDCAN1, FDCAN2) .................................................................................... 87
UNIVERSAL SERIAL BUS ON-THE-GO HIGH-SPEED (OTG_HS) ......................................................................... 88
ETHERNET MAC INTERFACE WITH DEDICATED DMA CONTROLLER (ETH) ................................................... 88
HIGH-DEFINITION MULTIMEDIA INTERFACE (HDMI)-CONSUMER ELECTRONICS CONTROL (CEC) .................. 89
DEBUG INFRASTRUCTURE ............................................................................................................................... 89
ESC (ETHERCAT) SUB-SYSTEM ..................................................................................................................... 90
2.45.1
Overview ................................................................................................................................................ 90
2.45.2
Features ................................................................................................................................................. 91
2.45.4
ESC Configuration ................................................................................................................................. 93
2.45.5
Memory Map ........................................................................................................................................ 102
3
ELECTRICAL SPECIFICATIONS ................................................................................................................ 112
PARAMETER CONDITIONS ............................................................................................................................. 112
3.1.1
Minimum and maximum values ............................................................................................................ 112
3.1.2
Typical values ...................................................................................................................................... 112
3.1.3
Typical curves ...................................................................................................................................... 112
3.1.4
Loading capacitor ................................................................................................................................ 112
3.1.5
Pin input voltage .................................................................................................................................. 112
3.1.6
Power supply scheme ........................................................................................................................... 114
3.1.7
Current consumption measurement ..................................................................................................... 115
ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 116
RECOMMENDED OPERATING CONDITIONS FOR MAIN SYSTEM ..................................................................... 118
3.3.1
General operating conditions .............................................................................................................. 118
3.3.2
VCAP external capacitor ..................................................................................................................... 121
3.3.3
SMPS step-down converter .................................................................................................................. 121
3.3.4
Operating conditions at power-up / power-down ................................................................................ 123
3.3.5
Embedded reset and power control block characteristics ................................................................... 123
3.3.6
Embedded reference voltage ................................................................................................................ 125
3.3.7
Supply current characteristics ............................................................................................................. 125
3.3.8
Wakeup time from low-power modes ................................................................................................... 145
3.3.9
External clock source characteristics .................................................................................................. 146
3.3.10
Internet clock source characteristics ................................................................................................... 150
3.3.11
PLL characteristics .............................................................................................................................. 153
3.3.12
Memory characteristics........................................................................................................................ 155
3.3.13
EMC characteristics ............................................................................................................................ 156
3.3.14
Absolute maximum ratings (electrical sensitivity) ............................................................................... 157
3.3.15
I/O current injection characteristics .................................................................................................... 158
3.3.16
I/O port characteristics ........................................................................................................................ 159
3.3.17
NRST pin characteristics ..................................................................................................................... 166
3.3.18
FMC characteristics ............................................................................................................................ 167
3.3.19
Quad-SPI interface characteristics ...................................................................................................... 189
6
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
3.3.20
Delay block (DLYB) characteristics .................................................................................................... 191
3.3.21
16-bit ADC characteristics .................................................................................................................. 191
3.3.22
DAC characteristics ............................................................................................................................. 200
3.3.23
Voltage reference buffer characteristics .............................................................................................. 203
3.3.24
Temperature sensor characteristics ..................................................................................................... 204
3.3.25
Temperature and VBAT monitoring ....................................................................................................... 205
3.3.26
Voltage booster for analog switch ....................................................................................................... 205
3.3.27
Comparator characteristics ................................................................................................................. 206
3.3.28
Operational amplifier characteristics .................................................................................................. 207
3.3.29
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics .................................................. 209
3.3.30
Camera interface (DCMI) timing specifications .................................................................................. 211
3.3.31
LCD-TFT controller (LTDC) characteristics....................................................................................... 212
3.3.32
Timer characteristics ........................................................................................................................... 214
3.3.33
Communication interfaces ................................................................................................................... 214
ESC SUB-SYSTEM DC ELECTRICAL CHARACTERISTICS................................................................................ 232
3.4.1
Leakage Current and Capacitance ...................................................................................................... 232
3.4.2
DC Characteristics of 3.3V (with 5V Tolerant) I/O Pins ..................................................................... 232
ESC SUB-SYSTEM AC ELECTRICAL CHARACTERISTICS................................................................................ 233
3.5.1
Power-on Reset for VCCK ................................................................................................................... 233
3.5.2
Ethernet PHY Electrical Characteristics ............................................................................................. 234
POWER CONSUMPTION.................................................................................................................................. 235
3.6.1
Main System ......................................................................................................................................... 235
3.6.2
ESC Sub-system ................................................................................................................................... 235
3.6.3
Package Thermal Characteristics ........................................................................................................ 235
ESC SUB-SYSTEM POWER–UP SEQUENCE..................................................................................................... 236
ESC SUB-SYSTEM AC TIMING CHARACTERISTICS ....................................................................................... 237
3.8.1
ESC I2C Timing ................................................................................................................................... 237
3.8.2
ESC Port 2 MII Timing ........................................................................................................................ 239
3.8.3
Distributed Clocks SYNC/LATCH ........................................................................................................ 242
3.8.4
ESC Digital I/O Timing ........................................................................................................................ 243
3.8.5
ESC PDI SPI Slave Timing .................................................................................................................. 245
3.8.6
Function SPI Slave Timing................................................................................................................... 250
3.8.7
PWM Motor Controller Timing ........................................................................................................... 251
3.8.8
Incremental and Hall Encoder Interface Timing ................................................................................. 254
3.8.9
ESC SPI Master Timing ....................................................................................................................... 256
4
PACKAGE INFORMATION ........................................................................................................................... 259
5
ORDERING INFORMATION ......................................................................................................................... 260
6
REVISION HISTORY ...................................................................................................................................... 260
7
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
List of Figures
FIGURE 1.2-1: AX58400 BLOCK DIAGRAM .................................................................................................................... 17
FIGURE 1.3-1: AX58400 PINOUT DIAGRAM ................................................................................................................... 18
FIGURE 2.3-1: ST ART™ ACCELERATOR SCHEMATIC AND ENVIRONMENT .................................................................... 62
FIGURE 2.5-1: POWER-UP/POWER-DOWN SEQUENCE....................................................................................................... 64
FIGURE 2.9-1: AX58400 BUS MATRIX ............................................................................................................................ 68
FIGURE 2.45-1: ESC SUB-SYSTEM BLOCK DIAGRAM ..................................................................................................... 92
FIGURE 3.1-1: PIN LOADING CONDITIONS ..................................................................................................................... 112
FIGURE 3.1-2: PIN INPUT VOLTAGE ............................................................................................................................... 113
FIGURE 3.1-3: POWER SUPPLY SCHEME......................................................................................................................... 114
FIGURE 3.1-4: CURRENT CONSUMPTION MEASUREMENT SCHEME................................................................................. 115
FIGURE 3.3-1: EXTERNAL CAPACITOR CEXT .................................................................................................................. 121
FIGURE 3.3-2: EXTERNAL COMPONENTS FOR SMPS STEP-DOWN CONVERTER.............................................................. 121
FIGURE 3.3-3: TYPICAL SMPS EFFICIENCY (%) VS LOAD CURRENT (A) IN RUN MODE AT TJ = 30 °C ........................... 137
FIGURE 3.3-4: TYPICAL SMPS EFFICIENCY (%) VS LOAD CURRENT (A) IN RUN MODE AT TJ = TJMAX ............................ 137
FIGURE 3.3-5: TYPICAL SMPS EFFICIENCY (%) VS LOAD CURRENT (A) IN LOW-POWER MODE AT TJ = 30 °C .............. 138
FIGURE 3.3-6: TYPICAL SMPS EFFICIENCY (%) VS LOAD CURRENT (A) IN LOW-POWER MODE AT TJ = TJMAX ............... 138
FIGURE 3.3-7: HIGH-SPEED EXTERNAL CLOCK SOURCE AC TIMING DIAGRAM .............................................................. 146
FIGURE 3.3-8: LOW-SPEED EXTERNAL CLOCK SOURCE AC TIMING DIAGRAM ............................................................... 147
FIGURE 3.3-9: TYPICAL APPLICATION WITH AN 8 MHZ CRYSTAL ................................................................................. 149
FIGURE 3.3-10: TYPICAL APPLICATION WITH A 32.768 KHZ CRYSTAL ......................................................................... 150
FIGURE 3.3-11: VIL/VIH FOR ALL I/OS EXCEPT BOOT0 ................................................................................................ 160
FIGURE 3.3-12: RECOMMENDED NRST PIN PROTECTION.............................................................................................. 166
FIGURE 3.3-13: ASYNCHRONOUS NON-MULTIPLEXED SRAM/PSRAM/NOR READ WAVEFORMS ................................ 168
FIGURE 3.3-14: ASYNCHRONOUS NON-MULTIPLEXED SRAM/PSRAM/NOR WRITE WAVEFORMS .............................. 170
FIGURE 3.3-15: ASYNCHRONOUS MULTIPLEXED PSRAM/NOR READ WAVEFORMS .................................................... 172
FIGURE 3.3-16: SYNCHRONOUS MULTIPLEXED NOR/PSRAM READ TIMINGS .............................................................. 175
FIGURE 3.3-17: SYNCHRONOUS MULTIPLEXED PSRAM WRITE TIMINGS ...................................................................... 177
FIGURE 3.3-18: SYNCHRONOUS NON-MULTIPLEXED NOR/PSRAM READ TIMINGS ...................................................... 179
FIGURE 3.3-19: SYNCHRONOUS NON-MULTIPLEXED PSRAM WRITE TIMINGS .............................................................. 181
FIGURE 3.3-20: NAND CONTROLLER WAVEFORMS FOR READ ACCESS ......................................................................... 183
FIGURE 3.3-21: NAND CONTROLLER WAVEFORMS FOR WRITE ACCESS ....................................................................... 183
FIGURE 3.3-22: NAND CONTROLLER WAVEFORMS FOR COMMON MEMORY READ ACCESS .......................................... 184
FIGURE 3.3-23: NAND CONTROLLER WAVEFORMS FOR COMMON MEMORY WRITE ACCESS ......................................... 184
FIGURE 3.3-24: SDRAM READ ACCESS WAVEFORMS (CL = 1)..................................................................................... 186
FIGURE 3.3-25: SDRAM WRITE ACCESS WAVEFORMS.................................................................................................. 187
FIGURE 3.3-26: QUAD-SPI TIMING DIAGRAM - SDR MODE........................................................................................... 190
FIGURE 3.3-27: QUAD-SPI TIMING DIAGRAM - DDR MODE .......................................................................................... 191
FIGURE 3.3-28: ADC ACCURACY CHARACTERISTICS (12-BITRESOLUTION) .................................................................. 198
FIGURE 3.3-29: TYPICAL CONNECTION DIAGRAM USING THE ADC .............................................................................. 198
FIGURE 3.3-30: POWER SUPPLY AND REFERENCE DECOUPLING (VREF+ NOT CONNECTED TO VDDA) .............................. 199
FIGURE 3.3-31: POWER SUPPLY AND REFERENCE DECOUPLING (VREF+ CONNECTED TO VDDA) ...................................... 199
FIGURE 3.3-32: 12-BIT BUFFERED /NON-BUFFERED DAC ............................................................................................. 203
FIGURE 3.3-33: CHANNEL TRANSCEIVER TIMING DIAGRAMS ........................................................................................ 210
FIGURE 3.3-34: DCMI TIMING DIAGRAM ...................................................................................................................... 211
FIGURE 3.3-35: LCD-TFT HORIZONTAL TIMING DIAGRAM........................................................................................... 213
FIGURE 3.3-36: LCD-TFT VERTICAL TIMING DIAGRAM ............................................................................................... 213
FIGURE 3.3-37: USART TIMING DIAGRAM IN MASTER MODE ...................................................................................... 216
FIGURE 3.3-38: USART TIMING DIAGRAM IN SLAVE MODE ......................................................................................... 217
FIGURE 3.3-39: SPI TIMING DIAGRAM - SLAVE MODE AND CPHA = 0 .......................................................................... 218
FIGURE 3.3-40: SPI TIMING DIAGRAM - SLAVE MODE AND CPHA = 1(1) ....................................................................... 219
FIGURE 3.3-41: SPI TIMING DIAGRAM - MASTER MODE(1) ............................................................................................. 219
FIGURE 3.3-42: I2S SLAVE TIMING DIAGRAM (PHILIPS PROTOCOL)(1) ............................................................................ 221
FIGURE 3.3-43: I2S MASTER TIMING DIAGRAM (PHILIPS PROTOCOL)(1).......................................................................... 221
FIGURE 3.3-44: SAI MASTER TIMING WAVEFORMS ....................................................................................................... 223
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AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
FIGURE 3.3-45: SAI SLAVE TIMING WAVEFORMS.......................................................................................................... 223
FIGURE 3.3-46: MDIO SLAVE TIMING DIAGRAM .......................................................................................................... 224
FIGURE 3.3-47: SDIO HIGH-SPEED MODE ..................................................................................................................... 226
FIGURE 3.3-48: SD DEFAULT MODE .............................................................................................................................. 226
FIGURE 3.3-49: DDR MODE .......................................................................................................................................... 226
FIGURE 3.3-50: ULPI TIMING DIAGRAM ....................................................................................................................... 227
FIGURE 3.3-51: ETHERNET SMI TIMING DIAGRAM ....................................................................................................... 228
FIGURE 3.3-52: ETHERNET RMII TIMING DIAGRAM ...................................................................................................... 229
FIGURE 3.3-53: ETHERNET MII TIMING DIAGRAM ........................................................................................................ 230
FIGURE 3.3-54: JTAG TIMING DIAGRAM ...................................................................................................................... 231
FIGURE 3.3-55: SWD TIMING DIAGRAM ....................................................................................................................... 231
FIGURE 3.5-1: POWER ON RESET (POR) TIMING DIAGRAM ......................................................................................... 233
FIGURE 3.7-1: POWER-UP SEQUENCE TIMING DIAGRAM .............................................................................................. 236
FIGURE 3.8-1: WRITE ACCESS (1 ADDRESS BYTE, UP TO 16 KBIT EEPROMS) .............................................................. 237
FIGURE 3.8-2: WRITE ACCESS (2 ADDRESS BYTES, 32 KBIT - 4 MBIT EEPROMS) ........................................................ 237
FIGURE 3.8-3: READ ACCESS (1 ADDRESS BYTE, UP TO 16 KBIT EEPROMS)................................................................ 238
FIGURE 3.8-4: PORT 2 MII TX TIMING DIAGRAM ......................................................................................................... 239
FIGURE 3.8-5: PORT 2 MII RX TIMING DIAGRAM ........................................................................................................ 240
FIGURE 3.8-6: MDC/MDIO WRITE ACCESS ................................................................................................................. 241
FIGURE 3.8-7: MDC/MDIO READ ACCESS ................................................................................................................... 241
FIGURE 3.8-8: LATCH TIMING ..................................................................................................................................... 242
FIGURE 3.8-9: SYNC TIMING ....................................................................................................................................... 242
FIGURE 3.8-10: DIGITAL INPUT: INPUT DATA SAMPLED AT SOF, IO CAN BE READ IN THE SAME FRAME ...................... 243
FIGURE 3.8-11: DIGITAL INPUT: INPUT DATA SAMPLED WITH LATCH_IN .................................................................. 243
FIGURE 3.8-12: DIGITAL OUTPUT TIMING ..................................................................................................................... 243
FIGURE 3.8-13: OE_EXT TIMING ................................................................................................................................. 243
FIGURE 3.8-14: BASIC MOSI/MISO TIMING ................................................................................................................ 245
FIGURE 3.8-15: PDI SPI SLAVE READ ACCESS (2 BYTE ADDRESSING, 1 BYTE READ DATA) WITH WAIT STATE BYTE ... 246
FIGURE 3.8-16: PDI SPI SLAVE READ ACCESS (2 BYTE ADDRESSING, 2 BYTE READ DATA) WITH WAIT STATE BYTE ... 247
FIGURE 3.8-17: PDI SPI SLAVE WRITE ACCESS (2 BYTE ADDRESSING, 1 BYTE WRITE DATA)........................................ 248
FIGURE 3.8-18: PDI SPI SLAVE WRITE ACCESS (3 BYTE ADDRESSING, 1 BYTE WRITE DATA)........................................ 249
FIGURE 3.8-19: FUNCTION SPI SLAVE WITH SHARE PIN TIMING DIAGRAM .................................................................. 250
FIGURE 3.8-20: FUNCTION SPI SLAVE WITH INDIVIDUAL PIN TIMING DIAGRAM .......................................................... 250
FIGURE 3.8-21: PWMX TIMING .................................................................................................................................... 251
FIGURE 3.8-22: ONLY PWM CHANNEL 2 SHIFT DIAGRAM ........................................................................................... 252
FIGURE 3.8-23: BBM (BREAK BEFORE MAKE) TIMING DIAGRAM ............................................................................... 253
FIGURE 3.8-24: ONE SHOT WITH MULTI STEP TIMING DIAGRAM .................................................................................. 253
FIGURE 3.8-25: ABZ TIMING DIAGRAM ....................................................................................................................... 254
FIGURE 3.8-26: CW/CCW TIMING DIAGRAM............................................................................................................... 254
FIGURE 3.8-27: CLK/DIR TIMING DIAGRAM ............................................................................................................... 254
FIGURE 3.8-28: HALL TIMING DIAGRAM ...................................................................................................................... 254
FIGURE 3.8-29: SPI MASTER TIMING ........................................................................................................................... 256
FIGURE 3.8-30: MMISO /MMOSIO TIMING ................................................................................................................ 256
FIGURE 3.8-31: SPI MDRLD READY TIMEOUT TIMING ............................................................................................... 257
FIGURE 3.8-32: SPI MTRG TRIGGER PULSE TIMEOUT ................................................................................................. 257
FIGURE 3.8-33: SPI MDRLD TRIGGER LDAC GAP AND WIDTH TIMING..................................................................... 257
9
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
List of Tables
TABLE 1.1-1: AX58400 FEATURES AND PERIPHERAL COUNTS ...................................................................................... 15
TABLE 1.4-1: LEGEND/ABBREVIATIONS USED IN THE PINOUT TABLE .............................................................................. 19
TABLE 1.4-2: PORT A ALTERNATE FUNCTIONS ................................................................................................................ 36
TABLE 2.6-1: SYSTEM VS DOMAIN LOW-POWER MODE ................................................................................................... 66
TABLE 2.23-1: DFSDM IMPLEMENTATION ..................................................................................................................... 75
TABLE 2.29-1: TIMER FEATURE COMPARISON ................................................................................................................ 78
TABLE 2.32-1: USART FEATURES .................................................................................................................................. 84
TABLE 2.45-1: ESC BOOTSTRAP PINS CONFIGURATION ................................................................................................. 93
TABLE 2.45-2: ESC I2C EEPROM LAYOUT ................................................................................................................... 96
TABLE 2.45-3: ESC MEMORY MAP .............................................................................................................................. 107
TABLE 2.45-4: ESC FUNCTION REGISTER MAP ............................................................................................................ 109
TABLE 2.45-5: ESC MEMORY AND FUNCTION REGISTERS MIRROR MAPPING TABLE .................................................. 111
TABLE 3.2-1: VOLTAGE CHARACTERISTICS(1) ............................................................................................................... 116
TABLE 3.2-2: CURRENT CHARACTERISTICS .................................................................................................................. 117
TABLE 3.2-3: THERMAL CHARACTERISTICS .................................................................................................................. 117
TABLE 3.3-1: GENERAL OPERATING CONDITIONS ......................................................................................................... 119
TABLE 3.3-2: SUPPLY VOLTAGE AND MAXIMUM FREQUENCY CONFIGURATION ............................................................ 120
TABLE 3.3-3: VCAP OPERATING CONDITIONS(1) ........................................................................................................... 121
TABLE 3.3-4: CHARACTERISTICS OF SMPS STEP-DOWN CONVERTER EXTERNAL COMPONENTS ................................... 122
TABLE 3.3-5: SMPS STEP-DOWN CONVERTER CHARACTERISTICS FOR EXTERNAL USAGE ............................................ 122
TABLE 3.3-6: OPERATING CONDITIONS AT POWER-UP / POWER-DOWN (REGULATOR ON) ............................................ 123
TABLE 3.3-7: RESET AND POWER CONTROL BLOCK CHARACTERISTICS ......................................................................... 124
TABLE 3.3-8: EMBEDDED REFERENCE VOLTAGE ........................................................................................................... 125
TABLE 3.3-9: INTERNAL REFERENCE VOLTAGE CALIBRATION VALUES ......................................................................... 125
TABLE 3.3-10: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN RUN MODE, CODE WITH DATA PROCESSING
RUNNING FROM ITCM FOR CORTEX-M7 CORE, AND FLASH MEMORY FOR CORTEX-M4(ART ACCELERATOR ON),
LDO REGULATOR ON(1)(2)..................................................................................................................................... 126
TABLE 3.3-11: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN RUN MODE, CODE WITH DATA PROCESSING
RUNNING FROM ITCM FOR ARM CORTEX-M7 AND FLASH MEMORY FOR ARM CORTEX-M4, ART ACCELERATOR
ON, SMPS REGULATOR(1)..................................................................................................................................... 126
TABLE 3.3-12: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN RUN MODE, CODE WITH DATA PROCESSING
RUNNING FROM FLASH MEMORY, BOTH CORES RUNNING, CACHE ON, ART ACCELERATOR ON, LDO REGULATOR
ON(1) .................................................................................................................................................................... 127
TABLE 3.3-13: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN RUN MODE, CODE WITH DATA PROCESSING
RUNNING FROM FLASH MEMORY, BOTH CORES RUNNING, CACHE OFF, ART ACCELERATOR OFF, LDO REGULATOR
ON(1) .................................................................................................................................................................... 127
TABLE 3.3-14: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN RUN MODE, CODE WITH DATA PROCESSING
RUNNING FROM ITCM, ONLY ARM CORTEX-M7 RUNNING, LDO REGULATOR ON(1)(2) ........................................ 128
TABLE 3.3-15: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN RUN MODE, CODE WITH DATA PROCESSING
RUNNING FROM ITCM, ONLY ARM CORTEX-M7 RUNNING, SMPS REGULATOR(1)(2)............................................. 129
TABLE 3.3-16: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN RUN MODE, CODE WITH DATA PROCESSING
RUNNING FROM FLASH MEMORY, ONLY ARM CORTEX-M7 RUNNING, CACHE ON, LDO REGULATOR ON(1) ........ 129
TABLE 3.3-17: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN RUN MODE, CODE WITH DATA PROCESSING
RUNNING FROM FLASH MEMORY, ONLY ARM CORTEX-M7 RUNNING, CACHE OFF, LDO REGULATOR ON(1) ....... 130
TABLE 3.3-18: TYPICAL AND MAXIMUM CURRENT CONSUMPTION BATCH ACQUISITION MODE, LDO REGULATOR ON 130
TABLE 3.3-19: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN RUN MODE, CODE WITH DATA PROCESSING
RUNNING FROM FLASH MEMORY, ONLY ARM CORTEX-M4 RUNNING, ART ACCELERATOR ON, LDO REGULATOR
ON(1) .................................................................................................................................................................... 131
TABLE 3.3-20: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN RUN MODE, CODE WITH DATA PROCESSING
RUNNING FROM FLASH BANK 2, ONLY ARM CORTEX-M4 RUNNING, ART ACCELERATOR ON, SMPS
REGULATOR(1)(2) .................................................................................................................................................... 131
TABLE 3.3-21: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN STOP, LDO REGULATOR ON(1)(2) ........................ 132
TABLE 3.3-22: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN STOP, SMPS REGULATOR(1) ............................... 133
TABLE 3.3-23: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN SLEEP MODE, LDO REGULATOR ON(1)(2) ............ 134
10
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
TABLE 3.3-24: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN SLEEP MODE, SMPS REGULATOR(1)(2)(3).............. 135
TABLE 3.3-25: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN STANDBY ........................................................... 135
TABLE 3.3-26: TYPICAL AND MAXIMUM CURRENT CONSUMPTION IN VBAT MODE ........................................................ 136
TABLE 3.3-27: PERIPHERAL CURRENT CONSUMPTION IN RUN MODE ............................................................................ 140
TABLE 3.3-28: LOW-POWER MODE WAKEUP TIMINGS(1) ................................................................................................ 145
TABLE 3.3-29: HIGH-SPEED EXTERNAL USER CLOCK CHARACTERISTICS(1) ................................................................... 146
TABLE 3.3-30: LOW-SPEED EXTERNAL USER CLOCK CHARACTERISTICS(1) .................................................................... 147
TABLE 3.3-31: 4-48 MHZ HSE OSCILLATOR CHARACTERISTICS(1)................................................................................ 148
TABLE 3.3-32: LOW-SPEED EXTERNAL USER CLOCK CHARACTERISTICS(1) .................................................................... 149
TABLE 3.3-33: HSI48 OSCILLATOR CHARACTERISTICS ................................................................................................. 150
TABLE 3.3-34: HSI OSCILLATOR CHARACTERISTICS(1) .................................................................................................. 151
TABLE 3.3-35: CSI OSCILLATOR CHARACTERISTICS(1) .................................................................................................. 151
TABLE 3.3-36: LSI OSCILLATOR CHARACTERISTICS ..................................................................................................... 152
TABLE 3.3-37: PLL CHARACTERISTICS (WIDE VCO FREQUENCY RANGE)(1) ................................................................. 153
TABLE 3.3-38: PLL CHARACTERISTICS (MEDIUM VCO FREQUENCY RANGE)(1) ............................................................ 154
TABLE 3.3-39: FLASH MEMORY CHARACTERISTICS ...................................................................................................... 155
TABLE 3.3-40: FLASH MEMORY PROGRAMMING (SINGLE BANK CONFIGURATION NDBANK=1) .................................. 155
TABLE 3.3-41: FLASH MEMORY ENDURANCE AND DATA RETENTION ............................................................................ 155
TABLE 3.3-42: EMS CHARACTERISTICS ........................................................................................................................ 156
TABLE 3.3-43: EMI CHARACTERISTICS......................................................................................................................... 157
TABLE 3.3-44: ESD ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 157
TABLE 3.3-45: ELECTRICAL SENSITIVITIES ................................................................................................................... 158
TABLE 3.3-46: I/O CURRENT INJECTION SUSCEPTIBILITY(1) ........................................................................................... 158
TABLE 3.3-47: I/O STATIC CHARACTERISTICS ............................................................................................................... 159
TABLE 3.3-48: OUTPUT VOLTAGE CHARACTERISTICS FOR ALL I/OS EXCEPT PC13, PC14, PC15 AND PI8(1)................. 161
TABLE 3.3-49: OUTPUT VOLTAGE CHARACTERISTICS FOR PC13, PC14, PC15 AND PI8(1) ............................................ 162
TABLE 3.3-50: OUTPUT TIMING CHARACTERISTICS (HSLV OFF)(1)(2)........................................................................... 164
TABLE 3.3-51: OUTPUT TIMING CHARACTERISTICS (HSLV ON)(1) ............................................................................... 165
TABLE 3.3-52: NRST PIN CHARACTERISTICS ................................................................................................................ 166
TABLE 3.3-53: ASYNCHRONOUS NON-MULTIPLEXED SRAM/PSRAM/NOR READ TIMINGS(1) ..................................... 169
TABLE 3.3-54: ASYNCHRONOUS NON-MULTIPLEXED SRAM/PSRAM/NOR READ-NWAIT TIMINGS(1)(2).................... 169
TABLE 3.3-55: ASYNCHRONOUS NON-MULTIPLEXED SRAM/PSRAM/NOR WRITE TIMINGS(1) .................................... 171
TABLE 3.3-56: ASYNCHRONOUS NON-MULTIPLEXED SRAM/PSRAM/NOR WRITE-NWAIT TIMINGS(1)(2) .................. 171
TABLE 3.3-57: ASYNCHRONOUS MULTIPLEXED PSRAM/NOR READ TIMINGS(1) .......................................................... 173
TABLE 3.3-58: ASYNCHRONOUS MULTIPLEXED PSRAM/NOR READ-NWAIT TIMINGS(1)(2) ........................................ 173
TABLE 3.3-59: ASYNCHRONOUS MULTIPLEXED PSRAM/NOR WRITE TIMINGS(1) ........................................................ 174
TABLE 3.3-60: ASYNCHRONOUS MULTIPLEXED PSRAM/NOR WRITE-NWAIT TIMINGS(1)(2) ....................................... 174
TABLE 3.3-61: SYNCHRONOUS MULTIPLEXED NOR/PSRAM READ TIMINGS(1) ............................................................ 176
TABLE 3.3-62: SYNCHRONOUS MULTIPLEXED PSRAM WRITE TIMINGS(1) .................................................................... 178
TABLE 3.3-63: SYNCHRONOUS NON-MULTIPLEXED NOR/PSRAM READ TIMINGS(1) .................................................... 180
TABLE 3.3-64: SYNCHRONOUS NON-MULTIPLEXED PSRAM WRITE TIMINGS(1) ............................................................ 182
TABLE 3.3-65: SWITCHING CHARACTERISTICS FOR NAND FLASH READ CYCLES(1)...................................................... 185
TABLE 3.3-66: SWITCHING CHARACTERISTICS FOR NAND FLASH WRITE CYCLES(1) .................................................... 185
TABLE 3.3-67: SDRAM READ TIMINGS(1) ..................................................................................................................... 186
TABLE 3.3-68: LPSDR SDRAM READ TIMINGS(1) ........................................................................................................ 187
TABLE 3.3-69: SDRAM WRITE TIMINGS(1) ................................................................................................................... 188
TABLE 3.3-70: LPSDR SDRAM WRITE TIMINGS(1) ...................................................................................................... 188
TABLE 3.3-71: QUADSPI CHARACTERISTICS IN SDR MODE(1) ..................................................................................... 189
TABLE 3.3-72: QUADSPI CHARACTERISTICS IN DDR MODE(1) .................................................................................... 190
TABLE 3.3-73: DELAY BLOCK CHARACTERISTICS ........................................................................................................ 191
TABLE 3.3-74: ADC CHARACTERISTICS(1)(2) ................................................................................................................. 191
TABLE 3.3-75: MINIMUM SAMPLING TIME VS RAIN(1)(2) ................................................................................................. 195
TABLE 3.3-76: ADC ACCURACY(1)(2) ............................................................................................................................. 197
TABLE 3.3-77: DAC CHARACTERISTICS(1)(2) ................................................................................................................. 201
TABLE 3.3-78: DAC ACCURACY(1) ................................................................................................................................ 202
TABLE 3.3-79: VREFBUF CHARACTERISTICS(1) ........................................................................................................... 204
TABLE 3.3-80: TEMPERATURE SENSOR CHARACTERISTICS ........................................................................................... 204
TABLE 3.3-81: TEMPERATURE SENSOR CALIBRATION VALUES ..................................................................................... 205
11
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
TABLE 3.3-82: VBAT MONITORING CHARACTERISTICS................................................................................................... 205
TABLE 3.3-83: VBAT CHARGING CHARACTERISTICS....................................................................................................... 205
TABLE 3.3-84: TEMPERATURE MONITORING CHARACTERISTICS ................................................................................... 205
TABLE 3.3-85: VOLTAGE BOOSTER FOR ANALOG SWITCH CHARACTERISTICS(1) ............................................................ 205
TABLE 3.3-86: COMP CHARACTERISTICS(1).................................................................................................................. 206
TABLE 3.3-87: OPERATIONAL AMPLIFIER CHARACTERISTICS ....................................................................................... 208
TABLE 3.3-88: DFSDM MEASURED TIMING 1.62-3.6 V................................................................................................ 210
TABLE 3.3-89: DCMI CHARACTERISTICS(1) .................................................................................................................. 211
TABLE 3.3-90: LTDC CHARACTERISTICS(1) .................................................................................................................. 212
TABLE 3.3-91: TIMX CHARACTERISTICS(1)(2) ................................................................................................................ 214
TABLE 3.3-92: MINIMUM I2C_KER_CK FREQUENCY IN ALL I2C MODES ........................................................................ 214
TABLE 3.3-93: I2C ANALOG FILTER CHARACTERISTICS(1) .............................................................................................. 215
TABLE 3.3-94: USART CHARACTERISTICS(1) ................................................................................................................ 216
TABLE 3.3-95: SPI CHARACTERISTICS(1) ....................................................................................................................... 218
TABLE 3.3-96: I2S DYNAMIC CHARACTERISTICS(1) ........................................................................................................ 220
TABLE 3.3-97: SAI CHARACTERISTICS(1) ...................................................................................................................... 222
TABLE 3.3-98: MDIO SLAVE TIMING PARAMETERS ..................................................................................................... 223
TABLE 3.3-99: DYNAMICS CHARACTERISTICS: SD / MMC CHARACTERISTICS, VDD=2.7 TO 3.6 V(1)(2) ......................... 225
TABLE 3.3-100: DYNAMICS CHARACTERISTICS: EMMC CHARACTERISTICS VDD=1.71V TO 1.9V(1)(2) ........................ 225
TABLE 3.3-101: DYNAMICS CHARACTERISTICS: USB ULPI(1) ...................................................................................... 227
TABLE 3.3-102: DYNAMICS CHARACTERISTICS: ETHERNET MAC SIGNALS FOR SMI (1) ............................................... 228
TABLE 3.3-103: DYNAMICS CHARACTERISTICS: ETHERNET MAC SIGNALS FOR RMII (1) ............................................. 228
TABLE 3.3-104: DYNAMICS CHARACTERISTICS: ETHERNET MAC SIGNALS FOR MII (1) ................................................ 229
TABLE 3.3-105: DYNAMICS JTAG CHARACTERISTICS .................................................................................................. 230
TABLE 3.3-106: DYNAMICS SWD CHARACTERISTICS: .................................................................................................. 231
TABLE 3.5-1: POWER ON RESET (POR) TIMING TABLE................................................................................................ 233
TABLE 3.6-1: POWER CONSUMPTION ............................................................................................................................ 235
TABLE 3.6-2: THERMAL CHARACTERISTICS ................................................................................................................. 235
TABLE 3.7-1: POWER-UP SEQUENCE TIMING TABLE..................................................................................................... 236
TABLE 3.8-1: I2C EEPROM TIMING TABLE ................................................................................................................. 238
TABLE 3.8-2: PORT 2 MII TX TIMING TABLE ............................................................................................................... 239
TABLE 3.8-3: PORT 2 MII RX TIMING TABLE ............................................................................................................... 240
TABLE 3.8-4: MDC/MDIO TIMING TABLE................................................................................................................... 241
TABLE 3.8-5: DC SYNC/LATCH TIMING CHARACTERISTICS ...................................................................................... 242
TABLE 3.8-6: DIGITAL I/O TIMING TABLE .................................................................................................................... 244
TABLE 3.8-7: PDI SPI SLAVE TIMING TABLE ............................................................................................................... 245
TABLE 3.8-8: FUNCTION SPI WITH SHARE PIN TIMING TABLE ...................................................................................... 250
TABLE 3.8-9: FUNCTION SPI WITH INDIVIDUAL PIN TIMING TABLE.............................................................................. 250
TABLE 3.8-10: PWMX TIMING TABLE ......................................................................................................................... 251
TABLE 3.8-11: PWMX SHIFT TIMING TABLE ............................................................................................................... 252
TABLE 3.8-12: PWMX BBM TIMING TABLE ................................................................................................................ 253
TABLE 3.8-13: STEP FUNCTION TIMING TABLE.............................................................................................................. 253
TABLE 3.8-14: INCREMENTAL AND HALL ENCODER TIMING TABLE ............................................................................ 255
TABLE 3.8-15: SPI MASTER TIMING TABLE ................................................................................................................. 258
12
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
1 Introduction
General Description
The AX58400 EtherCAT Slave Controller with Dual-Core MCU is a System-in-Package (SiP) product based on the
STM32H755 microcontroller from STMicroelectronics. AX58400 is equipped with STM32 Dual-core Arm® Cortex® M7 and Cortex® - M4 32-bit RISC cores. The Cortex® -M7 core operates at up to 480 MHz and the Cortex® - M4 core
at up to 240 MHz. Both cores feature a floating point unit (FPU) which supports Arm® single- and double-precision
(Cortex® -M7 core) operations and conversions (IEEE 754 compliant), including a full set of DSP instructions and a
memory protection unit (MPU) to enhance application security. The EtherCAT Slave Controller (ESC) with two
integrated Fast Ethernet PHYs which support 100Mbps full-duplex operation and HP Auto-MDIX. The AX58400
supports the CANopen (CoE), TFTP (FoE), Vender specific application (VoE), etc. standard EtherCAT protocols and
provides a cost-effective solution for industrial automation, motion/motor control, robotics, digital I/O control, sensors
data acquisition, etc. industrial fieldbus applications.
AX58400 incorporates high-speed embedded memories with a dual-bank Flash memory of 2 Mbytes, up to 1 Mbyte of
RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well
as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus
matrix and a multi-layer AXI interconnect supporting internal and external memory access.
AX58400 offers three ADCs, two DACs, two ultra-low power comparators, a low-power RTC, a high-resolution timer,
12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number
generator (RNG), and a cryptographic acceleration cell. The devices support four digital filters for external sigma-delta
modulators (DFSDM). They also feature standard and advanced communication interfaces.
• Standard peripherals
– Four I2Cs
– Four USARTs, four UARTs and one LPUART
– Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be
clocked by a dedicated internal audio PLL or by an external clock to allow synchronization.
– Four SAI serial audio interfaces
– One SPDIFRX interface
– One SWPMI (Single Wire Protocol Master Interface)
– Management Data Input/Output (MDIO) slaves
– Two SDMMC interfaces
– A USB OTG full-speed and a USB OTG high-speed interface with full-speed capability (with the ULPI)
– One FDCAN plus one TT-FDCAN interface
– An Ethernet interface
– ST Chrom-ART Accelerator™
– HDMI-CEC
• Advanced peripherals including
– A flexible memory control (FMC) interface
– A Quad-SPI Flash memory interface
– A camera interface for CMOS sensors
– An LCD-TFT display controller
– A JPEG hardware compressor/decompressor
Refer to Table 1.1-1: AX58400 Features and Peripheral Counts for the list of peripherals available in detail.
13
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
The AX58400’s ESC circuit also provides a three-channel PWM controller or a one-channel Step/Direction controller,
and an increment/hall encode interface for closed-loop motor control, a SPI master controller for data acquisition and
output, and an I/O watchdog for functional safety.
The AX58400, in 225LD EHS-TFBGA 13x13 mm, 0.8-mm pitch, supports the RoHS compliant package and industrial
grade operating temperature range from -40 to 85°C. For VDD power domain, supply voltage can drop down to 1.62 V
by using an external power supervisor (see Section 2.5.2: Power supply supervisor) and connecting the PDR_ON pin
to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on AX58400 to allow a greater power supply
choice. A comprehensive set of power-saving modes allows the design of low-power applications.
These features make AX58400 microcontrollers suitable for a wide range of the EtherCAT applications:
• Motor drive and application control
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
• Mobile applications, Internet of Things
• Field-Bus to EtherCAT converter
14
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Table 1.1-1: AX58400 Features and Peripheral Counts
Peripherals
AX58400
Flash memory
SRAM in Kbytes
TCM RAM in
Kbytes
2 Mbytes
SRAM mapped onto AXI bus
512
SRAM1 (D2 domain)
128
SRAM2 (D2 domain)
128
SRAM3 (D2 domain)
32
SRAM4 (D3 domain)
64
ITCM RAM (instruction)
64
DTCM RAM (data)
128
Backup SRAM (Kbytes)
4
FMC
Yes
General-purpose input/outputs
Timers
97
Quad-SPI
Yes
Ethernet
High-resolution
Yes
1
General-purpose
10
Advanced-control (PWM)
2
Basic
2
Low-power
5
Wakeup pins
4
2
Tamper pins
Random number generator
Yes
Cryptographic accelerator
Yes
SPI /
6/3(1)
I2S
I2C
4
4/4/
1
USART/ UART/
LPUART
SAI
4
SPDIFRX
4 inputs
SWPMI
Yes
MDIO
Yes
SDMMC
2
FDCAN/TT-FDCAN
1/1
USB OTG_FS
Yes
USB OTG_HS
Yes
Communication
interfaces
Camera interface
Yes
LCD-TFT
Yes
JPEG Codec
Yes
Chrom-ART Accelerator™ (DMA2D)
Yes
15
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Peripherals
AX58400
16-bit ADCs
Number of Direct channels
Number of Fast channels
Number of Slow channels
3
2
15
12-bit DAC
Yes
Number of channels
2
6
Comparators
2
Operational amplifiers
2
Digital filters for sigma delta modulator (DFSDM)
1
480 MHz(2)
400 MHz(3)
Maximum CPU frequency
300 MHz(4)
1.62 to 3.6 V(5)
Operating voltage (VDD)
Operating
temperatures
Ambient temperature
–40 up to +85 °C(6)
Junction temperature
–40 to + 125 °C
Package
225LD EHS-TFBGA
1.
The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
2.
The product junction temperature must be kept within the –40 to +105 °C range.
3.
The product junction temperature must be kept within the –40 to +125 °C range.
4.
Up to 300 MHz for STM32H755xxx3 sales types (extended industrial temperature range).
5.
VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 2.5.2: Power supply supervisor) and
connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector
enabled.
6.
Using appropriate cooling methods to guarantee that the maximum junction temperature (125 °C) is not exceeded, the maximum
ambient temperature (85°C) can be exceeded.
16
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Block Diagram
Figure 1.2-1: AX58400 Block Diagram
17
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pinout Diagram
1
A VDDLDO
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PE13
PE11
PE10
PE8
PF15
PF11
SCLK
PB1
SDA
PA7
PA4
PA3
VREF+
VSSA
A
VDDA
B
B
GND
PB10
PE15
PE14
PE12
PE9
PE7
PF14
PB2
PB0
PC4
PA5
RSTO
VREF-
C
VCAP
SCS_ESC
PB11
IO[24]
MOSI
VDD
VCC3IO
IO[23]
GND
VCCK
PDI_EMU
PA6
RSTn
PA2
D
PB12
PB13
PB14
SCS_FUNC
SINT
VDD
VCC3IO
IO[22]
GND
VCCK
SCL
PC5
PA1
PA0
E
PB15
PD8
PD9
PD10
IO[26]
VDD
VCC3IO
IO[21]
GND
VCCK
IO[4]
TEST
PC1
PC3_C
F
PD11
PD12
PD13
SYNC_
LATCH[0]
IO[25]
VDD
VCC3IO
GND
GND
VCCK
GND
NC
PC0
PF10
G
PD14
PD15
PG6
SYNC_
LATCH[1]
IO[2]
VDD
GND
GND
GND
GND
NRST
IO[19]
PF7
PF8
H
VDD33US
B
PG8
PG7
MISO
IO[27]
VDD
GND
GND
GND
GND
IO[17]
IO[18]
PF9
J
VDD50US
B
PC8
PC6
PC7
IO[28]
VDD
GND
GND
GND
VDD
IO[0]
IO[1]
PF6
GND
VLXSMPS J
K
PA10
PA8
PA9
PC9
IO[29]
VDD
VDD
GND
GND
VDD
IO[16]
PE5
PC13
VBAT
VSSSMPS K
L
PA12
PA11
PA13
IO[31]
IO[30]
PD6
PG11
PG12
P0_RSET_
BG
PB4
IO[20]
PE1
PE6
P0_ACT
PC15-OSC
L
32_OUT
M LED_RUN LED_ERR DONE
PA14
PA15
PG9
PG10
PG13
PG14
PB3
PB6
PE4
P1_ACT
PDR_ON
PC14-OSC
M
32_IN
N
VCAP
PC10
PC11
PD0
PD7
GND
GND
GND
GND
GND
PB5
PB9
PE0
PE2
PE3
N
P
GND
PC12
PD1
PD3
GND
P0_SD
P0_XSCI
BOOT0
PB8
GND
P
PD2
PD4
PD5
PB7
VCAP
2
3
4
13
14
EEP_
R VDDLDO
1
P1_TXON P1_RXIN
P1_SD
P0_TXON P0_RXIN
VCC33A P1_TXOP P1_RXIP VCC33A P0_TXOP P0_RXIP VCC33A P0_XSCO
5
6
7
8
9
10
Figure 1.3-1: AX58400 Pinout Diagram
18
11
12
GND_PLL C
VCC12A_
D
PLL
PC2_C
E
PH1F
OSC_OUT
PH0OSC_IN
G
VFBSMPS VDDSMPS H
VDDLDO R
15
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Signal Description
1.4.1 Main System Pin Description
Name
Abbreviation
Pin name
Pin type
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
ANA
Analog-only Input
FT
5 V tolerant I/O
TT
3.3 V tolerant I/O
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT and FT I/Os
I/O structure
I2C FM+ option
_a
analog option (supplied by VDDA)
_u
USB option (supplied by VDD33USB)
_h
High-speed low-voltage I/O
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset.
Notes
Pin functions
_f
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 1.4-1: Legend/abbreviations used in the pinout table
19
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
By ball definitions
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
-
N14
PE2
I/O
FT_h
-
TRACECLK, SAI1_CK1,
SPI4_SCK,
SAI1_MCLK_A,
SAI4_MCLK_A,
QUADSPI_BK1_IO2,
SAI4_CK1,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
N15
PE3
I/O
FT_h
-
TRACED0, TIM15_BKIN,
SAI1_SD_B,SAI4_SD_B,
FMC_A19, EVENTOUT
-
-
TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N,SPI4_NSS,
SAI1_FS_A, SAI4_FS_A,
SAI4_D2, FMC_A20,
DCMI_D4, LCD_B0,
EVENTOUT
-
-
TRACED2, SAI1_CK2,
DFSDM1_CKIN3,
TIM15_CH1,SPI4_MISO,
SAI1_SCK_A,
SAI4_SCK_A,SAI4_CK2,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
-
-
M12
K12
PE4
PE5
I/O
I/O
FT_h
FT_h
L13
PE6
I/O
FT_h
-
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
SAI2_MCLK_B,
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
K13
PC13
I/O
FT
-
EVENTOUT
RTC_TAMP1/RTC_
TS/WKUP2
M15
PC14-OSC32_IN
(OSC32_IN)(1)
I/O
FT
-
EVENTOUT
OSC32_IN
L15
PC15OSC32_OUT
(OSC32_OUT) (1)
I/O
FT
-
EVENTOUT
OSC32_OUT
J13
PF6
I/O
FT_ha
-
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
SAI4_SD_B,
ADC3_INN4,
ADC3_INP8
20
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
QUADSPI_BK1_IO3,
EVENTOUT
G13
G14
H13
PF7
PF8
PF9
I/O
I/O
I/O
FT_ha
FT_ha
FT_ha
-
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B,
UART7_TX,
SAI4_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_INP3
-
TIM16_CH1N,
SPI5_MISO,
SAI1_SCK_B,
UART7_RTS/UART7_DE,
SAI4_SCK_B,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_INN3,
ADC3_INP7
-
TIM17_CH1N,
SPI5_MOSI, SAI1_FS_B,
UART7_CTS,
SAI4_FS_B, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
ADC3_INP2
ADC3_INN2,
ADC3_INP6
F14
PF10
I/O
FT_ha
-
TIM16_BKIN, SAI1_D3,
QUADSPI_CLK,
SAI4_D3, DCMI_D11,
LCD_DE, EVENTOUT
G15
PH0-OSC_IN
(PH0)
I/O
FT
-
EVENTOUT
OSC_IN
F15
PH1-OSC_OUT
(PH1)
I/O
FT
-
EVENTOUT
OSC_OUT
G11
NRST
I/O
RST
-
-
-
-
DFSDM1_CKIN0,
DFSDM1_DATIN4,
SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_INP10
-
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO,
SAI1_SD_A,
SAI4_SD_A,
SDMMC2_CK, SAI4_D1,
ETH_MDC,
ADC123_INN10,
ADC123_INP11,
RTC_TAMP3/WK
UP5
F13
E13
PC0
PC1
I/O
I/O
FT_a
FT_ha
21
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
MDIOS_MDC,
EVENTOUT
E15
E14
D14
D13
PC2_C
PC3_C
PA0
PA1
ANA
ANA
I/O
I/O
TT_a
TT_a
FT_a
FT_ha
-
C1DSLEEP,
DFSDM1_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
EVENTOUT
ADC3_INN1,
ADC3_INP0
-
C1SLEEP,
DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SDO,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
ADC3_INP1
-
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
USART2_CTS/USART2_
NSS, UART4_TX,
SDMMC2_CMD,
SAI2_SD_B,
ETH_MII_CRS,
EVENTOUT
ADC1_INP16,
WKUP0
-
TIM2_CH2, TIM5_CH2,
LPTIM3_OUT,
TIM15_CH1N,
USART2_RTS/USART2_
DE, UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCLK_B,
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK,
LCD_R2, EVENTOUT
ADC1_INN16,
ADC1_INP17
ADC12_INP14,
WKUP1
ADC12_INP15
C14
PA2
I/O
FT_a
-
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT,
TIM15_CH1,
USART2_TX,
SAI2_SCK_B,
ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
A13
PA3
I/O
FT_ ha
-
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT,
TIM15_CH2,
22
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
USART2_RX, LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
A12
B12
C12
A11
PA4
PA5
PA6
PA7
I/O
I/O
I/O
I/O
TT_a
TT_ ha
FT_a
TT_a
-
D1PWREN, TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
SPI6_NSS,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
ADC12_INP18,
DAC1_OUT1
-
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
SPI6_SCK,
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC12_INN18,
ADC12_INP19,
DAC1_OUT2
-
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO, TIM13_CH1,
TIM8_BKIN_COMP12,
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC12_INP3
-
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
SPI6_MOSI, TIM14_CH1,
ETH_MII_RX_DV/ETH_R
MII_CRS_DV,
FMC_SDNWE,
EVENTOUT
ADC12_INN3,
ADC12_INP7,
OPAMP1_VINM
C2DSLEEP,
DFSDM1_CKIN2,
I2S1_MCK,
ADC12_INP4,
SPDIFRX1_IN3,
OPAMP1_VOUT,
ETH_MII_RXD0/ETH_R
COMP1_INM
MII_RXD0, FMC_SDNE0,
EVENTOUT
B11
PC4
I/O
TT_a
-
D12
PC5
I/O
TT_a
-
C2SLEEP, SAI1_D3,
DFSDM1_DATIN2,
SPDIFRX1_IN4,
23
ADC12_INN4,
ADC12_INP8,
OPAMP1_VINM
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
SAI4_D3,
ETH_MII_RXD1/ETH_R
MII_RXD1,
FMC_SDCKE0,
COMP1_OUT,
EVENTOUT
B10
A9
PB0
PB1
I/O
I/O
FT_a
TT_u
-
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
DFSDM1_CKOUT,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
LCD_G1, EVENTOUT
ADC12_INN5,
ADC12_INP9,
OPAMP1_VINP,
COMP1_INP
-
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN1,
LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
LCD_G0, EVENTOUT
ADC12_INP5,
COMP1_INM
COMP1_INP
B9
PB2
I/O
FT_ ha
-
RTC_OUT, SAI1_D1,
DFSDM1_CKIN1,
SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
SAI4_SD_A,
QUADSPI_CLK,
SAI4_D1, EVENTOUT
A7
PF11
I/O
FT_a
-
SPI5_MOSI, SAI2_SD_B,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
ADC1_INP2
B8
PF14
I/O
FT_fha
-
DFSDM1_CKIN6,
I2C4_SCL, FMC_A8,
EVENTOUT
ADC2_INN2,
ADC2_INP6
A6
PF15
I/O
FT_fh
-
I2C4_SDA, FMC_A9,
EVENTOUT
-
OPAMP2_VOUT,
COMP2_INM
OPAMP2_VINM
B7
PE7
I/O
TT_ha
-
TIM1_ETR,
DFSDM1_DATIN2,
UART7_RX,
QUADSPI_BK2_IO0,
FMC_D4/FMC_DA4,
EVENTOUT
A5
PE8
I/O
TT_ha
-
TIM1_CH1N,
DFSDM1_CKIN2,
UART7_TX,
QUADSPI_BK2_IO1,
24
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
FMC_D5/FMC_DA5,
COMP2_OUT,
EVENTOUT
B6
A4
A3
B5
A2
B4
PE9
PE10
PE11
PE12
PE13
PE14
I/O
I/O
I/O
I/O
I/O
I/O
TT_ha
FT_ha
FT_ha
FT_h
FT_h
FT_h
-
TIM1_CH1,
DFSDM1_CKOUT,
UART7_RTS/UART7_DE,
QUADSPI_BK2_IO2,
FMC_D6/FMC_DA6,
EVENTOUT
OPAMP2_VINP,
COMP2_INP
-
TIM1_CH2N,
DFSDM1_DATIN4,
UART7_CTS,
QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7,
EVENTOUT
COMP2_INM
-
TIM1_CH2,
DFSDM1_CKIN4,
SPI4_NSS, SAI2_SD_B,
FMC_D8/FMC_DA8,
LCD_G3, EVENTOUT
COMP2_INP
-
TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK, SAI2_SCK_B,
FMC_D9/FMC_DA9,
COMP1_OUT, LCD_B4,
EVENTOUT
-
-
TIM1_CH3,
DFSDM1_CKIN5,
SPI4_MISO, SAI2_FS_B,
FMC_D10/FMC_DA10,
COMP2_OUT, LCD_DE,
EVENTOUT
-
-
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B,
FMC_D11/FMC_DA11,
LCD_CLK, EVENTOUT
-
-
-
B3
PE15
I/O
FT_h
-
TIM1_BKIN,
FMC_D12/FMC_DA12,
TIM1_BKIN_COMP12/C
OMP_TIM1_BKIN,
LCD_R7, EVENTOUT
B2
PB10
I/O
FT_f
-
TIM2_CH3,
HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
25
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
DFSDM1_DATIN7,
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
C3
D1
D2
D3
PB11
PB12
PB13
PB14
I/O
I/O
I/O
I/O
FT_f
FT_u
FT_u
FT_u
-
TIM2_CH4,
HRTIM_SCIN,
LPTIM2_ETR, I2C2_SDA,
DFSDM1_CKIN7,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, LCD_G5,
EVENTOUT
-
-
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK,
FDCAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_R
MII_TXD0, OTG_HS_ID,
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT
-
-
TIM1_CH1N,
LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
USART3_CTS/USART3_
NSS, FDCAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_R
MII_TXD1, UART5_TX,
EVENTOUT
OTG_HS_VBUS
-
TIM1_CH2N,
TIM12_CH1,
TIM8_CH2N,
USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
USART3_RTS/USART3_
DE,
UART4_RTS/UART4_DE,
SDMMC2_D0,
OTG_HS_DM,
EVENTOUT
-
26
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
E1
E2
E3
E4
F1
F2
F3
Pin name
(function after
reset)
PB15
PD8
PD9
PD10
PD11
PD12
PD13
Pin
I/O
Notes
type structure
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT_u
FT_h
FT_h
FT_h
FT_h
FT_fh
FT_fh
Alternate functions
Additional functions
-
RTC_REFIN,
TIM1_CH3N,
TIM12_CH2,
TIM8_CH3N,
USART1_RX,
SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2,
UART4_CTS,
SDMMC2_D1,
OTG_HS_DP,
EVENTOUT
-
-
DFSDM1_CKIN3,
SAI3_SCK_B,
USART3_TX,
SPDIFRX1_IN2,
FMC_D13/FMC_DA13,
EVENTOUT
-
-
DFSDM1_DATIN3,
SAI3_SD_B,
USART3_RX,
FDCAN2_RXFD_MODE,
FMC_D14/FMC_DA14,
EVENTOUT
-
-
DFSDM1_CKOUT,
SAI3_FS_B,
USART3_CK,
FDCAN2_TXFD_MODE,
FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
-
-
LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS/USART3_
NSS,
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
-
-
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
USART3_RTS/USART3_
DE, QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT
-
-
LPTIM1_OUT,
TIM4_CH2, I2C4_SDA,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
-
27
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
EVENTOUT
G1
G2
G3
H3
H2
J3
J4
PD14
PD15
PG6
PG7
PG8
PC6
PC7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT_h
FT_h
FT_h
FT_h
FT_h
FT_h
FT_h
-
TIM4_CH3,
SAI3_MCLK_B,
UART8_CTS,
FMC_D0/FMC_DA0,
EVENTOUT
-
-
TIM4_CH4,
SAI3_MCLK_A,
UART8_RTS/UART8_DE,
FMC_D1/FMC_DA1,
EVENTOUT
-
-
TIM17_BKIN,
HRTIM_CHE1,
QUADSPI_BK1_NCS,
FMC_NE3, DCMI_D12,
LCD_R7, EVENTOUT
-
-
HRTIM_CHE2,
SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
-
TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6_
DE, SPDIFRX1_IN3,
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
-
-
HRTIM_CHA1,
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
I2S2_MCK, USART6_TX,
SDMMC1_D0DIR,
FMC_NWAIT,
SDMMC2_D6,
SDMMC1_D6, DCMI_D0,
LCD_HSYNC,
EVENTOUT
SWPMI_IO
-
TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
I2S3_MCK,
USART6_RX,
SDMMC1_D123DIR,
FMC_NE1,
SDMMC2_D7,
SWPMI_TX,
-
28
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
J2
K4
K2
K3
PC8
PC9
PA8
PA9
I/O
I/O
I/O
I/O
FT_h
FT_fh
FT_fha
FT_u
-
TRACED1,
HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
UART5_RTS/UART5_DE,
FMC_NE2/FMC_NCE,
SWPMI_RX,
SDMMC1_D0, DCMI_D2,
EVENTOUT
-
-
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
LCD_G3,
SWPMI_SUSPEND,
SDMMC1_D1, DCMI_D3,
LCD_B2, EVENTOUT
-
-
MCO1, TIM1_CH1,
HRTIM_CHB2,
TIM8_BKIN2, I2C3_SCL,
USART1_CK,
OTG_FS_SOF,
UART7_RX,
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
-
-
TIM1_CH2,
HRTIM_CHC1,
LPUART1_TX,
I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX,
FDCAN1_RXFD_MODE,
DCMI_D0, LCD_R5,
EVENTOUT
OTG_FS_VBUS
-
-
K1
PA10
I/O
FT_u
-
TIM1_CH3,
HRTIM_CHC2,
LPUART1_RX,
USART1_RX,
FDCAN1_TXFD_MODE,
OTG_FS_ID,
MDIOS_MDIO, LCD_B4,
DCMI_D1, LCD_B1,
EVENTOUT
L2
PA11
I/O
FT_u
-
TIM1_CH4,
29
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS,
UART4_RX,
USART1_CTS/USART1_
NSS, FDCAN1_RX,
OTG_FS_DM, LCD_R4,
EVENTOUT
L1
PA12
I/O
FT_u
-
TIM1_ETR,
HRTIM_CHD2,
LPUART1_RTS/LPUART
1_DE,
SPI2_SCK/I2S2_CK,
UART4_TX,
USART1_RTS/USART1_
DE, SAI2_FS_B,
FDCAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
L3
PA13(JTMS/
SWDIO)
I/O
FT
-
JTMS-SWDIO,
EVENTOUT
-
M4
PA14(JTCK/
SWCLK)
I/O
FT
-
JTCK-SWCLK,
EVENTOUT
-
-
JTDI,
TIM2_CH1/TIM2_ETR,
HRTIM_FLT1, CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
SPI6_NSS,
UART4_RTS/UART4_DE,
UART7_TX, EVENTOUT
-
-
HRTIM_EEV1,
DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX,
UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
-
-
HRTIM_FLT2,
DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
-
M5
N2
N3
PA15(JTDI)
PC10
PC11
I/O
I/O
I/O
FT
FT_ha
FT_h
30
-
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
EVENTOUT
P2
N4
P3
R2
P4
R3
R4
L6
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT_h
FT_h
FT_h
FT_h
FT_h
FT_h
FT_h
FT_h
-
TRACED3,
HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
USART3_CK,
UART5_TX,
SDMMC1_CK,
DCMI_D9, EVENTOUT
-
-
DFSDM1_CKIN6,
SAI3_SCK_A,
UART4_RX,
FDCAN1_RX,
FMC_D2/FMC_DA2,
EVENTOUT
-
-
DFSDM1_DATIN6,
SAI3_SD_A, UART4_TX,
FDCAN1_TX,
FMC_D3/FMC_DA3,
EVENTOUT
-
-
TRACED2, TIM3_ETR,
UART5_RX,
SDMMC1_CMD,
DCMI_D11, EVENTOUT
-
-
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_
NSS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
-
-
HRTIM_FLT3,
SAI3_FS_A,
USART2_RTS/USART2_
DE,
FDCAN1_RXFD_MODE,
FMC_NOE, EVENTOUT
-
-
HRTIM_EEV3,
USART2_TX,
FDCAN1_TXFD_MODE,
FMC_NWE, EVENTOUT
-
-
SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A,
USART2_RX,
-
31
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
SAI4_SD_A,
FDCAN2_RXFD_MODE,
SAI4_D1, SDMMC2_CK,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT
N5
M6
M7
L7
PD7
PG9
PG10
PG11
I/O
I/O
I/O
I/O
FT_h
FT_h
FT_h
FT_h
-
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
USART2_CK,
SPDIFRX1_IN1,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
-
-
SPI1_MISO/I2S1_SDI,
USART6_RX,
SPDIFRX1_IN4,
QUADSPI_BK2_IO2,
SAI2_FS_B,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
EVENTOUT
-
-
HRTIM_FLT5,
SPI1_NSS/I2S1_WS,
LCD_G3, SAI2_SD_B,
FMC_NE3, DCMI_D2,
LCD_B2, EVENTOUT
-
-
LPTIM1_IN2,
HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN1,
SDMMC2_D2,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
-
-
-
L8
PG12
I/O
FT_h
-
LPTIM1_IN1,
HRTIM_EEV5,
SPI6_MISO,
USART6_RTS/USART6_
DE, SPDIFRX1_IN2,
LCD_B4,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_NE4,
LCD_B1, EVENTOUT
M8
PG13
I/O
FT_h
-
TRACED0,LPTIM1_OUT,
HRTIM_EEV10,
SPI6_SCK,
USART6_CTS/USART6_
32
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
NSS,
ETH_MII_TXD0/ETH_R
MII_TXD0, FMC_A24,
LCD_R0, EVENTOUT
M9
M10
L10
N11
M11
PG14
PB3(JTDO/T
RACESWO)
PB4(NJTRST)
PB5
PB6
I/O
I/O
I/O
I/O
I/O
FT_h
FT
FT
FT
FT_f
-
TRACED1,
LPTIM1_ETR,
SPI6_MOSI,
USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
-
JTDO/TRACESWO,
TIM2_CH2,
HRTIM_FLT4,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SPI6_SCK,
SDMMC2_D2,
CRS_SYNC,
UART7_RX, EVENTOUT
-
-
NJTRST, TIM16_BKIN,
TIM3_CH1,
HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS,
SPI6_MISO,
SDMMC2_D3,
UART7_TX, EVENTOUT
-
-
TIM17_BKIN, TIM3_CH2,
HRTIM_EEV7,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI,
FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
-
-
TIM16_CH1N,
TIM4_CH1,
HRTIM_EEV8,
I2C1_SCL, CEC,
I2C4_SCL, USART1_TX,
-
33
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
LPUART1_TX,
FDCAN2_TX,
QUADSPI_BK1_NCS,
DFSDM1_DATIN5,
FMC_SDNE1, DCMI_D5,
UART5_TX, EVENTOUT
R13
PB7
I/O
FT_fa
-
TIM17_CH1N,
TIM4_CH2,
HRTIM_EEV9,
I2C1_SDA, I2C4_SDA,
USART1_RX,
LPUART1_RX,
FDCAN2_TXFD_MODE,
DFSDM1_CKIN5,
FMC_NL,
DCMI_VSYNC,
EVENTOUT
P13
BOOT0
I
B
-
-
VPP
-
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7,
I2C1_SCL, I2C4_SCL,
SDMMC1_CKIN,
UART4_RX,
FDCAN1_RX,
SDMMC2_D4,
ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
-
-
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
I2C4_SDA,
SDMMC1_CDIR,
UART4_TX,
FDCAN1_TX,
SDMMC2_D5,
I2C4_SMBA,
SDMMC1_D5, DCMI_D7,
LCD_B7, EVENTOUT
-
-
LPTIM1_ETR,
TIM4_ETR,
HRTIM_SCIN,
LPTIM2_ETR,
UART8_RX,
FDCAN1_RXFD_MODE,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
-
P14
N12
N13
PB8
PB9
PE0
I/O
I/O
I/O
FT_fh
FT_fh
FT_h
34
PVD_IN
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin
No
Pin name
(function after
reset)
Pin
I/O
Notes
type structure
Alternate functions
Additional functions
EVENTOUT
L12
PE1
I/O
FT_h
-
LPTIM1_IN2,
HRTIM_SCOUT,
UART8_TX,
FDCAN1_TXFD_MODE,
FMC_NBL1, DCMI_D3,
EVENTOUT
M14
PDR_ON
I
FT
-
-
-
-
1. When this ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is valid
for all resets except for power-on reset.
2. Pxy_C and Pxy balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register.
Refer to the product reference manual for a detailed description of the switch configuration bits.
3. There is a direct path between Pxy_C and Pxy balls, through an analog switch. Pxy alternate functions are available on Pxy_C
when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product reference
manual for a detailed description of the switch configuration bits.
35
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
By port functions
Table 1.4-2: Port A alternate functions
AF0
AF2
AF3
AF4
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
PA0
-
TIM2_CH1/
TIM2_ETR
TIM5_CH1
TIM8_ETR
TIM15_BKIN
-
-
PA1
-
TIM2_CH2
TIM5_CH2
LPTIM3_
OUT
TIM15_
CH1N
-
-
PA2
-
TIM2_CH3
TIM5_CH3
LPTIM4_
OUT
TIM15_CH1
-
-
USART2_
TX
SAI2_SCK
_B
-
PA3
-
TIM2_CH4
TIM5_CH4
LPTIM5_
OUT
TIM15_CH2
-
-
USART2_
RX
-
LCD_B2
PA4
D1PWR
EN
-
TIM5_ETR
-
-
SPI1_NSS/
I2S1_WS
USART2_
CK
SPI6_NSS
-
PA5
D2PWR
EN
TIM2_CH1/
TIM2_ETR
-
TIM8_
CH1N
-
SPI1_SCK/
I2S1_CK
-
-
SPI6_SCK
-
OTG_HS_
ULPI_CK
-
-
PA6
-
TIM1_BKIN
TIM3_CH1
TIM8_BKIN
-
SPI1_
MISO/I2S1
_SDI
-
-
SPI6_
MISO
TIM13_CH1
TIM8_BKIN
_COMP12
MDIOS_
MDC
TIM1_BKIN
_COMP12
PA7
-
TIM1_CH1N
TIM3_CH2
TIM8_
CH1N
-
SPI1_
MOSI/I2S1
_SDO
-
-
SPI6_
MOSI
TIM14_CH1
-
ETH_MII_RX
_DV/ETH_
RMII_CRS_DV
FMC_SDN
WE
PA8
MCO1
TIM1_CH1
HRTIM_
CHB2
TIM8_BKIN2
I2C3_SCL
-
-
USART1_
CK
-
-
TIM8_BKIN
2_COMP12
PA9
-
TIM1_CH2
HRTIM_
CHC1
LPUART1_TX
-
USART1_
TX
-
PA10
-
TIM1_CH3
HRTIM_
CHC2
LPUART1_
RX
-
-
USART1_
RX
-
PA11
-
TIM1_CH4
HRTIM_
CHD1
LPUART1_
CTS
-
Port A
Port
AF1
I2C3_SMBA
AF5
SPI2_SCK/
I2S2_CK
-
SPI2_NSS/
I2S2_WS
AF6
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI3_NSS/
I2S3_WS
UART4_RX
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
UART4_TX
SDMMC2_
CMD
SAI2_SD_B
ETH_MII_
CRS
-
-
-
EVENT
OUT
UART4_RX
QUADSPI_
BK1_IO3
SAI2_
MCLK_B
-
-
LCD_R2
EVENT
OUT
ETH_MDIO
MDIOS_
MDIO
-
LCD_R1
EVENT
OUT
ETH_MII_
COL
-
-
LCD_B5
EVENT
OUT
LCD_
VSYNC
EVENT
OUT
LCD_R4
EVENT
OUT
LCD_G2
EVENT
OUT
-
-
EVENT
OUT
LCD_B3
LCD_R6
EVENT
OUT
USART2_
CTS/
USART2_NSS
USART2_
RTS/
USART2_DE
USART1_
CTS/
USART1_NSS
36
-
FDCAN1_
RXFD_
MODE
FDCAN1_
TXFD_MODE
FDCAN1_
RX
OTG_HS_
ULPI_D0
-
OTG_FS_
SOF
ETH_MII_RX
_CLK/ETH_
RMII_REF_CLK
-
UART7_RX
OTG_HS_
SOF
DCMI_
HSYNC
DCMI_PIX
CLK
-
-
-
DCMI_D0
LCD_R5
EVENT
OUT
OTG_FS_ID
MDIOS_
MDIO
LCD_B4
DCMI_D1
LCD_B1
EVENT
OUT
-
-
-
LCD_R4
EVENT
OUT
OTG_FS_
DM
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
Port A
Port
AF1
AF2
AF3
AF4
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
FDCAN1_
TX
OTG_FS_
DP
-
-
-
LCD_R5
EVENT
OUT
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PA12
-
TIM1_ETR
HRTIM_
CHD2
LPUART1_
RTS/
LPUART1_DE
PA13
JTMSSWDIO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA14
JTCKSWCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA15
JTDI
TIM2_CH1/
TIM2_ETR
HRTIM_
FLT1
-
CEC
SPI6_NSS
UART4_
RTS/UART
4_DE
-
-
UART7_TX
-
-
-
EVENT
OUT
-
SPI1/2/3/4/
5/6/CEC
SPI2_SCK/
I2S2_CK
SPI1_NSS/
I2S1_WS
UART4_TX
SPI3_NSS/
I2S3_WS
USART1_
RTS/
USART1_DE
37
SAI2_FS_B
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF2
AF3
AF4
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
PB0
-
TIM1_CH2N
TIM3_CH3
-
-
PB1
-
TIM1_CH3N
TIM3_CH4
-
PB2
RTC_
OUT
-
SAI1_D1
PB3
JTDO/
TRACE
SWO
TIM2_CH2
PB4
NJTRST
TIM16_
BKIN
PB5
-
TIM17_
BKIN
PB6
-
PB7
-
PB8
-
PB9
Port
AF1
TIM8_CH3N
-
DFSDM1_
CKIN1
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
DFSDM1_
CKOUT
-
UART4_
CTS
LCD_R3
OTG_HS_
ULPI_D1
ETH_MII_RX
D2
-
-
LCD_G1
EVENT
OUT
-
DFSDM1_
DATIN1
-
-
LCD_R6
OTG_HS_
ULPI_D2
ETH_MII_RX
D3
-
-
LCD_G0
EVENT
OUT
-
SAI1_SD_A
QUADSPI_
CLK
SAI4_D1
-
-
-
-
EVENT
OUT
CRS_SYNC
UART7_RX
-
-
-
EVENT
OUT
-
UART7_TX
-
-
-
EVENT
OUT
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI3_
MOSI/I2S3
_SDO
SAI4_SD_A
-
SPI1_SCK/
I2S1_CK
SPI3_SCK/
I2S3_CK
TIM3_CH1
HRTIM_
EEV6
-
SPI1_
MISO/I2S1
_SDI
SPI3_MISO/
I2S3_SDI
SPI2_NSS/
I2S2_WS
SPI6_
MISO
SDMMC2_D3
TIM3_CH2
HRTIM_
EEV7
I2C1_SMBA
SPI1_
MOSI/I2S1
_SDO
I2C4_SMBA
SPI3_
MOSI/I2S3
_SDO
SPI6_
MOSI
FDCAN2_
RX
OTG_HS_
ULPI_D7
ETH_PPS_
OUT
FMC_SDCKE1
TIM4_CH1
HRTIM_
EEV8
I2C1_SCL
CEC
I2C4_SCL
USART1_
TX
LPUART1_TX
FDCAN2_
TX
QUADSPI_
BK1_NCS
DFSDM1_
DATIN5
FMC_SDNE1
TIM4_CH2
HRTIM_
EEV9
I2C1_SDA
-
I2C4_SDA
USART1_
RX
LPUART1_
RX
TIM16_CH1
TIM4_CH3
DFSDM1_
CKIN7
I2C1_SCL
-
I2C4_SCL
SDMMC1_
CKIN
-
TIM17_CH1
TIM4_CH4
DFSDM1_
DATIN7
I2C1_SDA
SPI2_NSS/
I2S2_WS
I2C4_SDA
PB10
-
TIM2_CH3
HRTIM_SC
OUT
LPTIM2_IN1
I2C2_SCL
SPI2_SCK/
I2S2_CK
PB11
-
TIM2_CH4
HRTIM_
SCIN
LPTIM2_
ETR
I2C2_SDA
PB12
-
TIM1_BKIN
-
-
I2C2_SMBA
PB13
-
TIM1_CH1N
-
LPTIM2_
OUT
Port B
-
TIM16_CH1N
TIM17_CH1N
HRTIM_
FLT4
TIM8_CH2N
AF5
-
-
SPI6_SCK
SDMMC2_D2
FDCAN2_
TXFD_
MODE
-
DFSDM1_
CKIN5
UART4_RX
FDCAN1_
RX
SDMMC2_
D4
ETH_MII_TX
D3
SDMMC1_
CDIR
UART4_TX
FDCAN1_
TX
SDMMC2_
D5
DFSDM1_
DATIN7
USART3_
TX
-
QUADSPI_
BK1_NCS
OTG_HS_
ULPI_D3
DFSDM1_
CKIN7
USART3_
RX
-
SPI2_NSS/
I2S2_WS
DFSDM1_
DATIN1
USART3_
CK
-
FDCAN2_
RX
OTG_HS_
ULPI_D5
ETH_MII_TX
D0/ETH_
RMII_TXD0
SPI2_SCK/
I2S2_CK
DFSDM1_
CKIN1
-
FDCAN2_
TX
OTG_HS_
ULPI_D6
ETH_MII_
TXD1/ETH_
RMII_TXD1
-
USART3_CTS/
USART3_NSS
38
-
OTG_HS_
ULPI_D4
DCMI_D10
UART5_
RX
EVENT
OUT
DCMI_D5
UART5_
TX
EVENT
OUT
DCMI_
VSYNC
-
EVENT
OUT
SDMMC1_
D4
DCMI_D6
LCD_B6
EVENT
OUT
I2C4_SMBA
SDMMC1_
D5
DCMI_D7
LCD_B7
EVENT
OUT
ETH_MII_RX
_ER
-
-
LCD_G4
EVENT
OUT
-
-
LCD_G5
EVENT
OUT
OTG_HS_ID
TIM1_BKIN
_COMP12
UART5_
RX
EVENT
OUT
-
-
UART5_
TX
EVENT
OUT
ETH_MII_TX
_EN/ETH_
RMII_TX_EN
FMC_NL
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
Port
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
-
TIM1_CH2N
AF2
AF3
AF4
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
TIM12_CH1
TIM8_CH2N
USART1_TX
SPI2_
MISO/I2S2
_SDI
TIM12_CH2
TIM8_CH3N
USART1_RX
SPI2_
MOSI/I2S2
_SDO
Port B
PB14
AF1
PB15
RTC_
REFIN
TIM1_CH3N
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
DFSDM1_
DATIN2
USART3_
RTS/USAR
T3_DE
UART4_
RTS/UART
4_DE
SDMMC2_
D0
-
-
OTG_HS_
DM
-
-
EVENT
OUT
DFSDM1_
CKIN2
-
-
-
OTG_HS_
DP
-
-
EVENT
OUT
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
UART4_
CTS
39
SDMMC2_D1
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
Port
PC0
PC1
PC2
PC3
PC4
Port C
PC5
AF1
AF2
AF3
AF4
AF5
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
-
-
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
DFSDM1_
DATIN4
-
SAI2_FS_B
-
SPI2_
MOSI/I2S2
_SDO
SAI1_SD_A
-
SAI4_SD_A
SDMMC2_
CK
DFSDM1_
CKOUT
-
-
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
-
-
-
DFSDM1_
CKIN0
-
SAI1_D1
DFSDM1_
DATIN0
-
-
DFSDM1_
CKIN1
-
SPI2_
MISO/I2S2
_SDI
-
-
DFSDM1_
DATIN1
-
SPI2_
MOSI/I2S2
_SDO
-
-
-
-
-
DFSDM1_
CKIN2
-
I2S1_MCK
-
-
-
SPDIFRX1_
IN3
-
ETH_MII_RX
D0/ETH_
RMII_RXD0
-
SAI1_D3
DFSDM1_
DATIN2
-
-
-
-
-
SPDIFRX1_
IN4
SAI4_D3
ETH_MII_RX
D1/ETH_
RMII_RXD1
TRACE
D0
C1DSLEEP
C1
SLEEP
C2
DSLEEP
C2
SLEEP
DFSDM1_
CKIN4
OTG_HS_
ULPI_STP
-
FMC_SDN
WE
-
LCD_R5
EVENT
OUT
SAI4_D1
ETH_MDC
MDIOS_
MDC
-
-
EVENT
OUT
-
OTG_HS_
ULPI_DIR
ETH_MII_TX
D2
-
-
EVENT
OUT
-
OTG_HS_
ULPI_NXT
-
-
EVENT
OUT
-
-
EVENT
OUT
COMP1_
OUT
-
EVENT
OUT
ETH_MII_TX
_CLK
FMC_SDNE0
FMC_SDCKE0
FMC_SDNE0
FMC_SDCKE0
PC6
-
HRTIM_CH
A1
TIM3_CH1
TIM8_CH1
DFSDM1_
CKIN3
I2S2_MCK
-
USART6_
TX
SDMMC1_
D0DIR
FMC_
NWAIT
SDMMC2_
D6
-
SDMMC1_
D6
DCMI_D0
LCD_
HSYNC
EVENT
OUT
PC7
TRGIO
HRTIM_CH
A2
TIM3_CH2
TIM8_CH2
DFSDM1_
DATIN3
-
I2S3_MCK
USART6_
RX
SDMMC1_
D123DIR
FMC_NE1
SDMMC2_
D7
SWPMI_TX
SDMMC1_
D7
DCMI_D1
LCD_G6
EVENT
OUT
HRTIM_CH
B1
TIM3_CH3
TIM8_CH3
-
-
-
USART6_
CK
UART5_
RTS/UART
5_DE
FMC_NE2/
FMC_NCE
-
SWPMI_RX
SDMMC1_
D0
DCMI_D2
-
EVENT
OUT
TIM3_CH4
TIM8_CH4
I2C3_SDA
I2S_CKIN
-
UART5_
CTS
QUADSPI_
BK1_IO0
LCD_G3
SWPMI_
SUSPEND
SDMMC1_
D1
DCMI_D3
LCD_B2
EVENT
OUT
PC8
TRACE
D1
PC9
MCO2
-
PC10
-
-
HRTIM_EE
V1
DFSDM1_
CKIN5
-
-
SPI3_SCK/I
2S3_CK
USART3_
TX
UART4_TX
QUADSPI_
BK1_IO1
-
-
SDMMC1_
D2
DCMI_D8
LCD_R2
EVENT
OUT
PC11
-
-
HRTIM_
FLT2
DFSDM1_
DATIN5
-
-
SPI3_MISO/
I2S3_SDI
USART3_
RX
UART4_RX
QUADSPI_
BK2_NCS
-
-
SDMMC1_
D3
DCMI_D4
-
EVENT
OUT
-
HRTIM_EE
V2
-
-
-
SPI3_MOSI/
I2S3_SDO
USART3_
CK
UART5_TX
-
-
-
SDMMC1_
CK
DCMI_D9
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC12
PC13
TRACE
D3
-
-
-
-
-
-
40
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF1
AF2
AF3
AF4
AF5
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
Port C
Port
41
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF2
AF3
AF4
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
PD0
-
-
-
DFSDM1_
CKIN6
-
-
PD1
-
-
-
DFSDM1_
DATIN6
-
-
-
TIM3_ETR
-
-
Port
Port D
PD2
TRACE
D2
AF1
-
DFSDM1_
CKOUT
-
AF5
SPI2_SCK/
I2S2_CK
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/6/
USART1/2/3/
6/UART7/SD
MMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
-
UART4_RX
FDCAN1_
RX
-
-
FMC_D2/
FMC_DA2
-
-
EVENT
OUT
SAI3_SD_A
-
UART4_TX
FDCAN1_
TX
-
-
FMC_D3/
FMC_DA3
-
-
EVENT
OUT
-
-
UART5_RX
-
-
-
SDMMC1_
CMD
DCMI_D11
-
EVENT
OUT
-
-
-
-
FMC_CLK
DCMI_D5
LCD_G7
EVENT
OUT
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SAI3_SCK_A
PD3
-
-
-
-
PD4
-
-
HRTIM_
FLT3
-
-
-
SAI3_FS_A
PD5
-
-
HRTIM_EE
V3
-
-
-
PD6
-
-
SAI1_D1
DFSDM1_
CKIN4
PD7
-
-
-
DFSDM1_
DATIN4
PD8
-
-
-
PD9
-
-
PD10
-
PD11
PD12
USART2_CTS/
USART2_NSS
USART2_
RTS/USART2
_DE
-
FDCAN1_
RXFD_
MODE
-
-
FMC_NOE
-
-
EVENT
OUT
-
USART2_
TX
-
FDCAN1_
TXFD_
MODE
-
-
FMC_NWE
-
-
EVENT
OUT
SPI3_
MOSI/I2S3
_SDO
SAI1_SD_A
USART2_
RX
SDMMC2_
CK
FMC_
NWAIT
DCMI_D10
LCD_B2
EVENT
OUT
-
SPI1_
MOSI/I2S1
_SDO
DFSDM1_
CKIN1
USART2_
CK
-
SPDIFRX1_
IN1
-
SDMMC2_
CMD
FMC_NE1
-
-
EVENT
OUT
DFSDM1_
CKIN3
-
-
SAI3_SCK_B
USART3_
TX
-
SPDIFRX1_
IN2
-
-
FMC_D13/
FMC_DA13
-
-
EVENT
OUT
-
DFSDM1_
DATIN3
-
-
SAI3_SD_B
USART3_
RX
-
FDCAN2_
RXFD_
MODE
-
-
FMC_D14/
FMC_DA14
-
-
EVENT
OUT
-
-
DFSDM1_
CKOUT
-
-
SAI3_FS_B
USART3_
CK
-
FDCAN2_
TXFD_
MODE
-
-
FMC_D15/
FMC_DA15
-
LCD_B3
EVENT
OUT
-
-
-
LPTIM2_
IN2
I2C4_SMBA
-
-
-
QUADSPI_
BK1_IO0
SAI2_SD_A
-
FMC_A16
-
-
EVENT
OUT
-
LPTIM1_IN1
TIM4_CH1
I2C4_SCL
-
-
-
QUADSPI_
BK1_IO1
SAI2_FS_A
-
FMC_A17
-
-
EVENT
OUT
LPTIM2_IN1
DFSDM1_
DATIN1
SAI4_SD_A
USART3_CTS/
USART3_NSS
USART3_
RTS/
USART3_
DE
42
FDCAN2_
RXFD_
MODE
SAI4_D1
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF2
AF3
AF4
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
PD13
-
LPTIM1_
OUT
TIM4_CH2
-
I2C4_SDA
PD14
-
-
TIM4_CH3
-
PD15
-
-
TIM4_CH4
-
Prot D
Port
AF1
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI2/3/6/
USART1/2/3/
6/UART7/SD
MMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
-
-
-
-
-
FMC_A18
-
-
EVENT
OUT
-
-
SAI3_MCLK
_B
-
-
-
SAI3_MCLK
_A
-
UART8_
CTS
UART8_RTS/
UART8_DE
43
QUADSPI_
BK1_IO3
SAI2_SCK_A
-
-
-
FMC_D0/
FMC_DA0
-
-
EVENT
OUT
-
-
-
FMC_D1/
FMC_DA1
-
-
EVENT
OUT
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF2
AF3
AF4
AF5
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
SAI2_
MCLK_A
-
FMC_NBL0
DCMI_D2
-
EVENT
OUT
-
FMC_NBL1
DCMI_D3
-
EVENT
OUT
FMC_A23
-
-
EVENT
OUT
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PE0
-
LPTIM1_
ETR
TIM4_ETR
HRTIM_
SCIN
LPTIM2_
ETR
-
-
-
UART8_RX
FDCAN1_
RXFD_
MODE
PE1
-
LPTIM1_IN2
-
HRTIM_
SCOUT
-
-
-
-
UART8_TX
FDCAN1_
TXFD_
MODE
-
SAI4_
MCLK_A
QUADSPI_
BK1_IO2
SAI4_CK1
Port
Port E
AF1
PE2
TRACE
CLK
-
SAI1_CK1
-
-
SPI4_SCK
SAI1_MCLK
_A
-
PE3
TRACE
D0
-
-
-
TIM15_BKIN
-
SAI1_SD_B
-
PE4
TRACE
D1
-
SAI1_D2
DFSDM1_
DATIN3
SPI4_NSS
SAI1_FS_A
-
PE5
TRACE
D2
-
SAI1_CK2
DFSDM1_
CKIN3
TIM15_CH1
SPI4_
MISO
SAI1_SCK_A
-
PE6
TRACE
D3
TIM15_CH2
SPI4_
MOSI
SAI1_SD_A
-
TIM1_BKIN2
SAI1_D1
-
TIM15_CH1N
SAI4_SD_B
ETH_MII_TX
D3
-
-
-
FMC_A19
-
-
EVENT
OUT
SAI4_FS_A
-
SAI4_D2
-
FMC_A20
DCMI_D4
LCD_B0
EVENT
OUT
SAI4_SCK
_A
-
SAI4_CK2
-
FMC_A21
DCMI_D6
LCD_G0
EVENT
OUT
FMC_A22
DCMI_D7
LCD_G1
EVENT
OUT
SAI4_SD_A
SAI4_D1
SAI2_
MCLK_B
TIM1_BKIN2
_COMP12
PE7
-
TIM1_ETR
-
DFSDM1_
DATIN2
-
-
-
UART7_RX
-
-
QUADSPI_
BK2_IO0
-
FMC_D4/
FMC_DA4
-
-
EVENT
OUT
PE8
-
TIM1_CH1N
-
DFSDM1_
CKIN2
-
-
-
UART7_TX
-
-
QUADSPI_
BK2_IO1
-
FMC_D5/
FMC_DA5
COMP2_
OUT
-
EVENT
OUT
PE9
-
TIM1_CH1
-
DFSDM1_
CKOUT
-
-
-
UART7_RTS/
UART7_DE
-
-
QUADSPI_
BK2_IO2
-
FMC_D6/
FMC_DA6
-
-
EVENT
OUT
PE10
-
TIM1_CH2N
-
DFSDM1_
DATIN4
-
-
-
UART7_
CTS
-
-
QUADSPI_
BK2_IO3
-
FMC_D7/
FMC_DA7
-
-
EVENT
OUT
PE11
-
TIM1_CH2
-
DFSDM1_
CKIN4
-
SPI4_NSS
-
-
-
-
-
FMC_D8/
FMC_DA8
-
LCD_G3
EVENT
OUT
PE12
-
TIM1_CH3N
-
DFSDM1_
DATIN5
-
SPI4_SCK
-
-
-
-
-
FMC_D9/
FMC_DA9
COMP1_
OUT
LCD_B4
EVENT
OUT
PE13
-
TIM1_CH3
-
DFSDM1_
CKIN5
-
SPI4_
MISO
-
-
-
-
-
FMC_D10/
FMC_DA10
COMP2_
OUT
LCD_DE
EVENT
OUT
44
SAI2_SD_B
SAI2_SCK_B
SAI2_FS_B
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF1
AF2
AF3
AF4
AF5
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PE14
-
TIM1_CH4
-
-
-
SPI4_
MOSI
-
-
-
-
SAI2_MCL
K_B
-
FMC_D11/
FMC_DA11
-
PE15
-
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
FMC_D12/
FMC_DA12
TIM1_BKIN
_COMP12/
COMP_
TIM1_BKIN
Prot E
Port
45
LCD_CLK
LCD_R7
EVENT
OUT
EVENT
OUT
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF1
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PF0
-
-
-
-
I2C2_SDA
-
-
-
-
-
-
-
FMC_A0
-
-
EVENT
OUT
PF1
-
-
-
-
I2C2_SCL
-
-
-
-
-
-
-
FMC_A1
-
-
EVENT
OUT
PF2
-
-
-
-
I2C2_SMBA
-
-
-
-
-
-
-
FMC_A2
-
-
EVENT
OUT
PF3
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A3
-
-
EVENT
OUT
PF4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A4
-
-
EVENT
OUT
PF5
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A5
-
-
EVENT
OUT
PF6
-
TIM16_CH1
-
-
-
SPI5_NSS
SAI1_SD_B
UART7_RX
PF7
-
TIM17_CH1
-
-
-
SPI5_SCK
SAI1_MCLK
_B
UART7_TX
PF8
-
-
-
-
SPI5_
MISO
SAI1_SCK_B
UART7_RTS/
UART7_DE
PF9
-
-
-
-
SPI5_
MOSI
SAI1_FS_B
PF10
-
SAI1_D3
-
-
-
PF11
-
-
-
-
-
PF12
-
-
-
-
-
PF13
-
-
-
DFSDM1_
DATIN6
PF14
-
-
-
DFSDM1_
CKIN6
PF15
-
-
-
Port F
Port
TIM16_CH1N
TIM17_CH1N
TIM16_BKIN
-
SPI1/2/3/4/
5/6/CEC
SAI4_SD_B
QUADSPI_
BK1_IO3
-
-
-
-
-
EVENT
OUT
SAI4_
MCLK_B
QUADSPI_
BK1_IO2
-
-
-
-
-
EVENT
OUT
SAI4_SCK
_B
TIM13_CH1
QUADSPI_
BK1_IO0
-
-
-
-
EVENT
OUT
UART7_
CTS
SAI4_FS_B
TIM14_CH1
QUADSPI_
BK1_IO1
-
-
-
-
EVENT
OUT
-
-
-
SAI4_D3
-
-
DCMI_D11
LCD_DE
EVENT
OUT
SPI5_
MOSI
-
-
-
-
SAI2_SD_B
-
DCMI_D12
-
EVENT
OUT
-
-
-
-
-
-
-
FMC_A6
-
-
EVENT
OUT
I2C4_SMBA
-
-
-
-
-
-
-
FMC_A7
-
-
EVENT
OUT
I2C4_SCL
-
-
-
-
-
-
-
FMC_A8
-
-
EVENT
OUT
I2C4_SDA
-
-
-
-
-
-
-
FMC_A9
-
-
EVENT
OUT
46
QUADSPI_
CLK
FMC_
SDNRAS
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF2
AF3
AF4
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
PG0
-
-
-
-
-
PG1
-
-
-
-
PG2
-
-
-
TIM8_BKIN
PG3
-
-
-
PG4
-
PG5
-
PG6
Port G
Port
AF1
TIM1_BKIN2
TIM8_BKIN2
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
-
-
-
-
-
-
-
FMC_A10
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
FMC_A11
-
-
EVENT
OUT
-
-
-
-
-
-
-
TIM8_BKIN_
COMP12
FMC_A12
-
-
EVENT
OUT
-
-
-
-
-
-
-
TIM8_BKIN2
_COMP12
FMC_A13
-
-
EVENT
OUT
TIM1_BKIN2
_COMP12
FMC_A14/
FMC_BA0
-
-
EVENT
OUT
-
FMC_A15/
FMC_BA1
-
-
EVENT
OUT
-
FMC_NE3
DCMI_D12
LCD_R7
EVENT
OUT
-
FMC_INT
DCMI_D13
-
-
-
-
-
-
-
-
-
TIM1_ETR
-
-
-
-
-
-
-
-
-
-
TIM17_
BKIN
HRTIM_
CHE1
-
-
-
-
-
-
-
PG7
-
-
HRTIM_
CHE2
-
-
-
SAI1_MCLK
_A
-
-
-
PG8
-
-
-
TIM8_ETR
-
SPI6_NSS
-
-
-
PG9
-
-
-
-
-
SPI1_
MISO/I2S1
_SDI
-
PG10
-
-
HRTIM_
FLT5
-
-
SPI1_NSS/
I2S1_WS
-
-
PG11
-
LPTIM1_IN2
HRTIM_
EEV4
-
-
SPI1_SCK/
I2S1_CK
-
-
PG12
-
LPTIM1_IN1
HRTIM_
EEV5
-
-
SPI6_
MISO
-
USART6_
CK
USART6_
RTS/
USART6_DE
USART6_
RX
SPDIFRX1
_
IN3
SPDIFRX1
_
IN4
-
SPDIFRX1
_
IN1
USART6_
RTS/
USART6_DE
47
SPDIFRX1
_IN2
QUADSPI_
BK1_NCS
ETH_PPS_
OUT
LCD_CLK
EVENT
OUT
FMC_
SDCLK
-
LCD_G7
EVENT
OUT
DCMI_
VSYNC
-
EVENT
OUT
QUADSPI_
BK2_IO2
SAI2_FS_B
-
FMC_NE2/
FMC_NCE
LCD_G3
SAI2_SD_B
-
FMC_NE3
DCMI_D2
LCD_B2
EVENT
OUT
-
SDMMC2_
D2
ETH_MII_
TX_EN/ETH
_RMII_TX_EN
-
DCMI_D3
LCD_B3
EVENT
OUT
LCD_B4
-
FMC_NE4
-
LCD_B1
EVENT
OUT
ETH_MII_TX
D1/ETH_
RMII_TXD1
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
Port
Port G
SYS
AF1
AF2
AF3
AF4
AF5
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
AF6
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
PG13
TRACE
D0
LPTIM1_
OUT
HRTIM_
EEV10
-
-
SPI6_SCK
-
PG14
TRACE
D1
LPTIM1_
ETR
-
-
-
SPI6_
MOSI
-
-
-
-
-
-
-
PG15
-
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
-
-
-
ETH_MII_TX
D0/ETH_
RMII_TXD0
FMC_A24
-
LCD_R0
EVENT
OUT
-
ETH_MII_TX
D1/ETH_
RMII_TXD1
FMC_A25
-
LCD_B0
EVENT
OUT
-
-
DCMI_D13
-
EVENT
OUT
USART6_CTS/
USART6_NSS
USART6_
TX
-
USART6_CTS/
USART6_NSS
48
-
QUADSPI_
BK2_IO3
-
FMC_
SDNCAS
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF2
AF3
AF4
AF5
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI1/2/3/4/
5/6/CEC
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PH2
-
LPTIM1_IN2
-
-
-
-
-
-
-
QUADSPI_
BK2_IO0
SAI2_SCK_B
ETH_MII_
CRS
FMC_
SDCKE0
-
LCD_R0
EVENT
OUT
PH3
-
-
-
-
-
-
-
-
-
QUADSPI_
BK2_IO1
SAI2_
MCLK_B
ETH_MII_
COL
FMC_SDNE0
-
LCD_R1
EVENT
OUT
PH4
-
-
-
-
I2C2_SCL
-
-
-
-
LCD_G5
OTG_HS_U
LPI_NXT
-
-
-
LCD_G4
EVENT
OUT
PH5
-
-
-
-
I2C2_SDA
SPI5_NSS
-
-
-
-
-
-
-
EVENT
OUT
PH6
-
-
-
I2C2_SMBA
SPI5_SCK
-
-
-
-
-
ETH_MII_RX
D2
FMC_SDNE1
DCMI_D8
-
EVENT
OUT
PH7
-
-
-
-
I2C3_SCL
SPI5_
MISO
-
-
-
-
-
ETH_MII_RX
D3
FMC_
SDCKE1
DCMI_D9
-
EVENT
OUT
PH8
-
-
TIM5_ETR
-
I2C3_SDA
-
-
-
-
-
-
-
FMC_D16
DCMI_HSY
NC
LCD_R2
EVENT
OUT
PH9
-
-
-
I2C3_SMBA
-
-
-
-
-
-
-
FMC_D17
DCMI_D0
LCD_R3
EVENT
OUT
PH10
-
-
TIM5_CH1
-
I2C4_SMBA
-
-
-
-
-
-
-
FMC_D18
DCMI_D1
LCD_R4
EVENT
OUT
PH11
-
-
TIM5_CH2
-
I2C4_SCL
-
-
-
-
-
-
-
FMC_D19
DCMI_D2
LCD_R5
EVENT
OUT
PH12
-
-
TIM5_CH3
-
I2C4_SDA
-
-
-
-
-
-
-
FMC_D20
DCMI_D3
LCD_R6
EVENT
OUT
PH13
-
-
-
-
-
-
-
UART4_TX
FDCAN1_
TX
-
-
FMC_D21
-
LCD_G2
EVENT
OUT
PH14
-
-
-
-
-
-
-
UART4_RX
FDCAN1_
RX
-
-
FMC_D22
DCMI_D4
LCD_G3
EVENT
OUT
PH15
-
-
-
-
-
-
-
-
FDCAN1_
TXFD_
MODE
-
-
FMC_D23
DCMI_D11
LCD_G4
EVENT
OUT
Port
Port H
AF1
TIM12_CH1
TIM12_CH2
TIM8_CH1N
TIM8_CH2N
TIM8_CH3N
49
-
FMC_SDN
WE
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF2
AF3
AF4
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PI0
-
-
TIM5_CH4
-
-
SPI2_NSS/
I2S2_WS
-
-
-
-
-
FMC_D24
DCMI_D13
LCD_G5
EVENT
OUT
PI1
-
-
-
-
SPI2_SCK/
I2S2_CK
-
-
-
-
-
FMC_D25
DCMI_D8
LCD_G6
EVENT
OUT
PI2
-
-
-
TIM8_CH4
-
-
-
-
-
-
-
FMC_D26
DCMI_D9
LCD_G7
EVENT
OUT
PI3
-
-
-
TIM8_ETR
-
SPI2_
MOSI/I2S2
_SDO
-
-
-
-
-
-
FMC_D27
DCMI_D10
-
EVENT
OUT
PI4
-
-
-
TIM8_BKIN
-
-
-
-
-
-
FMC_NBL2
DCMI_D5
LCD_B4
EVENT
OUT
PI5
-
-
-
TIM8_CH1
-
-
-
-
-
-
-
FMC_NBL3
DCMI_
VSYNC
LCD_B5
EVENT
OUT
PI6
-
-
-
TIM8_CH2
-
-
-
-
-
-
SAI2_SD_A
-
FMC_D28
DCMI_D6
LCD_B6
EVENT
OUT
PI7
-
-
-
TIM8_CH3
-
-
-
-
-
-
SAI2_FS_A
-
FMC_D29
DCMI_D7
LCD_B7
EVENT
OUT
PI8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PI9
-
-
-
-
-
-
-
-
UART4_RX
FDCAN1_
RX
-
-
FMC_D30
-
LCD_VS
YNC
EVENT
OUT
PI10
-
-
-
-
-
-
-
-
-
FDCAN1_
RXFD_MODE
-
ETH_MII_RX
_ER
FMC_D31
-
LCD_HS
YNC
EVENT
OUT
PI11
-
-
-
-
-
-
-
-
-
LCD_G6
-
-
-
PI12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_HS
YNC
EVENT
OUT
PI13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_VS
YNC
EVENT
OUT
PI14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_CLK
EVENT
OUT
PI15
-
-
-
-
-
-
-
-
-
LCD_G2
-
-
-
-
Port I
Port
AF1
TIM8_BKIN2
AF5
SPI1/2/3/4/
5/6/CEC
SPI2_MIS
O/I2S2_SDI
AF6
50
FDCAN1_
RXFD_MODE
SAI2_
MCLK_A
SAI2_SCK_A
OTG_HS_
ULPI_DIR
TIM8_BKIN2
_COMP12
TIM8_BKIN_
COMP12
-
LCD_R0
EVENT
OUT
EVENT
OUT
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF2
AF3
AF4
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
SPI1/2/3/4/
5/6/CEC
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PJ0
-
-
-
-
-
-
-
-
-
LCD_R7
-
-
-
-
LCD_R1
EVENT
OUT
PJ1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R2
EVENT
OUT
PJ2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R3
EVENT
OUT
PJ3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R4
EVENT
OUT
PJ4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R5
EVENT
OUT
PJ5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R6
EVENT
OUT
PJ6
-
-
-
TIM8_CH2
-
-
-
-
-
-
-
-
-
-
LCD_R7
EVENT
OUT
PJ7
TRGIN
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G0
EVENT
OUT
PJ8
-
TIM1_CH3N
-
-
-
-
-
UART8_TX
-
-
-
-
-
LCD_G1
EVENT
OUT
PJ9
-
TIM1_CH3
-
-
-
-
-
UART8_RX
-
-
-
-
-
LCD_G2
EVENT
OUT
PJ10
-
TIM1_CH2N
-
-
SPI5_
MOSI
-
-
-
-
-
-
-
-
LCD_G3
EVENT
OUT
PJ11
-
TIM1_CH2
-
-
SPI5_µ
MISO
-
-
-
-
-
-
-
-
LCD_G4
EVENT
OUT
-
-
-
-
-
-
-
-
LCD_G3
-
-
-
-
LCD_B0
EVENT
OUT
Port J
Port
PJ12
TRGOUT
AF1
TIM8_CH2N
TIM8_CH1
TIM8_CH1N
TIM8_CH2
TIM8_CH2N
AF5
AF6
PJ13
-
-
-
-
-
-
-
-
-
LCD_B4
-
-
-
-
LCD_B1
EVENT
OUT
PJ14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B2
EVENT
OUT
PJ15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
EVENT
OUT
51
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
AF0
AF2
AF3
AF4
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI2/3/SAI1
/3/I2C4
/
UART4/
DFSDM
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
I2C4/UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
SPI1/2/3/4/
5/6/CEC
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD/
COMP
UART5/
LCD
SYS
PK0
-
TIM1_CH1N
-
TIM8_CH3
-
SPI5_SCK
-
-
-
-
-
-
-
-
LCD_G5
EVENT
OUT
PK1
-
TIM1_CH1
-
-
SPI5_NSS
-
-
-
-
-
-
-
-
LCD_G6
EVENT
OUT
PK2
-
TIM1_BKIN
-
TIM8_BKIN
-
-
-
-
-
-
-
-
LCD_G7
EVENT
OUT
PK3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B4
EVENT
OUT
PK4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B5
EVENT
OUT
PK5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B6
EVENT
OUT
PK6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B7
EVENT
OUT
PK7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_DE
EVENT
OUT
Port K
Port
AF1
TIM8_CH3N
AF5
AF6
52
TIM8_BKIN
_COMP12
TIM1_BKIN_
COMP12
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
1.4.2 ESC Sub-system Pin Description
Following abbreviations are used in “Type” column of below pin description tables. Note that some I/O pins
with multiple signal definitions on the same pin may have different attributes in “Type” column for different
signal definition
A
B5
I5
O5
B3
I3
O3
Analog
Bi-directional I/O, 3.3V with 5V tolerant
Input, 3.3V with 5V tolerant
Output, 3.3V with 5V tolerant
Bi-directional I/O, 3.3V
Input, 3.3V
Output, 3.3V
PU
PD
P
S
T
4m
8m
Internal Pull-Up
Internal Pull-Down
Power/Ground pin
Schmitt Trigger
Tri-state
4mA driving strength
8mA driving strength
The multi-function pin settings are configured by the I2C Hardware Configuration EEPROM (HWCFGEE).
Please refer to Section 2.45.4.2 for details.
Pin No
Pin Name
Type
E12
TEST
I5/PD/S
F12
NC
I3
C13
RSTn
I5/PU/S
RSTO\
RSTO_POL
O5/8m
B13
M1
LED_RUN\
EEP_SIZE
B5/4m
M2
LED_ERR\
3PORT_MODE
B5/4m
L14
P0_ACT\
P0_FIBER
B5/4m
M13
P1_ACT\
P1_FIBER
B5/4m
G4
SYNC_LATCH[1]
B5/8m
F4
SYNC_LATCH[0]
B5/8m
M3
EEP_DONE
O5/8m
Description
Test mode enable
For normal operation, please always tie to logic
low or NC.
Reserved. Please connect to GND.
Reset Input, active low
RST_N is the hardware reset input used to reset
this chip. This input is logic AND with internal
Power-On-Reset (POR) circuit, which generates
the main system reset for this chip.
Reset Output
This pin is input direction during chip reset stage
used to bootstrap the mode setting to decide the
RSTO polarity, please refer to Section 2.45.4.1.
RUN LED
This pin is input direction during chip reset stage
used to bootstrap the mode setting to decide the
EEPROM size configuration, please refer to
Section 2.45.4.1.
Error LED
This pin is input direction during chip reset stage
used to bootstrap the mode setting to decide the
Port 2 MII enable configuration, please refer to
Section 2.45.4.1.
PHY 0 Link/Activity LED
This pin is input direction during chip reset stage
used to bootstrap the mode setting to decide the
PHY 0 media mode, please refer to Section
2.45.4.1.
PHY 1 Link/Activity LED
This pin is input direction during chip reset stage
used to bootstrap the mode setting to decide the
PHY 1 media mode, please refer to Section
2.45.4.1.
Distributed Clocks SyncSignal output or
LatchSignal input 1
Distributed Clocks SyncSignal output or
LatchSignal input 0
This pin asserted high indicates that the EEPROM
53
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin No
Pin Name
Type
PDI_EMU
OE_EXT
LRDn
SCLK
SOF
LECSn
SCS_ESC
OUTVLD
LWRn
MOSI
EOF
LFCSn
SCS_FUNC
WD_TRIG
LINT
SINT
I5
I5
I5
I5
O5/8m
I5
I5
O5/8m
I5
I5
O5/8m
I5
I5
O5/8m
O5/T
O5/T
D11
SCL
O5/T/4m
/S
A10
SDA
B5/T/4m
/S
LAT_IN
LRDY
MISO
IO[0]
LDA[0]
MSCLK
IO[1]
LDA[1]
MMOSI
IO[2]
LDA[2]
MMISO
IO[4]
LDA[4]
MSS[0]
IO[16]
LA[8]
I5
O5/T
O5
B5/8m
B5
O5
B5/8m
B5
O5
B5/8m
B5
I5
B5/8m
B5
O5
B5/8m
I5
LINK
I5
IO[17]
LA[9]
B5/8m
I5
PULAB
O5
MDIO
IO[18]
LA[10]
B5
B5/8m
I5
C11
A8
C2
C5
D4
D5
H4
J11
J12
G5
E11
K11
H11
H12
Description
is successfully loaded (Checksum matched) and
the PDI can be used.
PDI Emulation enable
Output Enable
Local bus Read
SPI Clock
Start-of-Frame
Local bus ESC Chip Select
SPI Chip Select for ESC
Output data Valid/Output event
Local bus Write
SPI data MOSI
End-of-Frame
Local bus Function Chip Select
SPI Chip Select for Function
Watchdog Trigger
Local bus Interrupt
SPI Interrupt
I2C Serial Clock line for I2C master controller
SCL is a tri-stateable output, which requires an
external pull-up resistor.
I2C Serial Data line for I2C master controller.
SDA is a tri-stateable output, which requires an
external pull-up resistor.
external data Latch
Local bus Ready
SPI data MISO
Digital /General Purpose I/O[7:0]
Local bus Data bus [7:0]
SPI Master SCLK
Digital /General Purpose I/O[7:0]
Local bus Data bus [7:0]
SPI Master MOSI
Digital /General Purpose I/O[7:0]
Local bus Data bus [7:0]
SPI Master MISO
Digital /General Purpose I/O[7:0]
Local bus Data bus [7:0]
SPI Master Slave Select
Digital /General Purpose I/O[23:16]
Local bus Address bus
LINK
Provided by the PHY if a 100 Mbps (Full Duplex)
link is established.
Digital /General Purpose I/O[23:16]
Local bus Address bus
Pulse AB, toggle when programmable point A and
B
PHY Management Interface data
Digital /General Purpose I/O[23:16]
Local bus Address bus
54
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Pin No
G12
Pin Name
PULC
MDC
IO[19]
LA[11]
PULZ
Type
O5
O5
B5/8m
I5
O5
TXD[0] \ LINK_POL
O5
IO[20]
LA[12]
PULB
B5/8m
I5
O5
TXD[1]
TXD[2:1]\ TX_SH[1:0]
O5
IO[21]
LA[13]
PULA
B5/8m
I5
O5
TXD[2]
TXD[2:1]\ TX_SH[1:0]
O5
IO[22]
LBHE
PWM3H
TXD[3]
IO[23]
PWM3L
TX_EN
IO[24]
LDA[8]
PWM2H
RXD[0]
IO[25]
LDA[9]
PWM2L
RXD[1]
IO[26]
LDA[10]
PWM1H
RXD[2]
IO[27]
LDA[11]
PWM1L
RXD[3]
IO[28]
LDA[12]
EMn
B5/8m
I5
O5/T
O5
B5/8m
O5/T
O5
B5/8m
B5
O5/T
I5
B5/8m
B5
O5/T
I5
B5/8m
B5
O5/T
I5
B5/8m
B5
O5/T
I5
B5/8m
B5
I5
L11
E8
D8
C8
C4
F5
E5
H5
J5
Description
Pulse C, PWM period central point
PHY Management Interface clock
Digital /General Purpose I/O[23:16]
Local bus Address bus
Pulse Z, PWM period start point
Transmit data [0]
These pins are input direction during chip reset use
to bootstrap the mode setting to decide external
PHY’s LINK polarity.
Digital /General Purpose I/O[23:16]
Local bus Address bus
Pulse B, programmable point B
Transmit data [2:1]
This pin is input direction during chip reset stage
used to bootstrap the mode setting to decide the
external PHY’s TXD phase shift, please refer to
Section 2.45.4.1.
Digital /General Purpose I/O[23:16]
Local bus Address bus
Pulse A, programmable point A
Transmit data [2:1]
This pin is input direction during chip reset stage
used to bootstrap the mode setting to decide the
external PHY’s TXD phase shift, please refer to
Section 2.45.4.1.
Digital /General Purpose I/O[23:16]
Local bus Byte High Enable (16-bit width only)
PWM 3 High pin
Transmit data [3]
Digital /General Purpose I/O[23:16]
PWM 3 Low pin
Transmit enable
Digital/General Purpose I/O[31:24]
Local bus Data bus [15:8]
PWM 2 High pin
Receive data
Digital/General Purpose I/O[31:24]
Local bus Data bus [15:8]
PWM 2 Low pin
Receive data
Digital/General Purpose I/O[31:24]
Local bus Data bus [15:8]
PWM 1 High pin or DIR pin
Receive data
Digital/General Purpose I/O[31:24]
Local bus Data bus [15:8]
PWM 1 Low pin or STEP pin
Receive data
Digital/General Purpose I/O[31:24]
Local bus Data bus [15:8]
Emergency input, active low
55
AX58400
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Pin No
Pin Name
RX_ER
IO[29]
LDA[13]
ENCA
RX_DV
IO[30]
LDA[14]
ENCB
RX_CLK
IO[31]
LDA[15]
ENCZ
Type
I5
B5/8m
B5
I5
I5
B5/8m
B5
I5
I5
B5/8m
B5
I5
MCLK
O5
P6
P7
P1_TXON
P1_RXIN
A
A
P8
P1_SD
A
P9
P10
P0_TXON
P0_RXIN
A
A
P11
P0_SD
A
P12
R12
P0_XSCI
P0_XSCO
A
A
R6
P1_TXOP
A
R7
P1_RXIP
A
R9
P0_TXOP
A
R10
P0_RXIP
A
L9
P0_RSET_BG
A
K5
L5
L4
Description
Receive error
Digital/General Purpose I/O[31:24]
Local bus Data bus [15:8]
ENC input A, Sin., CW, CLK, or HALL A
Receive data valid
Digital/General Purpose I/O[31:24]
Local bus Data bus [15:8]
ENC input B, Cos., CCW, DIR, or HALL B
Receive Clock
Digital/General Purpose I/O[31:24]
Local bus Data bus [15:8]
ENC input Z, Zero point or HALL C
MII Clock
25 MHz clock source for Ethernet PHYs
PHY 1 differential Transmitted Negative signal
PHY 1 differential Received Negative signal
PHY 1 fiber mode Signal Detect
Same P0_SD description
PHY 0 differential Transmitted Negative signal
PHY 0 differential Received Negative signal
PHY 0 fiber mode Signal Detect
SD < 0.2V, Copper mode1.0V < SD < 1.8V, Fiber mode without detected
signal. Generate far-end fault
SD > 2.4V, Fiber mode with detected signal
Crystal 25MHz Input
Crystal 25MHz Output
PHY 1 differential Transmitted Positive signal
Same as PHY0 TXOP/ON description
PHY 1 differential Received Positive signal
Same as PHY0 RXIP/IN description
PHY 0 differential Transmitted Positive signal
In the copper mode, the differential data is
transmitted to the media on the TXOP/TXON
signal pair in the MDI mode.
In the fiber mode, the signal pair should be
connected to the TX+/TX- pin of the fiber
transceiver.
PHY 0 differential Received Positive signal
In the copper mode, the differential data from the
media is received on the RXIP/RXIN signal pair in
the MDI mode.
In the fiber mode, the signal pair should be
connected to the RX+/RX- pin of the fiber
transceiver.
PHY off-chip Bias Resistor
Connects an external resistor of 12 KΩ ± 1% to
the PCB analog ground.
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1.4.3 Power/Ground Pin Description
Pin No
C6, D6,
E6, F6,
G6, H6,
J6, J10,
K6, K7,
K10
K15
J15
H15
H14
C1, N1,
R14
A1, R1,
R15
A15
A14
B14
B15
K14
J1
H1
B1, C9,
D9, E9,
F8, F9,
F11, G7,
G8, G9,
G10, H7,
H8, H9,
H10, J7,
J8, J9,
J14, K8,
K9, N6,
N7, N8,
N9, N10,
P1, P5,
P15
C10, D10,
E10, F10
Pin Name
Type
Description
VDD
P
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
VSSSMPS
VLXSMPS
VDDSMPS
VFBSMPS
S
S
S
S
VCAP
S
VDDLDO
S
VSSA
VREF+
VREFVDDA
VBAT
VDD50USB
VDD33USB
GND (VSS)
S
S
S
S
S
S
S
P
VCCK
P
VCC12A_PLL
P
VCC3IO
P
VCC33A
P
D15
C7, D7,
E7, F7
R5, R8,
R11
Ground for all Analog and Digital Power.
Digital Power for core, 1.2V
Please add a 0.1uF bypass capacitor between each
VCCK and GND.
Analog Power for PLL, 1.2V.
Please add a 0.1uF bypass capacitor between
VCC12A_PLL and GND.
Digital Power for I/O pins, 3.3V
Please add a 0.1uF bypass capacitor between each
VCC3IO and GND.
Analog Power for Ethernet PHY, 3.3V
Please add a 0.1uF bypass capacitor between
VCC33A and GND.
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EtherCAT Slave Controller w/ Dual-Core MCU
2 Function Description
Dual STM32 Arm® Cortex® cores
The industrial AX58400 device embed two STM32 Arm® cores, a Cortex® -M7 and a Cortex® - M4. The Cortex® M4 offers optimal performance for real-time applications while the Cortex® -M7 core can execute highperformance tasks in parallel.
The two cores belong to separate power domains. This allows designing gradual high- power efficiency solutions
in combination with the low-power modes already available on this AX58400 device.
2.1.1 Arm® Cortex® -M7 with FPU
The Arm® Cortex® -M7 with double-precision FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation,
with a reduced pin count and optimized power consumption, while delivering outstanding computational
performance and low interrupt latency.
The Cortex® -M7 processor is a highly efficient high-performance featuring:
• Six-stage dual-issue pipeline
• Dynamic branch prediction
• Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
• 64-bit AXI interface
• 64-bit ITCM interface
• 2x32-bit DTCM interfaces
The following memory interfaces are supported:
• Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
• Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses
• AXI Bus interface to optimize Burst transfers
• Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm
execution.
It also supports single and double precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
Figure 1.2-1 shows the general block diagram of the AX58400 device.
Note: Cortex® -M7 with FPU core is binary compatible with the Cortex® -M4 core.
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EtherCAT Slave Controller w/ Dual-Core MCU
2.1.2 Arm® Cortex® -M4 with FPU
The Arm® Cortex® -M4 processor is a high-performance embedded processor which supports DSP instructions. It
was developed to provide an optimized power consumption MCU, while delivering outstanding computational
performance and low interrupt latency.
The Arm® Cortex® -M4 processor is a highly efficient MCU featuring:
• 3-stage pipeline with branch prediction
• Harvard architecture
• 32-bit System (S-BUS) interface
• 32-bit I-BUS interface
• 32-bit D-BUS interface
The Arm® Cortex® -M4 processor also features a dedicated hardware adaptive real-time accelerator (ST ART
Accelerator™). This is an instruction cache memory composed of sixty- four 256-bit lines, a 256-bit cache buffer
connected to the 64-bit AXI interface and a 32-bit interface for non-cacheable accesses.
Memory protection unit (MPU)
The devices feature two memory protection units. Each MPU manages the CPU access rights and the attributes of
the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted
user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data
processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16
protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and
attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is generated.
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Memories
2.3.1 Embedded Flash memory
The AX58400 device embeds 2 Mbytes of Flash memory that can be used for storing programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing both code and data
constants. Each word consists of:
• One Flash word (8 words, 32 bytes or 256 bits)
• 10 ECC bits.
The Flash memory is divided into two independent banks. Each bank is organized as follows:
• 1 Mbyte of user Flash memory block containing eight user sectors of 128 Kbytes (4 K Flash memory words)
• 128 Kbytes of System Flash memory from which the device can boot
• 2 Kbytes (64 Flash words) of user option bytes for user configuration
2.3.2 Secure access mode
In addition to other typical memory protection mechanism (RDP, PCROP), AX58400 device introduces the Secure
access mode, a new enhanced security feature. This mode allows developing user-defined secure services by
ensuring, on the one hand code and data protection and on the other hand code safe execution.
Two types of secure services are available:
• Root Secure Services:
These services are embedded in System memory. They provide a secure solution for firmware and third-party
modules installation. These services rely on cryptographic algorithms based on a device unique private key.
• User-defined secure services:
These services are embedded in user Flash memory. Examples of user secure services are proprietary user
firmware update solution, secure Flash integrity check or any other sensitive applications that require a high
level of protection.
The secure firmware is embedded in specific user Flash memory areas configured through option bytes.
Secure services are executed just after a reset and preempt all other applications to guarantee protected and safe
execution. Once executed, the corresponding code and data are no more accessible.
The above secure services are available only for Cortex ® -M7 core operating in Secure access mode. The other
masters cannot access the option bytes involved in Secure access mode settings or the Flash secured areas.
2.3.3 Embedded SRAM
All devices feature around 1 Mbyte of RAM with hardware ECC. The RAM is divided as follows:
• 512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
• SRAM1 mapped on D2 domain: 128 Kbytes
• SRAM2 mapped on D2 domain: 128 Kbytes
• SRAM3 mapped on D2 domain: 32 Kbytes
• SRAM4 mapped on D3 domain: 64 Kbytes
• 4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses, and is retained in Standby or
VBAT mode.
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• RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either from the Arm® Cortex® M7 CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the Cortex® -M7(AHBS):
–
64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical real-times routines
by the Cortex® -M7.
–
128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service routines or stack/heap
memory. Both DTCM-RAMs can be used in parallel (for load/store operations) thanks to the Cortex ® M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in memories may occur.
They can be detected and corrected by ECC. This is an expected behavior that has to be managed at finalapplication software level in order to ensure data integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
• 7 ECC bits are added per 32-bit word.
• 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction and double-error
detection.
2.3.4 ST ART™ accelerator
The ART™ (adaptive real-time) accelerator block speeds up instruction fetch accesses of the Cortex ® -M4 core
from D1-domain internal memories (Flash memory bank 1, Flash memory bank 2, AXI SRAM) and from D1domain external memories attached via Quad-SPI controller and Flexible memory controller (FMC).
The ART™ accelerator is a 256-bit cache line using 64-bit WRAP4 accesses from the 64-bit AXI D1 domain. The
acceleration is achieved by loading selected code into an embedded cache and making it instantly available to
Cortex® -M4 core, thus avoiding latency due to memory wait states.
Figure 2.3-1shows the block schematic and the environment of the ART accelerator.
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EtherCAT Slave Controller w/ Dual-Core MCU
Figure 2.3-1: ST ART™ accelerator schematic and environment
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EtherCAT Slave Controller w/ Dual-Core MCU
Boot modes
By default, the boot codes are executed simultaneously by both cores. However, by programming the appropriate
Flash user option byte, it is possible to boot from one core while clock-gating the other core.
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to
program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes:
• All Flash address space
• Flash memory and SRAMs (except for ITCM /DTCM RAMs which cannot be accessed by the Cortex ® -M4
core)
The bootloader is located in non-user System memory. It is used to reprogram the Flash memory through a serial
interface (USART, I2C, SPI, USB-DFU).
Power supply management
2.5.1 Power supply scheme
AX58400 power supply voltages are the following:
• VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD pins.
• VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
• VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and OPAMP.
• VDD33USB and VDD50USB:
• VDD50USB can be supplied through the USB cable to generate the V DD33USB via the USB internal regulator. This
allows supporting a VDD supply different from 3.3 V.
The USB regulator can be bypassed to supply directly V DD33USB if VDD = 3.3 V.
• VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
• VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V, 1.2 V or 1.35 V). They are
configured through VOS bits in PWR_D3CR register and ODEN bit in the SYSCFG_PWRCR register. The
VCORE domain is split into the following power domains that can be independently switch off.
–
D1 domain containing some peripherals and the Cortex ® -M7 core.
–
D2 domain containing a large part of the peripherals and the Cortex ® -M4 core.
–
D3 domain containing some peripherals and the system control.
• VDDSMPS= 1.62 V to 3.6 V: SMPS step-down converter power supply
VDDSMPS must be kept at the same voltage level as VDD.
• VLXSMPS = SMPS step-down converter output coupled to an inductor.
• VFBSMPS = VCORE, 1.8 V or 2.5 V external SMPS step-down converter feedback voltage sense input.
During power-up and power-down phases, the following power sequence requirements must be respected (see
Figure 2.5-1):
• When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must remain below VDD + 300
mV.
• When VDD is above 1 V, all power supplies are independent (except for V DDSMPS, which must remain at the
same level as VDD).
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During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided
to the microcontroller remains below 1 mJ. This allows external decoupling capacitors to be discharged with
different time constants during the power-down transient phase.
Figure 2.5-1: Power-up/power-down sequence
1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB.
2. VDD and VDDSMPS must be wired together into order to follow the same voltage sequence.
2.5.2 Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout
reset (BOR) circuitry:
• Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold. The devices remain in
Reset mode when VDD is below this threshold,
• Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
• Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to 2.7 V) can be configured
through option bytes. A reset is generated when VDD drops below this threshold.
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2.5.3 Voltage regulator (SMPS step-down converter and LDO)
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can be independently
switched off.
Voltage regulator output can be adjusted according to application needs through 6 power supply levels:
• Run mode (VOS0 to VOS3)
–
Scale 0: boosted performance (available only with LDO regulator)
–
Scale 1: high performance
–
Scale 2: medium performance and consumption
–
Scale 3: optimized performance and low-power consumption
Note: For AX58400 sales types (industrial temperature range) the voltage regulator output can be set only to VOS2
or VOS3 in Run mode (VOS0 and VOS1 are not available for industrial temperature range).
• Stop mode (SVOS3 to SVOS5)
–
Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C, LPTIM) are
operational
–
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible through GPIO or
asynchronous interrupt.
2.5.4 SMPS step-down converter
The built-in SMPS step-down converter is a highly power-efficient DC/DC non-linear switching regulator that
provides lower power consumption than a conventional voltage regulator (LDO).
The SMPS step-down converter can be used for the following purposes:
• Direct supply of the VCORE domain
–
the SMPS step-down converter operating modes follow the device system operating modes (Run, Stop,
Standby).
–
the SMPS step-down converter output voltage are set according to the selected VOS and SVOS bits
(voltage scaling)
• Delivery of an intermediate voltage level to supply the internal voltage regulator (LDO)
–
SMPS step-down converter operating modes
When the SDEXTHP bit is equal to 0 in the PWR_CR3 register, the SMPS step- down converter follows
the device system operating modes (Run, Stop and Standby).
When the SDEXTHP bit is equal to 1 in PWR_CR3, the SMPS step-down converter is forced to Highperformance mode and does not follow the device system operating modes (Run, Stop and Standby).
–
The SMPS step-down converter output equals 1.8 V or 2.5 V according to the selected SD level
• Delivery of an external supply
–
The SMPS step-down converter is forced to High-performance mode (provided SDEXTHP bit is equal
to 1 in PWR_CR3)
–
The SMPS step-down converter output equals 1.8 V or 2.5 V according to the selected SD level
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Low-power strategy
There are several ways to reduce power consumption on AX58400:
• Select the SMPS step-down converter as VCORE supply voltage source, as it allows to enhance power efficiency.
• Select the adequate voltage scaling
• Decrease the dynamic power consumption by slowing down the system clocks even in Run mode, and by
individually clock gating the peripherals that are not used.
• Save power consumption when one or both CPUs are idle, by selecting among the available low-power mode
according to the user application needs. This allows achieving the best compromise between short startup time,
low-power consumption, as well as available wakeup sources.
The devices feature several low-power modes:
• CSleep (CPU clock stopped)
• CStop (CPU sub-system clock stopped)
• DStop (Domain bus matrix clock stopped)
• Stop (System clock stopped)
• DStandby (Domain powered down)
• Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or
WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex® -Mx core is set after returning
from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its subsystem and the peripherals
allocated in the domain enter low-power mode. For instance, D1 or D2 domain enters DStop/DStandby mode
when the CPU of the domain is in CStop mode AND the other CPU has no peripheral allocated in that domain, or
if it is in CStop mode too. D3 domain can enter DStop/DStandby mode if both core subsystems do not have active
peripherals in D3 domain, and D3 is not forced in Run mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the power domains
are in DStop or DStandby mode.
The clock system can be re-initialize by a master CPU (either the Cortex® -M4 or -M7) after exiting Stop mode
while the slave CPU is held in low-power mode. Once the master CPU has re-initialized the system, the slave CPU
can receive a wakeup interrupt and proceed with the interrupt service routine.
System power mode
Run
D1 domain power
mode
D2 domain power
mode
DRun/DStop/DStandby DRun/DStop/DStandby
D3 domain power
mode
DRun
Stop
DStop/DStandby
DStop/DStandby
DStop
Standby
DStandby
DStandby
DStandby
Table 2.6-1: System vs domain low-power mode
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Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of all the clocks, as well
as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the choice
of clock sources and allows to apply clock ratios to improve the power consumption. In addition, on some
communication peripherals that are capable to work with two different clock domains (either a bus interface clock
or a kernel peripheral clock), the system frequency can be changed without modifying the baudrate.
2.7.1 Clock management
The devices embed four internal oscillators, two oscillators with external crystal or resonator, two internal
oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
• Internal oscillators:
–
64 MHz HSI clock
–
48 MHz RC oscillator
–
4 MHz CSI clock
–
32 KHz LSI clock
• External oscillators:
–
HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz (generated from a crystal/
ceramic resonator)
–
LSE clock: 32.768 KHz
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock configuration.
2.7.2 System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for the debug, part of the
RCC and power controller status registers, as well as the backup power domain.
A system reset is generated in the following cases:
•
Power-on reset (pwr_por_rst)
•
Brownout reset
•
Low level on NRST pin (external reset)
•
Independent watchdog 1 (from D1 domain)
•
Independent watchdog 2 (from D2 domain)
•
Window watchdog 1 (from D1 domain)
•
Window watchdog 2 (from D2 domain)
•
Software reset
•
Low-power mode security reset
•
Exit from Standby
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General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up
or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most
of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and
have speed selection to better manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power consumption (refer to GPIOs
register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing
to the I/Os registers.
Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow interconnecting bus
masters with bus slaves (see Figure 2.9-1).
Figure 2.9-1: AX58400 Bus matrix
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DMA controllers
The devices feature four DMA instances to unload CPU activity:
• A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral
to memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI
interface and a dedicated AHB interface to access Cortex® -M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA controllers located in D2
domain to extend the standard DMA capabilities, or can manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers and linked list transfers.
• Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request router capabilities.
• One basic DMA (BDMA) located in D3 domain, with request router capabilities.
The DMA request router could be considered as an extension of the DMA controller. It routes the DMA peripheral
requests to the DMA controller itself. This allowing managing the DMA requests with a high flexibility,
maximizing the number of DMA requests that run concurrently, as well as generating DMA requests from
peripheral output trigger or DMA event.
ST Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphical accelerator which offers advanced bit blitting, row data
copy and pixel format conversion. It supports the following functions:
• Rectangle filling with a fixed color
• Rectangle copy
• Rectangle copy with pixel format conversion
• Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds
dedicated memory to store color lookup tables. The DMA2D also supports block based YCbCr to handle JPEG
decoder output.
An interrupt can be generated when an operation is complete or at a programmed watermark.
All the operations are fully automatized and are running independently from the CPU or the DMAs.
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Nested vectored interrupt controller (NVIC)
Both Cortex® -M7 (CPU1) and Cortex® -M4 (CPU2) cores have their own nested vector interrupt controller
(respectively NVIC1 and NVIC2). Each NVIC instance is able to manage 16 priority levels, and handle up to 150
maskable interrupt channels plus the 16 interrupt lines of the Cortex ® -M7 with FPU core.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor context automatically saved on interrupt entry, and restored on interrupt exit with no instruction
overhead
This hardware block provides flexible interrupt management features with minimum interrupt latency.
Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up the processors, power
domains and/or D3 domain from Stop mode.
The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events and 61 direct events
(including two interrupt lines for inter-core management).
Configurable events have dedicated pending flags, active edge selection, and software trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the
scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC
calculation unit helps compute a signature of the software during runtime, to be compared with a reference
signature generated at link- time and stored at a given memory location.
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Flexible memory controller (FMC)
The FMC controller main features are the following:
• Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (4 memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• 8-,16-,32-bit data bus width
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
• Read FIFO for SDRAM controller
• The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the FMC kernel clock divided
by 2.
Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication interface targeting Single,
Dual or Quad-SPI Flash memories. It supports both single and double datarate operations.
It can operate in any of the following modes:
• Direct mode through registers
• External Flash status register polling mode
• Memory mapped mode.
Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data accesses are supported as
well as code execution.
The opcode and the frame format are fully programmable.
Analog-to-digital converters (ADCs)
The AX58400 device embeds three analog-to-digital converters, which resolution can be configured to 16, 14, 12,
10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in the Single-shot or Scan mode. In Scan
mode, automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
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The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC converted values to
a destination location without any software action.
In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some or all selected
channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4,
TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer.
Temperature sensor
AX58400 device embeds a temperature sensor that generates a voltage (VTS) that varies linearly with the
temperature. This temperature sensor is internally connected to ADC3_IN18. The conversion range is between 1.7
V and 3.6 V. It can measure the device junction temperature ranging from − 40 up to +140 °C.
The temperature sensor has a good linearity, but it has to be calibrated to obtain a good overall accuracy of the
temperature measurement. As the temperature sensor offset varies from chip to chip due to process variation, the
uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To
improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated. The
temperature sensor factory calibration data are stored in the System memory area, which is accessible in Readonly mode.
VBAT operation
The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the voltage applied on
VBAT pin (when VDD supply is not present). VBAT power is switched when the PDR detects that VDD dropped
below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or directly by VDD, in
which case, the VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it
from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available
and VBAT pin should be connected to VDD.
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Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal
outputs.
This dual digital Interface supports the following features:
• two DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• left or right data alignment in 12-bit mode
• synchronized update capability
• noise-wave generation
• triangular-wave generation
• dual DAC channel independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• external triggers for conversion
• input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected to different DMA
streams.
Ultra-low-power comparators (COMP)
AX58400 device embeds two rail-to-rail comparators (COMP1 and COMP2). They feature programmable
reference voltage (internal or external), hysteresis and speed (low speed for low-power) as well as selectable output
polarity.
The reference voltage can be one of the following:
• An external I/O
• A DAC output channel
• An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers, and be combined into
a window comparator.
Operational amplifiers (OPAMP)
AX58400 device embeds two rail-to-rail operational amplifiers (OPAMP1 and OPAMP2) with external or internal
follower routing and PGA capability.
The operational amplifier main features are:
• PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3, -7 or -15
• One positive input connected to DAC
• Output connected to internal ADC
• Low input bias current down to 1 nA
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• Low input offset voltage down to 1.5 mV
• Gain bandwidth up to 7.3 MHz
The devices embed two operational amplifiers (OPAMP1 and OPAMP2) with two inputs and one output each.
These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The
operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging
from 2 to 16 or with inverting gain ranging from -1 to -15.
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers)
or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to perform
digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDM can
also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering
in hardware. DFSDM features optional parallel data stream inputs from internal ADC peripherals or
microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital
filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC
resolution.
The DFSDM peripheral supports:
• 8 multiplexed input digital serial channels:
–
configurable SPI interface to connect various SD modulator(s)
–
configurable Manchester coded 1 wire interface support
–
PDM (Pulse Density Modulation) microphone input support
–
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
–
clock output for SD modulator(s): 0..20 MHz
• alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
–
internal sources: ADC data or memory data streams (DMA)
• 4 digital filter modules with adjustable digital signal processing:
–
Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
integrator: oversampling ratio (1..256)
• up to 24-bit output data resolution, signed output data format
• automatic data offset correction (offset stored in register by user)
• continuous or single conversion
• start-of-conversion triggered by:
–
software trigger
–
internal timers
–
external events
–
start-of-conversion synchronously with first digital filter module (DFSDM0)
• analog watchdog feature:
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–
low value and high value data threshold registers
–
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
–
input from final output data or from selected input digital serial channels
–
continuous monitoring independently from standard conversion
• short circuit detector to detect saturated analog input values (bottom and top range):
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
–
monitoring continuously each input serial channel
• break signal generation on analog watchdog event or on short circuit detector event
• extremes detector:
–
storage of minimum and maximum values of final conversion data
–
refreshed by software
• DMA capability to read the final conversion data
• interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence
• “regular” or “injected” conversions:
–
“regular” conversions can be requested at any time or even in Continuous mode without having any
impact on the ti ming of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
DFSDM features
DFSDM1
Number of filters
4
Number of input
transceivers/channels
8
Internal ADC parallel input
X
Number of external triggers
16
Regular channel information in
identification register
X
Table 2.23-1: DFSDM implementation
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit
to 14-bit parallel interface, to receive video data. The camera interface can achieve a data transfer rate up to 105
Mbyte/s using a 60 MHz pixel clock. It features:
• Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12- or 14-bit
• Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565
progressive video or compressed data (like JPEG)
• Supports Continuous mode or Snapshot (a single frame) mode
• Capability to automatically crop the image
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LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals
to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following
features:
• 2 display layers with dedicated FIFO (64x64-bit)
• Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
• Up to 8 input color formats selectable per layer
• Flexible blending between two layers using alpha value (per pixel or constant)
• Flexible programmable parameters for each layer
• Color keying (transparency color)
• Up to 4 programmable interrupt events
• AXI master interface with burst of 16 words
JPEG Codec (JPEG)
The JPEG Codec can encode and decode a JPEG stream as defined in the ISO/IEC 10918- 1 specification. It
provides an fast and simple hardware compressor and decompressor of JPEG images with full management of
JPEG headers.
The JPEG codec main features are as follows:
• 8-bit/channel pixel depths
• Single clock per pixel encoding and decoding
• Support for JPEG header generation and parsing
• Up to four programmable quantization tables
• Fully programmable Huffman tables (two AC and two DC)
• Fully programmable minimum coded unit (MCU)
• Encode/decode support (non simultaneous)
• Single clock Huffman coding and decoding
• Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
• Support for single greyscale component
• Ability to enable/disable header processing
• Fully synchronous design
• Configuration for High-speed decode mode
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Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.
Cryptographic acceleration (CRYP and HASH)
The devices embed a cryptographic processor that supports the advanced cryptographic algorithms usually
required to ensure confidentiality, authentication, data integrity and non- repudiation when exchanging messages
with a peer:
• Encryption/Decryption
–
DES/TDES (data encryption standard/triple data encryption standard): ECB (electronic codebook) and
CBC (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key
–
AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (Counter mode) chaining
algorithms, 128, 192 or 256-bit key
• Universal HASH
–
SHA-1 and SHA-2 (secure HASH algorithms)
–
MD5
–
HMAC
The cryptographic accelerator supports DMA request generation.
Timers and watchdogs
The devices include one high-resolution timer, two advanced-control timers, ten general- purpose timers, two basic
timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 2.29-1 compares the features of the advanced-control, general-purpose and basic timers.
Timer
type
Timer
Highresolution HRTIM1
timer
Advancedcontrol
TIM1,
TIM8
DMA
Capture/
Counter Counter Prescaler
request
compare
resolution
type
factor
generation channels
16-bit
16-bit
Complementary
output
/1 /2 /4
(x2 x4 x8
x16 x32,
with DLL)
Yes
10
Yes
Any
Up,
integer
Down,
between 1
Up/down
and 65536
Yes
4
Yes
Up
77
Max
interface
clock
(MHz)
480
(2)
120
Max
timer
clock
(MHz)
(1)(2)
480
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Timer
type
Timer
TIM2,
TIM5
TIM3,
TIM4
TIM12
DMA
Capture/
Counter Counter Prescaler
request
compare
resolution
type
factor
generation channels
TIM15
TIM16,
TIM17
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)(2)
32-bit
Any
Up,
integer
Down,
between 1
Up/down
and 65536
Yes
4
No
120
240
16-bit
Any
Up,
integer
Down,
between 1
Up/down
and 65536
Yes
4
No
120
240
16-bit
Up
Any
integer
between 1
and 65536
No
2
No
120
240
Up
Any
integer
between 1
and 65536
No
1
No
120
240
Up
Any
integer
between 1
and 65536
Yes
2
1
120
240
Up
Any
integer
between 1
and 65536
Yes
1
1
120
240
Yes
0
No
120
240
No
0
No
120
240
General
purpose
TIM13,
TIM14
Complementary
output
16-bit
16-bit
16-bit
Basic
TIM6,
TIM7
16-bit
Up
Any
integer
between 1
and 65536
Lowpower
timer
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
16-bit
Up
1, 2, 4, 8,
16, 32, 64,
128
Table 2.29-1: Timer feature comparison
1.
The maximum timer clock is up to 480 MHz depending on TIMPRE bit in the RCC_CFGR register and
D2PRE1/2 bits in RCC_D2CFGR register.
2.
On AX58400 sales types (extended industrial temperature range), the maximum clock frequency is 300 MHz
for the high-resolution timer and 150 MHz for the other timers.
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2.29.1 High-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy timings, such as PWM
or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can be coupled by pairs
for deadtime insertion. It also features 5 fault inputs for protection purposes and 10 inputs to handle external events
such as current limitation, zero voltage or zero current switching.
The HRTIM1 timer is made of a digital kernel clocked at 480 MHz(a) The high-resolution is available on the 10
outputs in all operating modes: variable duty cycle, variable frequency, and constant ON time.
The slave timers can be combined to control multi-switch complex converters or operate independently to manage
multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events such as analog or digital
feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also offers specific
modes and features to offload the CPU: DMA requests, Burst mode controller, Push-pull and Resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost converters, either in voltage
or current mode, as well as lighting application (fluorescent or LED). It can also be used as a general purpose
timer, for instance to achieve high-resolution PWM-emulated DAC.
a. Up to 300 MHz for AX58400 sales types (extended industrial temperature range).
2.29.2 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6
channels. They have complementary PWM outputs with programmable inserted dead times. They can also be
considered as complete general-purpose timers. Their 4 independent channels can be used for:
• Input capture
• Output compare
• PWM generation (Edge- or Center-aligned modes)
• One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If
configured as 16-bit PWM generators, they have full modulation capability (0- 100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization
or event chaining.
TIM1 and TIM8 support independent DMA request generation.
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2.29.3 General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the AX58400 device (see Table 2.29-1 for
differences).
• TIM2, TIM3, TIM4, TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and TIM5. TIM2 and TIM5
are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a
16-bit auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent channels for input
capture/output compare, PWM or One-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the other general-purpose
timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or
event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling
quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.
• TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13, TIM14, TIM16 and
TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels for input
capture/output compare, PWM or One-pulse mode output. They can be synchronized with the TIM2, TIM3,
TIM4, TIM5 full-featured general-purpose timers or used as simple timebases.
2.29.4 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16bit time base.
TIM6 and TIM7 support independent DMA request generation.
2.29.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or
an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit auto-reload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous / One-shot mode
• Selectable software / hardware input trigger
• Selectable clock source:
• Internal clock source: LSE, LSI, HSI or APB clock
• External clock source over LPTIM input (working even with no internal clock source running, used by the
Pulse Counter Application)
• Programmable digital glitch filter
• Encoder mode
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2.29.6 Independent watchdogs
There are two independent watchdogs, one per domain. Each independent watchdog is based on a 12-bit
downcounter and 8-bit prescaler. It is clocked from an independent 32 KHz internal RC and as it operates
independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is
hardware- or software-configurable through the option bytes.
2.29.7 Window watchdogs
There are two window watchdogs, one per domain. Each window watchdog is based on a 7- bit downcounter that
can be set as free-running. It can be used as a watchdog to reset the device or each respective domain (configurable
in the RCC register), when a problem occurs. It is clocked from the main clock. It has an early warning interrupt
capability and the counter can be frozen in Debug mode.
2.29.8 SysTick timer
The devices feature two SysTick timers, one per CPU. These timers are dedicated to real- time operating systems,
but could also be used as a standard downcounter. It features:
• A 24-bit downcounter
• Auto-reload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.
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Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD
(binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master
clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the
calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy.
• Three anti-tamper detection pins with programmable filter.
• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event
on the timestamp pin, or by a tamper event, or by a switch to VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either from the V DD supply
when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data when V DD power is not
present. They are not reset by a system or power reset, or when the device wakes up from Standby mode.
The RTC clock sources can be:
• A 32.768 KHz external crystal (LSE)
• An external resonator or oscillator (LSE)
• The internal low-power RC oscillator (LSI, with typical frequency of 32 KHz)
• The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked
by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes.
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device
from the low-power modes.
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Inter-integrated circuit interface (I2C)
AX58400 device embeds four I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial I 2C bus. It controls all
I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and Master modes, multi-master capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK control
–
Address resolution protocol (ARP) support
–
SMBus alert
• Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be
independent from the PCLK reprogramming.
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
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Universal synchronous/asynchronous receiver transmitter (USART)
AX58400 device has four embedded universal synchronous receiver transmitters (USART1, USART2, USART3
and USART6) and four universal asynchronous receiver transmitters (UART4, UART5, UART7 and UART8).
Refer to Table 2.32-1for a summary of USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor
communication mode, single-wire Half-duplex communication mode and have LIN Master/Slave capability. They
provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to
communicate at speeds of up to 12.5 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816 compliant) and SPI-like
communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by
software and is disabled by default.
All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the MCU
from Stop mode. The wakeup from Stop mode is programmable and can be done on:
• Start bit detection
• Any received data frame
• A specific programmed data frame
• Specific TXFIFO/RXFIFO status when FIFO mode is enabled. All USART interfaces can be served by the
DMA controller.
(1)
USART1/2/3/6
UART4/5/7/8
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode (Master/Slave)
X
-
Smartcard mode
X
-
Single-wire Half-duplex communication
X
X
IrDA SIR ENDEC block
X
X
LIN mode
X
X
Dual clock domain and wakeup from low power mode
X
X
Receiver timeout interrupt
X
X
Modbus communication
X
X
Auto baud rate detection
X
X
Driver Enable
X
X
USART modes/features
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
Tx/Rx FIFO size
1. X = supported.
X
16
Table 2.32-1: USART features
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Low-power universal asynchronous receiver transmitter (LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire communication and modem
operations (CTS/RTS). It allows multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by
software and is disabled by default.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode.
The wakeup from Stop mode are programmable and can be done on:
• Start bit detection
• Any received data frame
• A specific programmed data frame
• Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 KHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in
Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption.
Higher speed clock can be used to reach higher baudrates.
LPUART interface can be served by the DMA controller.
Serial peripheral interface (SPI)/inter-integrated sound interfaces
(I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that allow communicating up
to 150 Mbits/s in Master and Slave modes, in Half-duplex, Full- duplex and Simplex modes. The 3-bit prescaler
gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. All SPI interfaces support NSS
pulse mode, TI mode, Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in Master
or Slave mode, in Simplex communication modes, and can be configured to operate with a 16-/32-bit resolution
as an input or output channel. Audio sampling frequencies from 8 KHz up to 192 KHz are supported. When either
or both of the I2S interfaces is/are configured in Master mode, the master clock can be output to the external
DAC/CODEC at 256 times the sampling frequency. All I 2S interfaces support 16x 8- bit embedded Rx and Tx
FIFOs with DMA capability.
Serial audio interfaces (SAI)
The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo or mono audio
protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF output is available when the
audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains
two independent audio sub-blocks. Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 KHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface. The SAI can work in
master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work
synchronously or asynchronously (with respect to the other one). The SAI can be connected with other SAIs to
work synchronously.
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SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These
standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound,
such as those defined by Dolby or DTS (up to 5.1).
The main SPDIFRX features are the following:
• Up to 4 inputs available
• Automatic symbol rate detection
• Maximum symbol rate: 12.288 MHz
• Stereo stream from 32 to 192 KHz supported
• Supports Audio IEC-60958 and IEC-61937, consumer applications
• Parity bit management
• Communication using DMA for audio samples
• Communication using DMA for control and user channel information
• Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data
stream. The user can select the wanted SPDIF input, and when a valid signal will be available, the SPDIFRX will
re-sample the incoming signal, decode the Manchester stream, recognize frames, sub-frames and blocks elements.
It delivers to the CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that will
be used to compute the exact sample rate for clock drift algorithms.
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless
Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are:
• Full-duplex communication mode
• automatic SWP bus state management (active, suspend, resume)
• configurable bitrate up to 2 Mbit/s
• automatic SOF, EOF and CRC handling SWPMI can be served by the DMA controller.
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Management Data Input/Output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
• 32 MDIO Registers addresses, each of which is managed using separate input and output data registers:
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
–
32 x 16-bit firmware read-only, MDIO write-only input data registers
• Configurable slave (port) address
• Independently maskable interrupts/events:
–
MDIO Register write
–
MDIO Register read
–
MDIO protocol error
• Able to operate in and wake up from Stop mode
SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System Specification Version 4.51 in
three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card specification version
4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a stack of MMC Version
4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed transfers between the
interface and the SRAM.
Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared message RAM memory
and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including event synchronized
time-triggered communication, global system time, and clock drift compensation. The FDCAN1 contains
additional registers, specific to the time triggered feature. The CAN FD option can be used together with eventtriggered and time-triggered CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs,
transmit buffers (and triggers for TT-FDCAN). This message RAM is shared between the two FDCAN1 and
FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock for both FDCAN1 and
FDCAN2 from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the
FDCAN1.
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Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. OTG-HS1 supports
both full-speed and high-speed operations, while OTG-HS2 supports only full-speed operations. They both
integrate the transceivers for full-speed operation (12 Mbit/s) and are able to operate from the internal HSI48
oscillator. OTG-HS1 features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When
using the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the OTG 2.0 specification.
They have software-configurable endpoint setting and supports suspend/resume. The USB OTG controllers require
a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.
The main features are:
• Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 9 bidirectional endpoints (including EP0)
• 16 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Battery Charging Specification Revision 1.2 support
• Internal FS OTG PHY support
• External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only)
The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60
MHz output.
• Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
• For OTG/Host modes, a power switch is needed in case bus-powered devices are connected
Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN
communications through an industry-standard medium-independent interface (MII) or a reduced mediumindependent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect
to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals
for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
• Supports 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and group addresses)
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• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2
Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time
stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time
High-definition multimedia interface (HDMI)-consumer electronics
control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control
(CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an environment. It is
specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain
independent from the CPU clock, allowing the HDMI-CEC controller to wakeup the MCU from Stop mode on
data reception.
Debug infrastructure
The devices offer a comprehensive set of debug and trace features on both cores to support software development
and system integration.
• Breakpoint debugging
• Code execution tracing
• Software instrumentation
• JTAG debug port
• Serial-wire debug port
• Trigger input and output
• Serial-wire trace port
• Trace port
• Arm® CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry standard debugging tools.
The debug infrastructure allows debugging one core at a time, or both cores in parallel.
The trace port performs data capture for logging and analysis.
A 4-Kbyte embedded trace FIFO (ETF) allows recording data and sending them to any com port. In Trace mode,
the trace is transferred by DMA to system RAM or to a high-speed interface (such as SPI or USB). It can even be
monitored by a software running on one of the cores. Unlike hardware FIFO mode, this mode is invasive since it
uses system resources which are shared by the processors.
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ESC (EtherCAT) Sub-system
2.45.1 Overview
The AX58400 implements a 2/3-port EtherCAT slave controller (ESC), licensed from Beckhoff Automation, with
9 Kbytes Process Data RAM, 8 Fieldbus Memory Management Units (FMMUs), 8 Sync-Managers and a 64-bit
Distributed Clock.
Port 0 and 1 integrate embedded Ethernet PHYs, and port 2 is an optional MII interface which are multi-function
pins shared with other interfaces (i.e. PWM, Hall, etc.). Packets are forwarded in the following order: Port 0>EtherCAT Processing Unit->Port 1->Port 2.
The AX58400 supports function register mirror from/to ESC memory space. The mirror registers located at process
data memory address from 0x3000 to 0x33FF.
For detailed information about the EtherCAT technology, the EtherCAT core mechanisms, and major features, we
refer to the official standard documentations and guidelines available from ETG (www.ethercat.org, ETG.1000),
IEC (http://www.iec.ch, IEC61158, IEC61784-2, IEC 61800-7), and Beckhoff (http://www.beckhoff.de, technical
specification) web sites.
The AX58400 requires a crystal (25MHz, ±25 PPM at room temperature) as the clock source. Internal PLL
generates the 100MHz clock for EtherCAT Slave Controller (ESC) and also for other functions.
The AX58400 has three reset sources. First, during the VCCK power-on, the internal Power-On-Reset (POR) can
generate a reset pulse to reset all the function blocks when the VCCK power pin rises to a certain threshold voltage
level. The second reset is RSTn pin, which is to do the fundamental reset. And third, EtherCAT command reset,
the EtherCAT master can send reset sequence to force AX58400 reset. AX58400 also supports a reset output
RSTO polarity bootstrap configuration (RSTO_POL).
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EtherCAT Slave Controller w/ Dual-Core MCU
2.45.2 Features
• 2/3-port EtherCAT Slave Controller (ESC) with 2 Integrated Fast Ethernet PHYs
• Standard EtherCAT Slave Controller (ESC)
–
8 Fieldbus Memory Management Units (FMMUs)
–
8 Sync Managers
–
64-bit distributed clock
–
9K bytes RAM
• Integrated Fast Ethernet PHYs
–
Compliant with IEEE 802.3/802.3u 100BASE-TX/100BASE-FX
–
PHY loopback mode
–
Supports twisted pair crossover detection and auto-correction (HP Auto-MDIX)
–
Automatic polarity detection and correction
• 3rd Ethernet MII Port for Flexible EtherCAT Network Configurations
• SPI Slave Interface for PDI and Function Access
• 3-channel PWM Controller for simple Motion Control
• Step & Direction Controller for simple Motion Control
• Incremental and Hall Encoder Interface for simple Motion Control
• Emergency Stop Input
• Configurable Watchdog for Outputs and Inputs Monitoring
• IRQ Event Output
• SPI Master Interface for ADC/DAC application
• Supports I2C Master Interface
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2.45.3
Block Diagram
Figure 2.45-1: ESC Sub-system Block Diagram
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2.45.4 ESC Configuration
2.45.4.1 Bootstrap Pins for Chip Configuration
The AX58400 supports five multi-function bootstrap pins (pin M1, M2, C11, L14 and M13) for five hardware
configurations, i.e. external I2C EEPROM size, ESC supported port number, RSTO polarity and integrated port
0/1 PHY media mode; and it also supports other three multi-function bootstrap pins (pin L11, E8, G12) for the
configuration of port 2 MII signals. User needs to utilize an external resistor to pull up / down these bootstrap pins.
Pins
Signal Name
M1
EEP_SIZE
M2
3PORT_MODE
B13
RSTO_POL
C11
PDI_EMU
L14
P0_FIBER
M13
P1_FIBER
L11
TX_SH [1]
E8
TX_SH [0]
G12
LINK_POL
Description
I2C EEPROM Size
0: 1 Kbit to 16Kbit
1: 32Kbit to 4Mbit
ESC port number
0: 2 ports mode
1: 3 ports mode
RSTO Reset Output Polarity
0: Active Low
1: Active High
Device emulation (0x0141.0)
0: Device status register is controlled by PDI
1: Device status register is identical to device control register
Port 0 PHY media mode
0: Copper mode
1: Fiber mode
Port 1 PHY Media mode
0: Copper mode
1: Fiber mode
Port 2 MII TXD Align position
2‘b00: Align with MCLK,
2’b01: Delay 1/4 phase with MCLK
2’b10: Delay 1/2 phase with MCLK
2’b11: Delay 3/4 phase with MCLK
Port 2 MII LINK Polarity
0: Active Low
1: Active High
Table 2.45-1: ESC Bootstrap Pins Configuration
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2.45.4.2 Hardware Configuration EEPROM (HWCFGEE)
The AX58400 I2C master controller supports the communication to external I 2C devices and an I2C Hardware
Configuration EEPROM Loader to support loading the EtherCAT Slave Information (ESI) from external I2C
EEPROM during chip reset. The AX58400 supports I2C EEPROM with EEPROM size from 1 Kbit (128 bytes) to
4 Mbit (500Kbytes).
The AX58400 I2C Hardware Configuration EEPROM layout is shown in following table.
EEPROM
EEPROM
Byte Offset
Word Offset
ESC Configuration Area
0x00
0x00
0x01
0x02
0x03
0x05 - 0x04
0x07 - 0x06
0x09 - 0x08
0x0A
0x0B
0x0C
0x0D
0x0F - 0x0E
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x13 - 0x10
0x09 – 0x08
0x17 - 0x14
0x0B – 0x0A
0x1B - 0x18
0x0D – 0x0C
0x1F - 0x1C
0x0F – 0x0E
0x27 - 0x20
0x13 – 0x10
Bootstrap Mailbox Config
0x29 - 0x28
0x14
0x2B - 0x2A
0x15
0x2D - 0x2C
0x16
0x2F - 0x2E
0x17
Mailbox Sync Man Config
0x31 - 0x30
0x18
0x33 - 0x32
0x19
0x35 - 0x34
0x1A
0x37 - 0x36
0x1B
0x39 - 0x38
0x1C
0x3F - 0x3A
0x1F – 0x1D
ESC Register
Offset
Parameter
PDI Control
ESC Configuration
(bit 2 is also mapped to ESC register 0x0110.2)
PDI Configuration
Sync/Latch [1:0] Configuration
Pulse Length of SyncSignals
Extended PDI Configuration
Configured Station Alias
Host Interface Extend Setting and Drive
Strength
Reserved, shall be zero
Reserved, shall be zero
Multi-Function Select and Drive Strength
Checksum
0x0140
0x0141
0x0150
0x0151
0x0983 - 0x0982
0x0153 - 0x0152
0x0013 - 0x0012
Vendor ID
Product Code
Revision Number
Serial Number
Reserved
Bootstrap Receive Mailbox Offset
Bootstrap Receive Mailbox Size
Bootstrap Send Mailbox Offset
Bootstrap Send Mailbox Size
Standard Receive Mailbox Offset
Standard Receive Mailbox Size
Standard Send Mailbox Offset
Standard Send Mailbox Size
Mailbox Protocol
Reserved
0x7B - 0x40
0x3D – 0x20
Reserved
0x7D - 0x7C
0x3E
Size
0x7F - 0x7E
0x3F
Version
ESC Category 1 (for AX58400 Bridge Access Configuration if used) *Note1
0x81 ~ 0x80
0x40
Category 1 Type (Default: 0x0001)
0x83 ~ 0x82
0x41
Category 1 Data Size (words) (Default: 0x0021)
0x84
0x42
MCTLR Access Control
94
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EtherCAT Slave Controller w/ Dual-Core MCU
EEPROM
Byte Offset
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
EEPROM
Word Offset
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
Parameter
PXCFGR Access Control
PTAPPR Access Control
PTBPPR Access Control
PPCR Access Control
PBBMR Access Control
P1CTRLR Access Control
P1SHR Access Control
P1HPWR Access Control
P2CTRLR Access Control
P2SHR Access Control
P2HPWR Access Control
P3CTRLR Access Control
P3SHR Access Control
P3HPWR Access Control
SGTR Access Control
SHPWR Access Control
TDLYR Access Control
STNR Access Control
SCFGR Access Control
SCTRLR Access Control
SCNTR Access Control
ECNTVR Access Control
ECNSTR Access Control
ELATR Access Control
EMODR Access Control
ECLRR Access Control
HALSTR Access Control
WTR Access Control
WCFGR Access Control
WTPVCR Access Control
WMSPR Access Control
WMMR Access Control
WOMR Access Control
WOER Access Control
WOPR Access Control
WTPVR Access Control
SPICFGR Access Control
SPIBRR Access Control
SPIDBSR Access Control
SPIDTR Access Control
SPIRPTR Access Control
SPILTR Access Control
SPIPRLR Access Control
SPI01BCR Access Control
SPI23BCR Access Control
SPI45BCR Access Control
SPI67BCR Access Control
SPI03SSR Access Control
95
ESC Register
Offset
0x0581
0x0582
0x0583
0x0584
0x0585
0x0586
0x0587
0x0588
0x0589
0x058A
0x058B
0x058C
0x058D
0x058E
0x058F
0x0590
0x0591
0x0592
0x0593
0x0594
0x0595
0x0596
0x0597
0x0598
0x0599
0x059A
0x059B
0x059C
0x059D
0x059E
0x059F
0x05A0
0x05A1
0x05A2
0x05A3
0x05A4
0x05A5
0x05A6
0x05A7
0x05A8
0x05A9
0x05AA
0x05AB
0x05AC
0x05AD
0x05AE
0x05AF
0x05B0
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EtherCAT Slave Controller w/ Dual-Core MCU
EEPROM
Byte Offset
0xB5
0xB6
0xB7
0xB8
EEPROM
Word Offset
Parameter
SPI47SSR Access Control
SPIINTSR Access Control
0x5B
SPITSR Access Control
SPIPOSR Access Control
0x5C
SPI Data Status (SPIDSR and SPIDSMR)
0xB9
Access Control
SPIC0DR Access Control
0xBA
0x5D
SPIC1DR Access Control
0xBB
SPIC2DR Access Control
0xBC
0x5E
SPIC3DR Access Control
0xBD
SPIC4DR Access Control
0xBE
0x5F
SPIC5DR Access Control
0xBF
SPIC6DR Access Control
0xC0
0x60
SPIC7DR Access Control
0xC1
0xC2
SPIMCR Access Control
0x61
0xC3
INTCR Access Control
0xC4
INTSR Access Control
0x62
0xC5
Function Mirror Enable
Other ESC Categories Information (Subdivided in Categories)
…
Category Strings
Category Generals
Category FMMU
Category SyncManager
Category Tx - / RxPDO for each PDO
ESC Register
Offset
0x05B1
0x05B2
0x05B3
0x05B4
0x05B5
0x05B6
0x05B7
0x05B8
0x05B9
0x05BA
0x05BB
0x05BC
0x05BD
0x05BE
0x05BF
0x05C0
0x05C1
Table 2.45-2: ESC I2C EEPROM Layout
Note 1: Reserved words or reserved bits of the ESC Configuration Area should be filled with 0.
Note 2: When (re-) configuring the EEPROM from an EtherCAT master system special care must be taken. Not
every master allows writing a category 1 entry to the EEPROM. There are different ways to write this
into the EEPROM for automatically loading access control configuration when AX58400 booting.
1. Use preprogrammed I2C EEPROM.
2. Use a different category, e.g., 2049, first. Then overwrite the upper byte with 0 with a single EEPROM
byte writes.
The AX58400 HWCFGEE contents from offset 0x00 to 0x7F are mandatory, as well as the general category (at
least the minimum I2C EEPROM size is 2Kbit, and for the complex devices with many categories should be
equipped with 32 Kbit EEPROMs or larger one). The ESC Configuration Area is used for AX58400 hardware
configuration. All other areas are used by the EtherCAT master or the local application.
The ESC Configuration Area (EEPROM offset 0x00 to 0x0F) is automatically read by AX58400 after power-on
or reset. It contains the PDI configuration, Distributed Clocks settings, and Configured Station Alias. The
consistency of the ESC Configuration Area data is secured with a checksum.
The EtherCAT Master can invoke reloading the EEPROM contents. In this case, the Configured Station Alias
register 0x0012:0x0013 and ESC Configuration register bits 0x0141 [1,4,5,6,7] (enhanced link detection) are not
transferred into the registers. They are only transferred at the initial EEPROM loading after power-on or reset.
To use AX58400 bridge functionalities, users should define the Bridger Access Configuration parameters in the
first category located at EEPROM offset 0x80. The Category Type must be 0x0001and the Category Data Size
must be 0x0021 so the AX58400 will automatically load the EEPROM Bridger Access Configuration parameters
into the Bridge Access Configuration registers memory area starting at 0x0580 after power-on or reset.
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2.45.4.3 EEPROM Contents Detailed Descriptions
PDI Control (0x00)
Bit
7:0
Description
PDI Control [7:0]
0x00: Interface deactivated (no PDI)
0x04: Digital I/O
0x05: SPI Slave
0x08: 16-bit Asynchronous Local Bus
0x09: 8-bit Asynchronous Local Bus
Others: reserved
ESC Configuration (0x01)
Bit
0
1
3:2
4
5
6
7
Description
Device emulation enables (control of AL status)
Enhanced Link detection all ports
Reserved
Enhanced Link port 0
Enhanced Link port 1
Enhanced Link port 2
Reserved
PDI Configuration (0x02)
Digital I/O
Bit
0
1
2
3
5:4
7:6
Description
OUTVALID polarity
OUTVALID mode
Unidirectional/Bidirectional mode
Watchdog behavior
Input DATA is sampled
Output DATA is updated
SPI Slave
Bit
1:0
3:2
4
5
7:6
Description
SPI mode
SPI_IRQ output driver/polarity
SPI_SEL polarity
Data Out sample mode
Reserved
Asynchronous Local Bus
Bit
Description
1:0
BUSY/RDY driver/polarity
3:2
IRQ driver/polarity
4
BHE/Byte Enable polarity
7:5
Reserved
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Sync/Latch[1:0] Configuration (0x03)
Bit
1:0
2
3
5:4
6
7
Description
SYNC0 output driver/polarity
SYNC0/LATCH0 configuration
SYNC0 mapped to AL Event Request
SYNC1 output driver/polarity
SYNC1/LATCH1 configuration
SYNC1 mapped to AL Event Request
Pulse Length SyncSignals (0x05 - 0x04)
Bit
15:0
Description
Pulse length of SyncSignal
Extended PDI Configuration (0x07 - 0x06)
Digital I/O / SPI Slave (for GPIO)
Bit Description
Digital I/O or GPIO
Digital I/O or GPIO are configured in pairs (1:0) as inputs or outputs:
0
0: Input
1: Output
1
3:2 pair (0: Input, 1: Output)
2
5:4 pair (0: Input, 1: Output)
3
7:6 pair (0: Input, 1: Output)
4
9:8 pair (0: Input, 1: Output)
5
11:10 pair (0: Input, 1: Output)
6
13:12 pair (0: Input, 1: Output)
7
15:14 pair (0: Input, 1: Output)
8
17:16 pair (0: Input, 1: Output)
9
19:18 pair (0: Input, 1: Output)
10
21:20 pair (0: Input, 1: Output)
11
23:22 pair (0: Input, 1: Output)
12
25:24 pair (0: Input, 1: Output)
13
27:26 pair (0: Input, 1: Output)
14
29:28 pair (0: Input, 1: Output)
15
31:30 pair (0: Input, 1: Output)
Asynchronous Local Bus
Bit
Description
0
Read BUSY delay
1
Perform internal write
10:2 Reserved
11
23:22 pair (data bus 8-bit width only) (0: Input, 1: Output)
12
25:24 pair (data bus 8-bit width only) (0: Input, 1: Output)
13
27:26 pair (data bus 8-bit width only) (0: Input, 1: Output)
14
29:28 pair (data bus 8-bit width only) (0: Input, 1: Output)
15
31:30 pair (data bus 8-bit width only) (0: Input, 1: Output)
Configured Station Alias (0x09 - 0x08)
Bit
15:0
Description
Alias Address used for node addressing
98
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Host Interface Extend Setting and Drive Strength (0x0A)
Digital I/O
Bit
Description
4:0
Reserved
Control Driving Select:
5
0: 4mA
1: 8mA
IO [9:0] Driving Select:
6
0: 4mA
1: 8mA
IO [15:10] Driving Select:
7
0: 4mA
1: 8mA
SPI Slave / Asynchronous Local Bus
Bit
Description
Interrupt Edge Pulse Length (INTP_LEN)
3:0
Interrupt Edge Pulse = (INTP_LEN+1) * 100ns
The trigger type of interrupt signal, SINT / LINT
4
0: Level trigger.
1: Edge trigger.
Control Driving Select:
5
0: 4mA
1: 8mA
IO [9:0] Driving Select:
6
0: 4mA
1: 8mA
IO [15:10] Driving Select:
7
0: 4mA
1: 8mA
Multi-Function Select and Drive Strength (0x0D)
Bit
0
1
2
3
4
5
Description
IO [9:0] select:
0: IO [9:0]
1: MTRG, MDRLD, MSS [3:0], MINT, MMISO, MMOSI, MSCLK,
Note: in Local Bus mode this bit no function
IO [15:10] (SPI slave separates) select:
0: IO [15:10]
1: IO [15:14], FMOSI, FSCLK, FMISO, SFINT
Note: in Local Bus mode this bit no function
IO [21:16] select:
0: IO [21:16]
1: PULA, PULB, PULZ, PULZ, PULAB, IO [16]
Note: in Local Bus mode this bit no function
IO [25:22] select:
0: IO [25:22]
1: PWM2L, PWM2H, PWM3L, PWM3H
Note: in Local Bus 16 bits mode this bit no function
IO [28:26] select:
0: IO [28:26]
1: EM, PWM1L, PWM1H
Note: in Local Bus 16 bits mode this bit no function
IO [31:29] select:
0: IO [31:29]
1: ENCZ, ENCB, ENCA
Note: in Local Bus 16 bits mode this bit no function
99
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
IO [21:16] Driving Select:
0: 4mA
1: 8mA
IO [31:22] Driving Select:
7
0: 4mA
1: 8mA
Note: When MII port 2 enable, the IO [31:16] pins are forced to MII port 2
6
Checksum (0x0F - 0x0E)
Bit
15:0
Description
Checksum
Low byte contains remainder of division of EEPROM offset 0x00 to 0x0D as unsigned
number divided by the polynomial X^8+X^2+X+1 (initial value 0xFF)
For debugging purposes, it is possible to disable the checksum validation with a checksum
value of 0x88A4. Note that NEVER use this for production!
Category 1 Type (0x81 - 0x80)
Bit
15:0
Description
Category 1 Type
MUST be 0x0001
Category 1 Data Size (0x83 - 0x82)
Bit
15:0
Description
Category 1 Data Size (words)
MUST be 0x0021
MCTLR Access Control (0x84)
Bit
3:0
4
7:5
Description
Sync. Source Select
0x0: Always triggered
0x1: Start Of Frame (SOF)
0x2: End Of Frame (EOF)
0x3: SYNC0 signal
0x4: LATCH0 signal
0x5: SYNC1 signal
0x6: LATCH1 signal
0x7: After write access
0x8: Trigger when data value changes
0x9: PDI Chip Select Assert
0xA: PDI Chip Select De-assert
0xB: FUNC Chip Select Assert
0xC: FUNC Chip Select De-assert
0xD: Trigger at start of MFC PWM cycle
Others: Always triggered
ESC Access Enable
0: Writeable with Function Host Interface
1: Writeable with ESC
Reserved
The Bit Definitions of the other parameters from EEPROM offset 0x85 to 0xC4 are the same as the Bit
Definitions of EEPROM offset 0x84.
100
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Function mirror enable (0xC5)
Bit
0
1
2
3
7:4
Description
PWM function register mirror:
0: Disable PWM function register mirror
1: Enable PWM function register mirror
ENC function register mirror:
0: Disable ENC function register mirror
1: Enable ENC function register mirror
SPI Master function register mirror:
0: Disable SPI Master function register mirror
1: Enable SPI Master function register mirror
IO Watchdog function register mirror:
0: Disable IO Watchdog function register mirror
1: Enable IO Watchdog function register mirror
Reserved
101
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
2.45.5 Memory Map
This section introduces the memory mapping in AX58400. AX58400 provides SPI and Local Bus slave interfaces
for both ESC PDI and Function to access the internal registers. Section 2.45.5.1 introduces the ESC memory map
which can be accessed by PDI SPI or Local bus interface ,and section 2.45.5.2 introduces the Function register
map which can be accessed by Function SPI or Local Bus interface. Due to the Function registers can be accessed
by PDI interface and EtherCAT Master directly. So, section 2.45.5.3 introduces the relationship between Function
and ESC PDI through the Bridge function.
2.45.5.1 ESC Memory Map
ESC Address
Length
Description
(Bytes)
0x0000
0x0001
0x0002
0x0004
0x0005
0x0006
0x0007
0x0008
1
1
2
1
1
1
1
2
0x0010
0x0012
2
2
0x0020
0x0021
0x0030
0x0031
1
1
1
1
0x0040
0x0041
0x0100
0x0108
0x0110
1
1
4
2
2
0x0120
0x0130
0x0134
0x0138
0x0139
2
2
2
1
1
0x0140
0x0141
0x0150
0x0151
0x0152
1
1
1
1
2
0x0200
0x0204
0x0210
0x0220
2
4
2
4
0x0300
0x0308
4x2
4x1
ESC Information
Type
Revision
Build
FMMUs supported
SyncManagers supported
RAM Size
Port Descriptor
ESC Features supported
Station Address
Configured Station Address
Configured Station Alias
Write Protection
Write Register Enable
Write Register Protection
ESC Write Enable
ESC Write Protection
Data Link Layer
ESC Reset ECAT
ESC Reset PDI
ESC DL Control
Physical Read/Write Offset
ESC DL Status
Application Layer
AL Control
AL Status
AL Status Code
RUN LED Override
ERR LED Override
PDI
PDI Control
ESC Configuration
PDI Configuration
Sync/Latch PDI Configuration
Extended PDI Configuration
Interrupts
ECAT Event Mask
AL Event Mask
ECAT Event Request
AL Event Request
Error Counters
RX Error Counter [3:0]
Forwarded RX Error counter [3:0]
102
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
0x030C
0x030D
0x030E
0x0310
1
1
1
4x1
0x0400
0x0410
0x0420
0x0440
0x0442
0x0443
2
2
2
2
1
1
0x0500
0x0501
0x0502
0x0504
0x0508
1
1
2
4
4
0x0510
0x0512
0x0513
0x0514
0x0516
0x0517
0x0518
2
1
1
2
1
1
4
0x0580
0x0581
0x0582
0x0583
0x0584
0x0585
0x0586
0x0587
0x0588
0x0589
0x058A
0x058B
0x058C
0x058D
0x058E
0x058F
0x0590
0x0591
0x0592
0x0593
0x0594
0x0595
0x0596
0x0597
0x0598
0x0599
0x059A
0x059B
0x059C
0x059D
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ECAT Processing Unit Error Counter
PDI Error Counter
PDI Error Code
Lost Link Counter [3:0]
Watchdogs
Watchdog Divider
Watchdog Time PDI
Watchdog Time Process Data
Watchdog Status Process Data
Watchdog Counter Process Data
Watchdog Counter PDI
I2C EEPROM Interface
EEPROM Configuration
EEPROM PDI Access State
EEPROM Control/Status
EEPROM Address
EEPROM Data
MII Management Interface
MII Management Control/Status
PHY Address
PHY Register Address
PHY Data
MII Management ECAT Access State
MII Management PDI Access State
PHY Port Status
Bridge Access Configuration
MCTLR Access Control Register
PXCFGR Access Control Register
PTAPPR Access Control Register
PTBPPR Access Control Register
PPCR Access Control Register
PBBMR Access Control Register
P1CTRLR Access Control Register
P1SHR Access Control Register
P1HPWR Access Control Register
P2CTRLR Access Control Register
P2SHR Access Control Register
P2HPWR Access Control Register
P3CTRLR Access Control Register
P3SHR Access Control Register
P3HPWR Access Control Register
Step Gap Time Access Control Register
SHPWR Access Control Register
TDLYR Access Control Register
Step Target Number Access Control Register
SCFGR Access Control Register
SCTRLR Access Control Register
Step Counter Content Access Control Register
Encoder Counter Value Access Control Register
Encoder Constant Access Control Register
Encoder Latched Access Control Register
EMODR Access Control Register
ECLRR Access Control Register
HALSTR Access Control Register
Watchdog Timer Access Control Register
WCFGR Access Control Register
103
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
0x059E
0x059F
0x05A0
0x05A1
0x05A2
0x05A3
0x05A4
0x05A5
0x05A6
0x05A7
0x05A8
0x05A9
0x05AA
0x05AB
0x05AC
0x05AD
0x05AE
0x05AF
0x05B0
0x05B1
0x05B2
0x05B3
0x05B4
0x05B5
0x05B6
0x05B7
0x05B8
0x05B9
0x05BA
0x05BB
0x05BC
0x05BD
0x05BE
0x05BF
0x05C0
0x05C1
0x0600:0x067F
+0x0
+0x4
+0x6
+0x7
+0x8
+0xA
+0xB
+0xC
+0xD
0x0800:0x083F
+0x0
+0x2
+0x4
+0x5
+0x6
+0x7
0x0900:0x09FF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0x0900
4
4
2
1
1
2
1
1
1
3
2
2
1
1
1
1
WTPVCR Access Control Register
Watchdog monitored Polarity Access Control Register
Watchdog monitored Mask Access Control Register
Watchdog Output Mask Access Control Register
Watchdog Output Enable Access Control Register
Watchdog Output Polarity Access Control Register
Watchdog Timer Peak value Access Control Register
SPICFGR Access Control Register
SPIBRR Access Control Register
SPIDBSR Access Control Register
SPIDTR Access Control Register
SPIRPTR Access Control Register
SPILTR Access Control Register
SPIPRLR Access Control Register
SPI01BCR Access Control Register
SPI23BCR Access Control Register
SPI45BCR Access Control Register
SPI67BCR Access Control Register
SPI03SSR Access Control Register
SPI47SSR Access Control Register
SPINTSR Access Control Register
SPITSR Access Control Register
SPIPOSR Access Control Register
SPI Data Status (SPIDSR and SPIDSMR) Access Control Register
SPIC0DR Access Control Register
SPIC1DR Access Control Register
SPIC2DR Access Control Register
SPIC3DR Access Control Register
SPIC4DR Access Control Register
SPIC5DR Access Control Register
SPIC6DR Access Control Register
SPIC7DR Access Control Register
SPIMCR Access Control Register
INTCR Access Control Register
INTSR Access Control Register
Function Mirror Enable Register
FMMU[7:0]
Logical Start Address
Length
Logical Start bit
Logical Stop bit
Physical Start Address
Physical Start bit
Type
Activate
Reserved
SyncManager[7:0]
Physical Start Address
Length
Control Register
Status Register
Activate
PDI Control
Distributed Clocks (DC)
DC – Receive Times
Receive Time Port 0
104
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
0x0904
0x0908
0x090C
0x0910
0x0918
0x0920
0x0928
0x092C
0x0930
0x0932
0x0934
0x0935
0x0980
0x0981
0x0982
0x0984
0x098E
0x098F
0x0990
0x0998
0x09A0
0x09A4
0x09A8
0x09A9
0x09AE
0x09AF
0x09B0
0x09B8
0x09C0
0x09C8
0x09F0
0x09F8
0x09FC
0x0E00
0x0E08
0x0F00
0x0F10
0x0F18
0x0F80
0x1000
0x1000
0x3000
0x3002
0x3004
0x3006
4
4
4
Receive Time Port 1
Receive Time Port 2
Receive Time Port 3
DC – Time Loop Control Unit
4(W)/8(R) System Time
8
Receive Time ECAT Processing Unit
8
System Time Offset
4
System Time Delay
4
System Time Difference
2
Speed Counter Start
2
Speed Counter Diff
1
System Time Difference Filter Depth
1
Speed Counter Filter Depth
DC – Cyclic Unit Control
1
Cyclic Unit Control
DC – SYNC Out Unit
1
Activation
2
Pulse Length of SyncSignals
1
Activation Status
1
SYNC0 Status
1
SYNC1 Status
8
Start Time Cyclic Operation/Next SYNC0 Pulse
8
Next SYNC1 Pulse
4
SYNC0 Cycle Time
4
SYNC1 Cycle Time
DC – Latch In Unit
1
Latch0 Control
1
Latch1 Control
1
Latch0 Status
1
Latch1 Status
8
Latch0 Time Positive Edge
8
Latch0 Time Negative Edge
8
Latch1 Time Positive Edge
8
Latch1 Time Negative Edge
DC – SyncManager Event Times
4
EtherCAT Buffer Change Event Time
4
PDI Buffer Start Event Time
4
PDI Buffer Change Event Time
ESC specific
8
Product ID
8
Vendor ID
Digital Input/Output
4
Digital I/O Output Data
4
General Purpose Outputs
4
General Purpose Inputs
User RAM/Extended ESC features
128
User RAM/Extended ESC Features
Process Data RAM
4
Digital I/O Input Data
8KB
Process Data RAM
Function Register Mirror (Refer to Section 2.45.5.2)
Write / Read
2
Motor Control Register
2
PWM Pulse X Configure Register
2
PWM Trigger A Pulse Position Register
2
PWM Trigger B Pulse Position Register
105
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
0x3008
0x300A
0x300C
0x300E
0x3010
0x3012
0x3014
0x3016
0x3018
0x301A
0x301C
0x3020
0x3024
0x3026
0x3028
0x302C
0x302E
0x3040
0x3044
0x304C
0x304E
0x3060
0x3064
0x3066
0x3068
0x306C
0x3070
0x3074
0x3078
0x3080
0x3082
0x3084
0x3086
0x3088
0x308A
0x308C
0x3090
0x3092
0x3094
0x3096
0x3098
0x309A
0x30B0
0x30B8
0x30C0
0x30C8
0x30D0
0x30D8
0x30E0
0x30E8
0x30F2
0x3100
0x3102
2
2
2
2
2
2
2
2
2
2
2
4
2
2
4
2
2
4
4
2
2
4
2
2
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
8
8
8
8
8
8
8
8
2
2
2
0x3230
0x3248
4
4
PWM Period Cycle Register
PWM Pulse Break Before Make Register
PWM1Control Register
PWM1 Counter Shift Register
PWM1 High Pulse Width Register
PWM2 Control Register
PWM2 Shift Register
PWM2 High Pulse Width Register
PWM3 Control Register
PWM3 Counter Shift Register
PWM3 High Pulse Width Register
Step Gap Time Register
Step High Pulse Width Register
Direction Transform Delay Step Register
Step Target Number Register
Step Configure Register
Step Control Register
Encoder Counter Value Register
Encoder Constant Register
Encoder Mode configuration Register
Encoder Clear Register
Watchdog Timer Register
Watchdog Control Register
Watchdog Timer Peak Value Clear Register
Watchdog Monitored Signals Polarity Register
Watchdog Monitored Signals Mask Register
Watchdog Output Mask Register
Watchdog Output Enable Register
Watchdog Output Polarity Register
SPI Configure Register
SPI Baud Rate Register
SPI Delay Byte and SS Register
SPI Delay Transfer Register
SPI RDY / Pulse Time Register
SPI LDAC Time Register
SPI Pulse/ RDY/ LDAC Register
SPI 0/1 Byte Count Register
SPI 2/3 Byte Count Register
SPI 4/5 Byte Count Register
SPI 6/7 Byte Count Register
SPI 0/1/2/3 slave Select Register
SPI 4/5/6/7 slave Select Register
SPI Channel 0 Data Register
SPI Channel 1 Data Register
SPI Channel 2 Data Register
SPI Channel 3 Data Register
SPI Channel 4 Data Register
SPI Channel 5 Data Register
SPI Channel 6 Data Register
SPI Channel 7 Data Register
SPI Master Control Register
Interrupt Configure Register
Interrupt Status Register
Read Only
Step Counter Content Register
Encoder Latched Register
106
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
0x3250
0x327C
0x32A8
0x32AA
0x32AC
0x32AE
0x32B0
0x32B8
0x32C0
0x32C8
0x32D0
0x32D8
0x32E0
0x32E8
0x32F0
2
4
2
2
2
2
8
8
8
8
8
8
8
8
2
Hall State Register
Watchdog Timer Peak Value Register
SPI Interrupt Status Register
SPI Timeout Status Register
SPI Pulse Overrun Status Register
SPI Data Status Register
SPI Channel 0 Data Register
SPI Channel 1 Data Register
SPI Channel 2 Data Register
SPI Channel 3 Data Register
SPI Channel 4 Data Register
SPI Channel 5 Data Register
SPI Channel 6 Data Register
SPI Channel 7 Data Register
SPI Data Status Mirror Register
Table 2.45-3: ESC Memory Map
107
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
2.45.5.2 Function Register Map
Address
Offset
0x000
0x002
0x004
0x006
0x008
0x00A
0x00C
0x00E
0x010
0x012
0x014
0x016
0x018
0x01A
0x01C
0x020
0x022
0x024
0x026
0x028
0x02A
0x02C
0x02E
0x030
0x032
0x040
0x042
0x044
0x046
0x048
0x04A
0x04C
0x04E
0x050
0x060
0x062
0x064
0x066
0x068
0x06A
0x06C
0x06E
0x070
0x072
0x074
0x076
0x078
0x07A
0x07C
0x07E
0x080
0x082
0x084
Name
MCTLR
PXCFGR
PTAPPR
PTBPPR
PPCR
PBBMR
P1CTRLR
P1SHR
P1HPWR
P2CTRLR
P2SHR
P2HPWR
P3CTRLR
P3SHR
P3HPWR
SGTLR
SGTHR
SHPWR
TDLYR
STNLR
STNHR
SCFGR
SCTRLR
SCNTLR
SCNTHR
ECNTVLR
ECNTVHR
ECNSTLR
ECNSTHR
ELATLR
ELATHR
EMODR
ECLRR
HALSTR
WTLR
WTHR
WCFGR
WTPVCR
WMPLR
WMPHR
WMMLR
WMMHR
WOMLR
WOMHR
WOELR
WOEHR
WOPLR
WOPHR
WTPVLR
WTPVHR
SPICFGR
SPIBRR
SPIDBSR
Description
Motor Control Register
PWM Pulse X Configure Register
PWM Trigger A Pulse Position Register
PWM Trigger B Pulse Position Register
PWM Period Cycle Register
PWM Pulse Break Before Make Register
PWM1Control Register
PWM1 Counter Shift Register
PWM1 High Pulse Width Register
PWM2 Control Register
PWM2 Shift Register
PWM2 High Pulse Width Register
PWM3 Control Register
PWM3 Counter Shift Register
PWM3 High Pulse Width Register
Step Gap Time Low Register
Step Gap Time High Register
Step High Pulse Width Register
direction Transform Delay step Register
Step Target Number Low Word Register
Step Target Number High Word Register
Step Configure Register
Step Control Register
Step Counter Content Low Register
Step Counter Content High Register
Encoder Counter value Low Register
Encoder Counter value High Register
Encoder Constant Low Register
Encoder Constant High Register
Encoder Latched Low Register
Encoder Latched High Register
Encoder Mode Configuration Register
Encoder Clear Register
Hall State Register
Watchdog Timer Low Register
Watchdog Timer High Register
Watchdog Configure Register
Watchdog Timer Peak Value Clear Register
Watchdog Monitored Polarity Low Register
Watchdog Monitored Polarity High Register
Watchdog Monitored Mask Low Register
Watchdog Monitored Mask High Register
Watchdog Output Mask Low Register
Watchdog Output Mask High Register
Watchdog Output Enable Low Register
Watchdog Output Enable High Register
Watchdog Output Polarity Low Register
Watchdog Output Polarity High Register
Watchdog Timer Peak Value Low Register
Watchdog Timer Peak Value High Register
SPI Configure Register
SPI Baud Rate Register
SPI Delay Byte and SS Register
108
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Address
Offset
0x086
0x088
0x08A
0x08C
0x090
0x092
0x094
0x096
0x098
0x09A
0x0A8
0x0AA
0x0AC
0x0AE
0x0B0
0x0B8
0x0C0
0x0C8
0x0D0
0x0D8
0x0E0
0x0E8
0x0F0
0x0F2
0x100
0x102
0x104
0x106
Others
Name
SPIDTR
SPIRPTR
SPILTR
SPIPRLR
SPI01BCR
SPI23BCR
SPI45BCR
SPI67BCR
SPI03SSR
SPI47SSR
SPINTSR
SPITSR
SPIPOSR
SPIDSR
SPIC0DR
SPIC1DR
SPIC2DR
SPIC3DR
SPIC4DR
SPIC5DR
SPIC6DR
SPIC7DR
SPIDSMR
SPIMCR
INTCR
INTSR
ESTOR
HSTSR
Reserved
Description
SPI Delay Transfer Register
SPI RDY / Pulse Time Register
SPI LDAC Time Register
SPI Pulse/ RDY/ LDAC Register
SPI 0/1 Byte Count Register
SPI 2/3 Byte Count Register
SPI 4/5 Byte Count Register
SPI 6/7 Byte Count Register
SPI 0/1/2/3 slave Select Register
SPI 4/5/6/7 slave Select Register
SPI Interrupt Status Register
SPI Timeout Status Register
SPI Pulse Overrun Status Register
SPI Data Status Register
SPI Channel 0 Data Register
SPI Channel 1 Data Register
SPI Channel 2 Data Register
SPI Channel 3 Data Register
SPI Channel 4 Data Register
SPI Channel 5 Data Register
SPI Channel 6 Data Register
SPI Channel 7 Data Register
SPI Data Status Mirror Register
SPI Master Control Register
Interrupt Configure Register
Interrupt Status Register
ESC State Override register
Host interface Status Register
Reserved
Table 2.45-4: ESC Function Register Map
109
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
2.45.5.3 Memory Map between ESC Memory and Function Registers
Function
Address
0x000
0x002
0x004
0x006
0x008
0x00A
0x00C
0x00E
0x010
0x012
0x014
0x016
0x018
0x01A
0x01C
0x020
0x022
0x024
0x026
0x028
0x02A
0x02C
0x02E
0x030
0x032
0x040
0x042
0x044
0x046
0x048
0x04A
0x04C
0x04E
0x050
0x060
0x062
0x064
0x066
0x068
0x06A
0x06C
0x06E
0x070
0x072
0x074
0x076
0x078
0x07A
0x07C
0x07E
0x080
0x082
0x084
ESC Address
R/W
RO
0x3000
0x3002
0x3004
0x3006
0x3008
0x300A
0x300C
0x300E
0x3010
0x3012
0x3014
0x3016
0x3018
0x301A
0x301C
0x3020
-
0x3024
0x3026
-
0x3028
-
0x302C
0x302E
-
-
0x3230
0x3040
-
0x3044
-
-
0x3248
0x304C
0x304E
-
0x3250
0x3060
-
0x3064
0x3066
-
0x3068
-
0x306C
-
0x3070
-
0x3074
-
0x3078
-
-
0x327C
0x3080
0x3082
0x3084
-
Name
Description
MCTLR
PXCFGR
PTAPPR
PTBPPR
PPCR
PBBMR
P1CTRLR
P1SHR
P1HPWR
P2CTRLR
P2SHR
P2HPWR
P3CTRLR
P3SHR
P3HPWR
SGTLR
SGTHR
SHPWR
TDLYR
STNLR
STNHR
SCFGR
SCTRLR
SCNTLR
SCNTHR
ECNTVLR
ECNTVHR
ECNSTLR
ECNSTHR
ELATLR
ELATHR
EMODR
ECLRR
HALSTR
WTLR
WTHR
WCFGR
WTPVCR
WMPLR
WMPHR
WMMLR
WMMHR
WOMLR
WOMHR
WOELR
WOEHR
WOPLR
WOPHR
WTPVLR
WTPVHR
SPICFGR
SPIBRR
SPIDBSR
110
Motor Control Register
PWM Pulse X Configure Register
PWM Trigger A Pulse Position Register
PWM Trigger B Pulse Position Register
PWM Period Cycle Register
PWM Pulse Break Before Make Register
PWM1Control Register
PWM1 Counter Shift Register
PWM1 High Pulse Width Register
PWM2 Control Register
PWM2 Shift Register
PWM2 High Pulse Width Register
PWM3 Control Register
PWM3 Counter Shift Register
PWM3 High Pulse Width Register
Step Gap Time Low Register
Step Gap Time High Register
Step High Pulse Width Register
direction Transform Delay step Register
Step Target Number Low Word Register
Step Target Number High Word Register
Step Configure Register
Step Control Register
Step Counter Content Low Register
Step Counter Content High Register
Encoder Counter value Low Register
Encoder Counter value High Register
Encoder Constant Low Register
Encoder Constant High Register
Encoder Latched Low Register
Encoder Latched High Register
Encoder Mode Configuration Register
Encoder Clear Register
Hall State Register
Watchdog Timer Low Register
Watchdog Timer High Register
Watchdog Configure Register
Watchdog Timer Peak Value Clear Register
Watchdog Monitored Polarity Low Register
Watchdog Monitored Polarity High Register
Watchdog Monitored Mask Low Register
Watchdog Monitored Mask High Register
Watchdog Output Mask Low Register
Watchdog Output Mask High Register
Watchdog Output Enable Low Register
Watchdog Output Enable High Register
Watchdog Output Polarity Low Register
Watchdog Output Polarity High Register
Watchdog Timer Peak Value Low Register
Watchdog Timer Peak Value High Register
SPI Configure Register
SPI Baud Rate Register
SPI Delay Byte and SS Register
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Function
Address
0x086
0x088
0x08A
0x08C
0x090
0x092
0x094
0x096
0x098
0x09A
0x0A8
0x0AA
0x0AC
0x0AE
0x0B0
0x0B8
0x0C0
0x0C8
0x0D0
0x0D8
0x0E0
0x0E8
0x0F0
0x0F2
0x100
0x102
ESC Address
R/W
RO
0x3086
0x3088
0x308A
0x308C
0x3090
0x3092
0x3094
0x3096
0x3098
0x309A
0x32A8
0x32AA
0x32AC
0x32AE
0x30B0
0x32B0
0x30B8
0x32B8
0x30C0
0x32C0
0x30C8
0x32C8
0x30D0
0x32D0
0x30D8
0x32D8
0x30E0
0x32E0
0x30E8
0x32E8
0x32F0
0x30F2
0x3100
0x3102
-
Name
Description
SPIDTR
SPIRPTR
SPILTR
SPIPRLR
SPI01BCR
SPI23BCR
SPI45BCR
SPI67BCR
SPI03SSR
SPI47SSR
SPINTSR
SPITSR
SPIPOSR
SPIDSR
SPIC0DR
SPIC1DR
SPIC2DR
SPIC3DR
SPIC4DR
SPIC5DR
SPIC6DR
SPIC7DR
SPIDSMR
SPIMCR
INTCR
INTSR
SPI Delay Transfer Register
SPI RDY / Pulse Time Register
SPI LDAC Time Register
SPI Pulse/ RDY/ LDAC Register
SPI 0/1 Byte Count Register
SPI 2/3 Byte Count Register
SPI 4/5 Byte Count Register
SPI 6/7 Byte Count Register
SPI 0/1/2/3 slave Select Register
SPI 4/5/6/7 slave Select Register
SPI Interrupt Status Register
SPI Timeout Status Register
SPI Pulse Overrun Status Register
SPI Data Status Register
SPI Channel 0 Data Register
SPI Channel 1 Data Register
SPI Channel 2 Data Register
SPI Channel 3 Data Register
SPI Channel 4 Data Register
SPI Channel 5 Data Register
SPI Channel 6 Data Register
SPI Channel 7 Data Register
SPI Data Status Mirror Register
SPI Master Control Register
Interrupt Configure Register
Interrupt Status Register
Table 2.45-5: ESC Memory and Function Registers Mirror Mapping Table
111
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
3 Electrical Specifications
Parameter conditions
Unless otherwise specified, all voltages are referenced to GND(VSS).
3.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction
temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction
temperature at TJ = 25 °C and TJ = TJmax (given by the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics are indicated in the
table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent
the mean value plus or minus three times the standard deviation (mean±3σ).
3.1.2 Typical values
Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the 1.7 V ≤ VDD ≤ 3.6 V voltage
range). They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion
lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated
(mean±2σ).
3.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
3.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 3.1-1.
3.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 3.1-2.
Figure 3.1-1: Pin loading conditions
112
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Figure 3.1-2: Pin input voltage
113
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
3.1.6 Power supply scheme
1. N corresponds to the number of VDD pins available on the package.
2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
Figure 3.1-3: Power supply scheme
Caution: Each power supply pair (VDD/GND(VSS), VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or below, the
appropriate pins on the underside of the PCB to ensure good operation of the device. It is not
recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect
operation of the device.
114
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
3.1.7 Current consumption measurement
Figure 3.1-4: Current consumption measurement scheme
115
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 3.2-1: Voltage characteristics(1), Table 3.2-2: Current
characteristics, and Table 3.2-3: Thermal characteristics may cause permanent damage to the device. These are
stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
Symbols
VDDX - VSS
Ratings
Min
Max
Unit
−0.3
4.0
V
−0.3
4.0
V
Digital core power supply for ESC sub-system
−0.5
1.6
V
Analog power supply for PLL for ESC sub-system
−0.5
1.6
V
GND−0.3
Min(VDD, VDDA,
VDD33USB, VBAT)
V
External main supply voltage (including VDD, VDDLDO, VDDSMPS,
VDDA, VDD33USB, VBAT)
VCC3IO, VCC33A Power supply of 3.3V I/O for ESC sub-system and Ethernet PHY
VCCK
VCC12A_PLL
Input voltage on FT_xxx pins
+4.0(3)(4)
VIN(2)
|∆VDDX|
|VSSx-VSS|
I IN
I OUT
Input voltage on TT_xx pins
GND -0.3
4.0
V
Input voltage on BOOT0 pin
GND
9.0
V
Input voltage on any other pins
GND -0.3
4.0
V
Input voltage of 3.3V I/O with 5V tolerant(VCC3IO domain).
GND -0.3
5.5
V
Variations between different VDDX power pins of the same domain
-
50
mV
Variations between all the different ground pins
-
50
mV
DC input current (VCC3IO domain).
50
mA
Output short circuit current (VCC3IO domain).
50
mA
1. All main power (VDD, VDDA, VDD33USB, VDDSMPS, VBAT) and ground (GND, VSSA) pins must always be connected to the external power
supply, in the permitted range.
(1)
2. VIN maximum must always be respected. Refer to Table 3.3-46: I/O current injection susceptibility
for the maximum allowed
injected current values.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
Table 3.2-1: Voltage characteristics(1)
116
AX58400
EtherCAT Slave Controller w/ Dual-Core MCU
Symbols
Ratings
Max
ΣIVDD
Total current into sum of all VDD power lines (source)(1)
620
ΣIVSS
Total current out of sum of all VSS ground
lines (sink)(1)
620
IVDD
Maximum current into each VDD power pin (source)(1)
100
IVSS
pin (sink)(1)
100
Maximum current out of each VSS ground
IIO
ΣI(PIN)
IINJ(PIN)(3)(4)
ΣIINJ(PIN)
Output current sunk by any I/O and control pin
20
Total output current sunk by sum of all I/Os and control pins(2)
140
Total output current sourced by sum of all I/Os and control pins(2)
140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5
−5/+0
Injected current on PA4, PA5
−0/0
Total injected current (sum of all I/Os and control pins)(5)
±25
Unit
mA
1. All main power (VDD, VDDA, VDD33USB) and ground (GND, VSS, VSSA) pins must always be connected to the external power supplies,
in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN
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