AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Features
Document No: AX88179A/V1.09/01/17/24
Single chip USB 3.2 Gen 1 to Gigabit
Ethernet Controller with Integrated
10M/100M/1000M Ethernet PHY
Supports TCO filter, L3/L4 IP/Port filter
Supports Second DA RX filter with bit
mask
USB Device Controller
Integrates on-chip USB Type-C 3.2
Gen1 PHY and controller compliant to
USB Spec 3.2 Gen 1, 2.0 and 1.1
Supports all USB 3.2 Gen 1 power
saving modes (U0, U1, U2, and U3)
Supports USB Super/High/Full Speed
modes with Bus-power or Self-power
device
Wake-on-LAN Functions
Supports suspend mode and remote
wakeup via link-change, Magic Packet,
Microsoft wakeup frame and external
wakeup pin
Supports Bonjour Wake-on-Demand
Supports Wakeup Packet Indication
Supports Microsoft Modern Standby
Advanced Power Management Features
Supports power management offload
(ARP & NS)
Supports ECMA-393 ProxZzzy® for
sleeping hosts
Gigabit Ethernet Controller
Integrates 10M/100M/1000M Gigabit
Ethernet MAC/PHY, compliant to IEEE
802.3, 802.3u and 802.3ab
Supports CDC-NCM, CDC-ECM
Supports IEEE 802.3az (Energy
Efficient Ethernet, EEE)
Supports AUTO-MDIX, flow control
(IEEE 802.3 Annex.31B)
Supports IPv4/IPv6 Packet Checksum
Offload Engine (COE)
Supports TCP Large Send Offload
V1/V2
Supports up to 9K Jumbo Frame
Supports IEEE 802.1Q VLAN tagging
and 4096 VLAN ID filtering; received
VLAN tag (4 bytes) can be stripped off
or preserved
Supports IEEE 802.1P Layer 2 Priority
Encoding and Decoding
Supports manageability L2 filter
Supports Windows 11/10/8.x,
Linux/Android /Chrome OS, Nintendo
Switch in-box drivers, and macOS/Linux
native CDC-NCM driver for driverless,
Plug & Play
Supports embedded eFuse for die
identifier and store the USB Device
Descriptors, Node-ID, etc.
Supports SPI Flash for firmware
customization
Single 20 MHz crystal clock source
Integrates on-chip power-on reset circuit
40-pin QFN, 5x5 mm package
Operating Temperature Range: 0 to
+70°C
Target Applications
Notebook/Laptop Onboard LAN
USB Ethernet Dongle for Ultrabook
/Table/Smart Phone/etc.
Docking Station, POS/PDA Cradle
ASIX Electronics Corporation
4F, No.8, Hsin Ann Rd.,
Hsinchu Science Park,
Hsinchu, Taiwan 30078
IP STB, Smart Camera, Smart TV Box
Game Console
5G/LTE Router/Gateway
1
Released Date: 01/17/2024
TEL: +886-3-579-9500
FAX: +886-3-579-9558
https://www.asix.com.tw/
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Typical Applications Diagram
Figure 0-1: AX88179A Typical Applications Diagram
2
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
DISCLAIMER
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may
make changes to the product specifications and descriptions in this document at any time, without notice.
ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without
limitation warranties of merchantability, fitness for a particular purpose, and non-infringement.
Designers must not rely on the absence or characteristics of any features or registers marked “reserved”, “undefined”
or “NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting
a design of ASIX products.
TRADEMARKS
ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the
property of their respective owners.
3
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Table of Contents
1
INTRODUCTION ............................................................................................................................................. 6
GENERAL DESCRIPTION ................................................................................................................................ 6
BLOCK DIAGRAM.......................................................................................................................................... 6
PINOUT DIAGRAM ......................................................................................................................................... 7
SIGNAL DESCRIPTION ................................................................................................................................... 8
1.4.1
USB Interface ....................................................................................................................................... 8
1.4.2
Clock .................................................................................................................................................... 8
1.4.3
GPHY MDI........................................................................................................................................... 8
1.4.4
Misc Pin ............................................................................................................................................... 9
1.4.5
Power and Ground Pin ........................................................................................................................ 9
2
FUNCTION DESCRIPTION.......................................................................................................................... 10
CLOCKS/RESETS ......................................................................................................................................... 10
USB CORE AND INTERFACES ...................................................................................................................... 10
10/100/1000M ETHERNET PHY ................................................................................................................. 10
ENERGY EFFICIENT ETHERNET (EEE) ........................................................................................................ 10
CHECKSUM OFFLOAD ENGINE (COE) ......................................................................................................... 11
USB TO ETHERNET BRIDGE ........................................................................................................................ 11
EFUSE ......................................................................................................................................................... 11
GENERAL PURPOSE I/O AND LED............................................................................................................... 11
3
SPI/EFUSE MEMORY ................................................................................................................................... 12
SPI/EFUSE MEMORY................................................................................................................................... 12
4
USB CONFIGURATION STRUCTURE ...................................................................................................... 12
USB CONFIGURATION ................................................................................................................................ 12
USB INTERFACE ......................................................................................................................................... 12
USB ENDPOINTS ......................................................................................................................................... 12
5
ELECTRICAL SPECIFICATIONS .............................................................................................................. 13
DC CHARACTERISTICS................................................................................................................................ 13
5.1.1
Absolute Maximum Ratings................................................................................................................ 13
5.1.2
Recommended Operating Condition .................................................................................................. 13
5.1.3
DC Characteristics of 3.3V I/O Pins .................................................................................................. 14
POWER CONSUMPTION................................................................................................................................ 15
POWER-ON-RESET (POR) SPECIFICATION .................................................................................................. 17
POWER–UP SEQUENCE ................................................................................................................................ 18
AC TIMING CHARACTERISTICS ................................................................................................................... 19
5.5.1
SPI Timing ......................................................................................................................................... 19
5.5.2
Clock Timing ...................................................................................................................................... 20
5.5.3
Reset Timing....................................................................................................................................... 20
6
PACKAGE INFORMATION ......................................................................................................................... 21
7
ORDERING INFORMATION ....................................................................................................................... 22
8
REVISION HISTORY .................................................................................................................................... 23
4
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
List of Figures
FIGURE 0-1: AX88179A TYPICAL APPLICATIONS DIAGRAM........................................................................................ 2
FIGURE 1-1: AX88179A BLOCK DIAGRAM .................................................................................................................. 6
FIGURE 1-2: AX88179A PINOUT DIAGRAM ................................................................................................................. 7
FIGURE 5-1: POWER ON RESET (POR) TIMING DIAGRAM .......................................................................................... 17
FIGURE 5-2: POWER-UP SEQUENCE TIMING DIAGRAM ............................................................................................... 18
FIGURE 5-3: SPI TIMING ............................................................................................................................................. 19
FIGURE 5-4: CLOCK TIMING DIAGRAM ....................................................................................................................... 20
List of Tables
TABLE 1-1: USB INTERFACE PIN DESCRIPTION ............................................................................................................ 8
TABLE 1-2: CLOCK PIN DESCRIPTION ........................................................................................................................... 8
TABLE 1-3: GPHY MDI PIN DESCRIPTION ................................................................................................................... 8
TABLE 1-4: MISC PIN DESCRIPTION .............................................................................................................................. 9
TABLE 1-5: POWER AND GROUND PIN DESCRIPTION .................................................................................................... 9
TABLE 5-1: AX88179A POWER CONSUMPTION ......................................................................................................... 15
TABLE 5-2: THERMAL CHARACTERISTICS .................................................................................................................. 16
TABLE 5-3: POWER ON RESET (POR) TIMING TABLE................................................................................................. 17
TABLE 5-4: POWER-UP SEQUENCE TIMING TABLE ..................................................................................................... 18
TABLE 5-5: SPI TIMING TABLE................................................................................................................................... 19
TABLE 5-6: CLOCK TIMING TABLE ............................................................................................................................. 20
TABLE 5-7: RESET TIMING TABLE .............................................................................................................................. 20
5
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
1 Introduction
General Description
The AX88179A USB 3.2 Gen1 to 10/100/1000M Gigabit Ethernet controller is a high performance and highly
integrated ASIC which enables low cost, small form factor, and simple plug-and-play Gigabit Ethernet network
connection capability for desktops, notebook PC’s, Ultrabook’s, docking stations, game consoles, digital-home
appliances, and any embedded system using a standard USB port.
The AX88179A features a USB interface to communicate with a USB Host Controller and is compliant with USB
specification V3.2 Gen1, V2.0, and V1.1. It implements a 10/100/1000Mbps Ethernet LAN function based on
IEEE802.3, IEEE802.3u, and IEEE802.3ab standards with embedded SRAMs for packet buffering. And, it also
integrates an on-chip 10/100/1000Mbps EEE-compliant Ethernet PHY to simplify system design.
Block Diagram
Figure 1-1: AX88179A Block Diagram
6
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AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Pinout Diagram
AVDD33_XTAL
RSET
XTAL_OUT
XTAL_IN
DVDD11
RST_N
GPIO4
GPIO3
DVDD33
GPIO2
29
28
27
26
25
24
23
22
21
9
10
DVDD11
40
SSUSB_RXB
39
8
MDIP3
MDIN3
AX88179A
SSUSB_RXA
38
7
AVDD11_GBE
AVDD11_SSUSB
37
6
MDIN2
SSUSB_TXB
36
5
MDIP2
4
35
SSUSB_TXA
MDIN1
AVDD33_SSUSB
MDIP1
34
3
33
USB_DM
AVDD33_GBE
2
32
USB_DP
MDIN0
1
31
AVDD33_USB
MDIP0
30
AX88179A is housed in a 40-pin E-PAD QFN package.
20
LED1
19
LED0
18
AVSS33_BUCK
17
AVDD33_BUCK
16
LX
15
DVDD11
14
DVDD11
13
DVDD33
12
GPIO_8/PME
11
VBUS
Figure 1-2: AX88179A Pinout Diagram
7
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AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Signal Description
Following abbreviations are used in “Type” column of below pin description tables. Note that some I/O pins with
multiple signal definitions on the same pin may have different attributes in “Type” column for different signal
definition.
AB
AI
AO
B3
I3
O3
Analog Bi-directional I/O
Analog Input
Analog Output
Bi-directional I/O, 3.3V
Input, 3.3V
Output, 3.3V
PU
PD
P
S
T
4m
8m
Internal Pull-Up (75K)
Internal Pull-Down (75K)
Power/Ground pin
Schmitt Trigger
Tri-state
4mA driving strength
8mA driving strength
1.4.1 USB Interface
Pin Name
USB_DP
USB_DM
SSUSB_TXA
SSUSB_TXB
SSUSB_RXA
SSUSB_RXB
Type
AB
AB
AO
AO
AI
AI
Pin No
Pin Description
2
USB 2.0 data differential pair positive pin.
3
USB 2.0 data differential pair negative pin.
5
USB 3.2 Gen 1 TX- differential pair pin A.
6
USB 3.2 Gen 1 TX+ differential pair pin B.
8
USB 3.2 Gen 1 RX- differential pair pin A.
9
USB 3.2 Gen 1 RX+ differential pair pin B.
Table 1-1: USB Interface Pin Description
1.4.2 Clock
Pin Name
XTAL_IN
XTAL_OUT
Type
I3
O3
Pin No
27
28
Pin Description
20Mhz crystal or oscillator clock input.
20Mhz crystal or oscillator clock output.
Table 1-2: Clock Pin Description
1.4.3 GPHY MDI
Pin Name
MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3
Type
AB
AB
AB
AB
AB
AB
AB
AB
Pin No
31
32
34
35
36
37
39
40
Pin Description
MDI pair 0 positive pin
MDI pair 0 negative pin
MDI pair 1 positive pin
MDI pair 1 negative pin
MDI pair 2 positive pin
MDI pair 2 negative pin
MDI pair 3 positive pin
MDI pair 3 negative pin
Table 1-3: GPHY MDI Pin Description
8
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AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
1.4.4 Misc Pin
Pin Name
Type
Pin No
Pin Description
RSET
AB
29
External Reference Resistor (24 KΩ, 1%) Connect resistor to Analog GND.
VBUS
I3/S
11
VBUS signal of USB.
RST_N
I3/S/PU
25
Reset signal. Active low
GPIO_2
B3/S
21
Clock pin of SPI.
GPIO_3
B3/S
23
SPI data I/O pin if GPIO_4 pulled up.
GPIO_4
B3/S
24
If pulled up, CS pin of SPI
GPIO_8/PME* B3/S/PU
12
PME pin for power management, always pull up this pin.
LED_0
B3
19
Programmable LED_0 indication
LED_1
B3
20
Programmable LED_1 indication
*: It is a multi-function pin. The default is an external wakeup pin. Active low. PME pin needs to set by tool.
Table 1-4: Misc Pin Description
1.4.5 Power and Ground Pin
Pin Name
Type Pin No
AVDD33_USB
P
1
AVDD33_SSUSB
P
4
AVDD11_SSUSB
P
7
DVDD11
P
10
DVDD33
P
13
DVDD11
P
14
DVDD11
P
15
LX
P
16
AVDD33_BUCK
P
17
AVSS33_BUCK
P
18
DVDD33
P
22
DVDD11
P
26
AVDD33_XTAL
P
30
AVDD33_GBE
P
33
AVDD11_GBE
P
38
Pin Description
3.3V Analog Power Input of USB.
3.3V Analog Power Input of SS USB.
1.1V Analog Power Input of SS USB.
1.1V Digital Power.
3.3V I/O Power.
1.1V Digital Power.
1.1V Digital Power.
This 1.1V power pin drives external inductors for on-die BUCK.
3.3V Analog Power for on-die BUCK.
3.3V Analog Ground for on-die BUCK.
3.3V I/O Power.
1.1V Digital Power.
3.3V Analog Power for crystal pad.
3.3V Analog Power for Ethernet PHY.
1.1V Analog Power for Ethernet PHY.
Table 1-5: Power and Ground Pin Description
9
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
2 Function Description
Clocks/Resets
The AX88179A integrates internal oscillator circuits for 20 MHz (20MHz ± 50PPM at room temperature),
respectively, which allow the chip to operate cost effectively with just one single external 20 MHz crystal.
The external 20 MHz crystal or oscillator, via pins XTAL_IN / XTAL_OUT, provides the reference clock to
internal oscillation circuit to generate clock source for the embedded Ethernet PHY, embedded USB PHY, and
base clock for ASIC use.
The AX88179A integrates an internal power-on-reset circuit, which can simplify the external reset circuitry on
PCB design. The power-on-reset circuit generates a reset pulse to reset chip logic after 1.1V core power ramping
up to 0.72V (typical threshold). The external hardware reset input pin, RST_N, is fed directly to the input of the
power-on-reset circuit and can also be used as additional hardware reset source to reset the system logic. For more
details on RST_N timing, please refer to the Reset timing section.
USB Core and Interfaces
The USB core and interfaces contains USB 3.2 Gen1/USB 2.0 transceiver interfaces (PIPE/UTMI) and USB 3.2
Gen1/USB 2.0 Device Controller.
The USB 3.2 Gen1/USB 2.0 transceiver (or PHY) processes USB 3.2 Gen1/2.0/1.1 Physical layer signals. And,
The USB 3.2 Gen1/USB 2.0 Device Controller is interfacing with USB 3.2 Gen1/USB 2.0 transceiver by
PIPE/UTMI buses and it processes packets of Link layer and protocol layer. Also, The USB 3.2 Gen1/USB 2.0
Device Controller contains Bulk IN and Bulk OUT buffers for handling Bulk transfer traffic and a FIFO for
Interrupt IN transfers.
The USB core and interfaces are used to communicate with a USB host controller and is compliant with USB
specification V3.2 Gen1, V2.0, and V1.1
10/100/1000M Ethernet PHY
The 10/100/1000M Ethernet PHY is compliant with 10Base-T, 100Base-TX, and 1000Base-T IEEE 802.3
standards. It provides all the necessary physical layer functions to transmit and receive Ethernet packets over CAT
5e UTP cable or CAT 3 UTP (10Mbps only) cable. It uses DSP technology and an Analog Front End (AFE) to
enable high-speed data transmission and reception over UTP cable. Functions such as Crossover Detection &
Auto-Correction (Auto-MDIX), polarity correction, adaptive equalization, cross-talk cancellation, echo
cancellation, timing recovery, and error correction are implemented.
Energy Efficient Ethernet (EEE)
It supports IEEE 802.3az also known as Energy Efficient Ethernet (EEE). And also supports EEE specified a
negotiation method to enable link partner to determine whether EEE is supported and to select the best set of
parameters common to both devices. It provides a protocol to coordinate transitions to/from a lower power
consumption level (Low Power Idle mode) based on link utilization. When no packets are being transmitted, the
system goes to Low Power Idle mode to save power. Once packets need to be transmitted, the system returns to
normal mode, and does this without changing the link status and without dropping/corrupting frames.
To save power, when the system is in Low Power Idle mode, most of the circuits are disabled; however, the
transition time to/from Low Power Idle mode is kept small enough to be transparent to upper layer protocols and
applications.
10
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AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Checksum Offload Engine (COE)
The Checksum Offload Engine (COE) supports IPv4, IPv6, layer 4 (TCP, UDP, ICMP, ICMPv6 and IGMP)
header processing functions and real time checksum calculation in hardware
The COE supports the following features in layer 3:
IP header parsing, including IPv4 and IPv6
IPv6 extension header and routing header type 0 supported
IPv4 header checksum check and generation (There is no checksum field in IPv6 header)
Detecting on RX direction for IP packets with error header checksum
The COE supports the following features in layer 4:
TCP and UDP checksum check and generation for non-fragmented packet
TCP Large Send Offload V2
ICMP, ICMPv6 and IGMP message checksum check and generation for non-fragmented packet.
USB to Ethernet Bridge
The USB to Ethernet bridge block is responsible for converting Ethernet MAC frame into USB packets or
vice-versa. This block supports proprietary burst transfer mechanism (US Patent Approval) to offload software
burden and to offer very high packet transfer throughput over USB bus.
This USB to Ethernet bridge block not only co-work with “eFuse and Control”, “SPI Loader I/F”, and General
Purpose I/Os and LEDs, but also handle USB Control transfers of Endpoint 0.
eFuse
The AX88179A integrated an eFuse which is allowed user to program USB descriptions (PID, VID, Serial
numbers… ect) and some device information (MAC address). And ASIX advance data structures allow user to
program this information for multiple times.
General Purpose I/O and LED
There are 3 general-purpose I/O pins for SPI flash and 2 LED pins for LED indication.
11
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AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
3 SPI/eFuse Memory
SPI/eFuse Memory
AX88179A supports integrated eFuse for MAC address, USB descriptor and several user specified information.
It also supports external SPI flash for firmware image. These non-violated memory supports advance data
architecture for multiple times programming.
4 USB Configuration Structure
USB Configuration
The AX88179A supports 2 USB Configuration, 1 for AX88179A proprietary driver, 1 for CDC-ECM/NCM.
USB Interface
The AX88179A supports 1 interface.
USB Endpoints
The AX88179A supports following 4 endpoints:
Endpoint 0: Control endpoint. It is used for configuring the device. Please refer to the USB Standard
Commands and USB Vendor Commands sections.
Endpoint 1: Interrupt endpoint. It is used for reporting network Link status. Please refer to the Interrupt
Endpoint section.
Endpoint 2: Bulk IN endpoint. It is used for receiving Ethernet Packet.
Endpoint 3: Bulk OUT endpoint. It is used for transmitting Ethernet Packet.
12
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
5 Electrical Specifications
DC Characteristics
5.1.1 Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
DVDD33
3.3V Supply Voltage
AVDD33_USB
AVDD33_SSUSB
-0.3
3.63
V
AVDD33_BUCK
AVDD33_XTAL
AVDD33_GBE
DVDD11
1.1V Supply Voltage
AVDD11_SSUSB
-0.1
1.2
V
AVDD11_GBE
Note:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should
be restricted to the optional sections of this datasheet. Exposure to absolute maximum rating condition for
extended periods may affect device reliability.
2. The input and output negative voltage ratings may be exceeded if the input and output currents under ratings
are observed.
5.1.2 Recommended Operating Condition
Symbol
AVDD33_USB
AVDD33_SSUSB
AVDD11_SSUSB
DVDD11
DVDD33
AVDD33_BUCK
AVDD33_XTAL
AVDD33_GBE
AVDD11_GBE
Tj
Ta
TSTG
Parameter
3.3V Analog Power Input of USB.
3.3V Analog Power Input of SS USB.
1.1V Analog Power Input of SS USB.
1.1V Digital Power.
3.3V I/O Power.
3.3V Analog Power Input of BUCK.
3.3V Analog Power Input of Crystal.
3.3V Analog Power Input of Ethernet PHY.
1.1V Analog Power Input of Ethernet PHY.
Operating junction temperature
Operating ambient temperature
Storage temperature
Min
3.14
3.14
1.045
1.045
3.14
3.14
3.14
3.14
1.045
0
0
-65
Typ
3.3
3.3
1.1
1.1
3.3
3.3
3.3
3.3
1.1
25
-
13
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Max
3.46
3.46
1.155
1.155
3.46
3.46
3.46
3.46
1.155
125
70
150
Units
V
V
V
V
V
V
V
V
V
℃
℃
℃
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
5.1.3 DC Characteristics of 3.3V I/O Pins
Symbol
Parameter
DVDD33 Power supply of 3.3V I/O.
Vil
Input low voltage.
Vih
Input high voltage.
Schmitt trigger negative going threshold
Vtvoltage.
Schmitt trigger positive going threshold
Vt+
voltage
Vol
Output low voltage.
Voh
Output high voltage.
Vopu (1) Output pull-up voltage for 5V tolerant IO
Conditions
3.3V I/O
LVTTL
Min
3.14
2.0
Typ
3.3
-
Max
3.46
0.8
-
Units
V
V
V
0.8
1.1
-
V
-
1.6
2.0
V
-
0.4
V
-
-
V
-
-
V
LVTTL
Iol = 4 ~ 8mA
DVDD33
Ioh = 4 ~ 8mA
-0.4
With internal
DVDD33
pull-up resistor
– 0.9
40
40
Vin = 3.3 or 0V
Vin = 0 V
-
Input pull-up resistance.
75
190
KΩ
Input pull-down resistance.
75
190
KΩ
Input leakage current.
±6
μA
Input leakage current with pull-up resistance.
-45
μA
Iin
Input leakage current with pull-down
Vin = DVDD33
45
μA
resistance.
Note: This parameter indicates that the pull-up resistor for the I/O pins cannot reach DVDD33 DC level even
without DC loading current.
Rpu
Rpd
14
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AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Power Consumption
Symbol
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
IVDD33
IVDD11
Description
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
IVDD33
Current Consumption of 3.3V
IVDD11
IVDD33
IVDD11
IVDD33
.
IVDD11
IVDD33
IVDD11
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
IVDD33
Current Consumption of 3.3V
IVDD11
IVDD33
IVDD11
IVDD33
System
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Current Consumption of 3.3V
ISYSTEM
ISYSTEM
ISYSTEM (Suspend)
Current Consumption of 1.1V
Current Consumption of 3.3V
Current Consumption of 1.1V
Power consumption of AX88179A full loading
(chip only)
Power consumption of AX88179A full loading
(test board)
Power consumption of AX88179A (test board):
Suspend and disable Remote WakeUp.
Conditions
Typ
Operating at Ethernet 1Gbps full duplex mode
and USB Super Speed mode
Operating at Ethernet 100Mbps full duplex
mode and USB Super Speed mode
Operating at Ethernet 100Mbps half duplex
mode and USB Super Speed mode
Operating at Ethernet 10Mbps half duplex
mode and USB Super Speed mode
Operating at Ethernet 1Gbps full duplex mode
and USB High Speed mode
Operating at Ethernet 100Mbps full duplex
mode and USB High Speed mode
Operating at Ethernet 100Mbps half duplex
mode and USB Super Speed mode
Operating at Ethernet 10Mbps half duplex
mode and USB High Speed mode
Operating at Ethernet 1Gbps full duplex mode
and USB Full Speed mode
Operating at Ethernet 100Mbps full duplex
mode and USB Full Speed mode
Operating at Ethernet 100Mbps half duplex
mode and USB Full Speed mode
Operating at Ethernet 10Mbps half duplex
mode and USB Full Speed mode
Ethernet unlink (Disable AutoDetach) and
USB Super Speed mode
104.3
90.5
73.4
42.6
73.3
42.6
63.5
32.7
64
90.1
34
33.2
33.8
29.7
22.6
38.5
59.4
75
30.7
31
30.6
26
21.4
23
62.8
31.2
14.7
7.3
57.7
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
70.6
mA
19.4
11.9
0.8
0
mA
mA
mA
mA
Operating at Ethernet 1Gbps mode and USB
Super Speed mode (Ethernet linked in EEE)
Operating at Ethernet 1Gbps mode and USB
Super Speed mode (Ethernet linked in
non-EEE)
USB Suspend and enable Remote WakeUp
(Ethernet linked in EEE 1Gbps mode)
USB Suspend and enable Remote WakeUp
(Ethernet linked in non-EEE 1Gbps mode)
58.8
70.3
103
mA
mA
mA
89.5
mA
19.2
11.9
58.7
69.9
mA
mA
mA
mA
3.3V include 1.1V
137
mA
133.9
mA
0.7
mA
Ethernet unlink (Enable AutoDetach)
USB Suspend and Ethernet is 1Gbps: enable
Remote WakeUp and disable WOLLP (WOL
Low Power)
USB Suspend and enable Remote WakeUp
and enable WOLLP to 10Mbps
Suspend and disable Remote WakeUp
VBUS of 5.0V (Using Switching regulator
with two ports:1.1/3.3V)
VBUS of 5.0V (Using Switching regulator
with two ports:1.1/3.3V)
Note: Above current value are typical values measured on AX88179A Test board.
Table 5-1: AX88179A Power Consumption
15
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Symbol
ΘJC
ΘJA
ΘJB
JT
Description
Thermal resistance of junction to case
Thermal resistance of junction to ambient
Thermal resistance of junction to board (PCB 4L)
Junction to Top of the Package Characterization
Parameter
Condition
Still Air
Min
-
Typ
18.5
32.9
9
Max
-
Unit
°C/W
°C/W
°C/W
-
0.67
-
°C/W
Table 5-2: Thermal Characteristics
16
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Power-On-Reset (POR) Specification
Below figures and table show the two POR circuit spec during power ramp-up/down.
Vrr
Vfr
DVDD11
POR Output
Tdrop
Trst
Figure 5-1: Power On Reset (POR) Timing Diagram
Symbol
DVDD11
V
V
Description
Power supply voltage to be detected
Conditions
-
Min.
1.045
Typ.
1.1
Max.
1.155
Units
V
rr
DVDD11 rise relax voltage
-
-
0.85
0.9
V
fr
DVDD11 fall release voltage
-
-
0.63
0.80
V
Trst
Reset time after POR trigger up
DVDD11 slew
rate = 1.0V / 1μs
1.8
2.5
4.8
μs
Tdrop
Drop time of DVDD11 to reset
DVDD11 slew
rate = 2.5V / 1μs
0.2
0.4
0.9
μs
Table 5-3: Power On Reset (POR) Timing Table
17
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Power–up Sequence
Trise3
T23
3.3V
DVDD33
0V
Trise2
1.1V
DVDD11
0V
Trst
RST_N
Tclk
…
XTAL_IN
Figure 5-2: Power-up Sequence Timing Diagram
Symbol
Parameter
Conditions
Min
Trise3
3.3V power supply rise time.
From 0V to 3.3V.
Trise2
1.1V power supply rise time.
From 0V to 1.1V.
Interval between DVDD33 rising to
T23
2.64V(80%) to DVDD11 rising to
2
0.88V(80%)
From DVDD11 rising to 1.1V to
Trst
RST_N asserted low level interval.
RST_N going high.
From DVDD33 rising to 3.3V to
20MHz crystal oscillator start-up
Tclk
clock stable of 20MHz crystal time.
oscillator.
Note: The above typical timing data is measured from AX88179A test board.
Typ
400
200
Max Units
us
us
-
4
ms
40
-
us
-
20
ms
Table 5-4: Power-up Sequence Timing Table
18
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
AC Timing Characteristics
5.5.1 SPI Timing
Figure 5-3: SPI Timing
Symbol
1
2
3
4
5
6
7
8, 9
Parameter
SCLK clock frequency
Setup time of SS to the first SCLK edge
Hold time of SS after the last SCLK edge
Minimum idle time between transfers (minimum
SS high time)
Min Typ
Fsys_clk
(SPIBRR + 1) * 2
0.5 * Tsclk
0.5 * Tsclk
((32 * SPIDT + 6) *
Tsys_clk) + (0.5 *
Tsclk)
5.98
0
-
MOSI data valid time, after SCLK edge
MISO data setup time before SCLK edge
MISO data hold time after SCLK edge
Bus drive time before SS assertion and after SS
de-assertion
Note 1: Fclk = 1/Tclk, where Tclk = ((SCL_HP + SCL_LP) * Tsys_clk).
Tsys_clk is 20MHz or 80MHz.
Table 5-5: SPI Timing Table
19
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
Max Units
MHz
-
ns
ns
ns
1.53
0.5 *
Tsclk
ns
ns
ns
ns
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
5.5.2 Clock Timing
TP_XTL20P
TH_XTL20P
TL_XTL20P
VIH
VIL
Figure 5-4: Clock Timing Diagram
Symbol
TP_XTL20P
TH_XTL20P
TL_XTL20P
Parameter
XTL20P clock cycle time
XTL20P clock high time
XTL20P clock low time
Condition
Min
-
Typ
50.0
25.0
25.0
Max
-
Unit
ns
ns
ns
Table 5-6: Clock Timing Table
5.5.3 Reset Timing
XTAL_IN
RST_N
Trst
Symbol
Description
Trst Reset pulse width after XTAL_IN is running
Min
200
Typ
-
Max
-
Unit
XTAL_IN clock cycle
Table 5-7: Reset Timing Table
20
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
6 Package Information
21
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
Recommended PCB Footprint for 40-pin QFN 5x5 package
Symbol
e
b
L
U
V
W
Description
Lead pitch
Pad width
Pad length
-
Typical Dimension
0.40 mm
0.20 mm
0.60 mm
2.80 mm
3.80 mm
4.20 mm
22
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
7 Ordering Information
Part Number
AX88179AQF
Description
40-pin QFN lead Free package, Commercial temperature range: 0 to 70°C.
8 Revision History
Revision
V0.10
V0.20
V0.30
V0.40
V0.50
V1.00
V1.01
V1.02
V1.03
V1.04
V1.05
V1.06
V1.07
V1.08
V1.09
Date
Comments
2020/10/13 Preliminary release.
2020/10/21 1.Modified some descriptions in Section 1.4, 3.1, 4.3.
2.Updated the package information in Section 6.
3.Updated the part number information in Section 7.
2021/01/08 Updated Wake-on-LAN Functions in Features page
2021/01/26 Corrected USB Device Controller Functions in Features page
2021/06/16 1.Modified some descriptions in Section 1.4.4
2.Updated Table 5-2.
2021/06/25 Updated some description in Section 1.4.4
2021/12/06 Updated some description in Section 5.1.1
2021/12/21 Updated some description in Features page.
2022/06/16 Updated some description in Table 5-1.
2022/06/30 Modified some description in Section 3.1
2022/11/24 1.Added Section 5.1.1
2.Updated some description in Section 1.4.1
2022/12/27 1.Added Recommended PCB Footprint for 40-pin QFN 5x5 package in Section 6
2.Updated Figure 1-1.
2023/02/20 Updated Table 5-4.
2023/12/04 Corrected signal definition in Section 1.4
2024/01/17 Updated some description in Features page.
23
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.
AX88179A
USB 3.2 Gen1 to Gigabit Ethernet Controller
4F, No.8, Hsin Ann RD., Hsinchu Science Park,
Hsinchu, Taiwan, R.O.C.
TEL: +886-3-5799500
FAX: +886-3-5799558
Email: support@asix.com.tw
Web: https://www.asix.com.tw
24
Copyright © 2020-2024 ASIX Electronics Corporation. All rights reserved.