AX88196L

AX88196 L 10/100BASE Fast Ethernet MAC Controller 10/100BASE Local CPU Bus Fast Ethernet MAC Controller with Embedded SRAM, SNI interface and Parallel Port Document No.: AX196-12 / V1.2 / May. 12 ’00 Features • • • • • • • • • IEEE 802.3u 100BASE-T, TX, and T4 Compatible Single chip local CPU bus 10/100Mbps Fast Ethernet MAC Controller Embedded 8K * 16 bit SRAM NE2000 register level compatible instruction Support both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80186 series and MC68K series CPU Support both 10Mbps and 100Mbps data rate Support both full-duplex or half-duplex operation Provides a MII port for both 10/100Mbps operation Provides SNI I/F for Home LAN PHY or 10M transceiver option Support EEPROM interface to store MAC address External and internal loop-back capability Support Standard Print Port, can also used as general I/O port • 128-pin LQFP low profile package • 20MHz to 25MHz Operation, Dual 5V and 3.3V CMOS process with 5V I/O tolerance. Or pure 3.3V operation *IEEE is a registered trademark of the Institute of Electrical and Electronic Engineers, Inc. *All other trademarks and registered trademark are the property of their respective holders. • • • Product description The AX88196 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller with embedded 8K*16 bit SRAM. The AX88196 supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88196 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and supports both 10Mbps/100Mbps media-independent interface (MII) and legacy pure 10Mbps SNI interface to simplify the design. Using Serial Network Interface (SNI) transceiver, Home LAN PHY or 10BASE-2 BNC type media can be supported. As well as, the chip also provides Standard Print Port (parallel port interface), can be used for printer server device or treat as simple general I/O port. System Block Diagram AD BUS Print Port Or General I/O Ports Addr L Home LAN PHY Or 10M PHY/TxRx LATCH RJ11 or BNC This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. ASIX ELECTRONICS CORPORATION 2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558 8051 CPU AX88196 Addr H 10/100M PHY/TxRx Ctl BUS RJ45 Always contact ASIX for possible updates before starting a design. First Released Date : Dec/13/1999 http://www.asix.com.tw AX88196 Local CPU BUS MAC Controller CONTENTS 1.0 INTRODUCTION ...............................................................................................................................................4 1.1 GENERAL DESCRIPTION: .....................................................................................................................................4 1.2 AX88196 BLOCK DIAGRAM:...............................................................................................................................4 1.3 AX88196 PIN CONNECTION DIAGRAM ................................................................................................................5 1.3.1 AX88196 Pin Connection Diagram for ISA Bus Mode.................................................................................6 1.3.2 AX88196 Pin Connection Diagram for 80x86 Mode....................................................................................7 1.3.3 AX88196 Pin Connection Diagram for MC68K Mode.................................................................................8 1.3.4 AX88196 Pin Connection Diagram for MCS-51 Mode ................................................................................9 2.0 SIGNAL DESCRIPTION..................................................................................................................................10 2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP....................................................................................................10 2.2 MII INTERFACE SIGNALS GROUP ........................................................................................................................11 2.3 EEPROM SIGNALS GROUP ...............................................................................................................................12 2.4 SNI INTERFACE PINS GROUP ..............................................................................................................................12 2.5 STANDARD PRINTER PORT INTERFACE PINS GROUP .............................................................................................12 2.6 POWER ON CONFIGURATION SETUP SIGNALS PINS GROUP .....................................................................................13 2.7 MISCELLANEOUS PINS GROUP ............................................................................................................................13 3.0 MEMORY AND I/O MAPPING ......................................................................................................................15 3.1 EEPROM MEMORY MAPPING ..........................................................................................................................15 3.2 I/O MAPPING....................................................................................................................................................15 3.3 SRAM MEMORY MAPPING ...............................................................................................................................15 4.0 REGISTERS OPERATION..............................................................................................................................16 4.1 COMMAND REGISTER (CR) OFFSET 00H (READ/WRITE) ...................................................................................18 4.2 INTERRUPT STATUS REGISTER (ISR) OFFSET 07H (READ/WRITE)......................................................................18 4.3 INTERRUPT MASK REGISTER (IMR) OFFSET 0FH (WRITE)..................................................................................19 4.4 DATA CONFIGURATION REGISTER (DCR) OFFSET 0EH (WRITE)........................................................................19 4.5 TRANSMIT CONFIGURATION REGISTER (TCR) OFFSET 0DH (WRITE).................................................................19 4.6 TRANSMIT STATUS REGISTER (TSR) OFFSET 04H (READ) .................................................................................20 4.7 RECEIVE CONFIGURATION (RCR) OFFSET 0CH (WRITE) ...................................................................................20 4.8 RECEIVE STATUS REGISTER (RSR) OFFSET 0CH (READ) ...................................................................................20 4.9 INTER-FRAME GAP (IFG) OFFSET 16H (READ/WRITE) .......................................................................................21 4.10 INTER-FRAME GAP SEGMENT 1(IFGS1) OFFSET 12H (READ/WRITE)................................................................21 4.11 INTER-FRAME GAP SEGMENT 2(IFGS2) OFFSET 13H (READ/WRITE)................................................................21 4.12 MII/EEPROM MANAGEMENT REGISTER (MEMR) OFFSET 14H (READ/WRITE)...............................................21 4.13 TEST REGISTER (TR) OFFSET 15H (WRITE) ....................................................................................................21 4.14 SPP DATA PORT REGISTER (SPP_DPR) OFFSET 18H (READ/WRITE)...............................................................22 4.15 SPP STATUS PORT REGISTER (SPP_SPR) OFFSET 19H (READ)........................................................................22 4.16 SPP COMMAND PORT REGISTER (SPP_CPR) OFFSET 1AH (READ/WRITE) ......................................................22 5.0 CPU I/O READ AND WRITE FUNCTIONS ..................................................................................................23 5.1 ISA BUS TYPE ACCESS FUNCTIONS. ....................................................................................................................23 5.2 80186 CPU BUS TYPE ACCESS FUNCTIONS. ........................................................................................................23 5.3 MC68K CPU BUS TYPE ACCESS FUNCTIONS.......................................................................................................24 5.4 MCS-51 CPU BUS TYPE ACCESS FUNCTIONS. .....................................................................................................24 6.0 ELECTRICAL SPECIFICATION AND TIMINGS .......................................................................................25 6.1 ABSOLUTE MAXIMUM RATINGS .........................................................................................................................25 6.2 GENERAL OPERATION CONDITIONS ...................................................................................................................25 6.3 DC CHARACTERISTICS......................................................................................................................................25 6.4 A.C. TIMING CHARACTERISTICS........................................................................................................................26 6.4.1 XTAL / CLOCK.........................................................................................................................................26 2 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 6.4.2 Reset Timing.............................................................................................................................................26 6.4.3 ISA Bus Access Timing..............................................................................................................................27 6.4.4 80186 Type I/O Access Timing..................................................................................................................28 6.4.5 68K Type I/O Access Timing.....................................................................................................................29 6.4.6 8051 Bus Access Timing ...........................................................................................................................30 6.4.7 MII Timing................................................................................................................................................31 6.4.8 SNI Timing................................................................................................................................................32 7.0 PACKAGE INFORMATION ...........................................................................................................................33 APPENDIX A: APPLICATION NOTE.................................................................................................................34 A.1 USING CRYSTAL 25MHZ OR 20MHZ .................................................................................................................34 A.2 USING OSCILLATOR 25MHZ OR 20MHZ ............................................................................................................34 A.3 USING 60MHZ OSCILLATOR/CRYSTAL ..............................................................................................................34 A.4 DUAL POWER (5V AND 3.3V/3.0V) APPLICATION ..............................................................................................35 A.5 SINGLE POWER (3.3V/3.0V) APPLICATION.........................................................................................................35 A.6 DUAL POWER (5V AND 3.3V) APPLICATION WITH 3.3V PHY .............................................................................36 ERRATA OF AX88196 VERSION ED2.................................................................................................................37 DEMONSTRATION CIRCUIT : AX88196 + ETHERNET PHY + HOMEPNA 1M8 PHY ..............................38 FIGURES FIG - 1 AX88196 BLOCK DIAGRAM ..............................................................................................................................4 FIG - 2 AX88196 PIN CONNECTION DIAGRAM...............................................................................................................5 FIG - 3 AX88196 PIN CONNECTION DIAGRAM FOR ISA BUS MODE ................................................................................6 FIG - 4 AX88196 PIN CONNECTION DIAGRAM FOR 80X86 MODE ...................................................................................7 FIG - 5 AX88196 PIN CONNECTION DIAGRAM FOR MC68K MODE ................................................................................8 FIG - 6 AX88196 PIN CONNECTION DIAGRAM FOR MCS-51 MODE................................................................................9 TABLES TAB - 1 LOCAL CPU BUS INTERFACE SIGNALS GROUP...................................................................................................11 TAB - 2 MII INTERFACE SIGNALS GROUP......................................................................................................................11 TAB - 3 EEPROM BUS INTERFACE SIGNALS GROUP......................................................................................................12 TAB - 4 SERIAL NETWORK INTERFACE PINS GROUP ......................................................................................................12 TAB - 5 STANDARD PRINTER PORT INTERFACE PINS GROUP ..........................................................................................13 TAB - 6 POWER ON CONFIGURATION SETUP PINS GROUP ................................................................................................13 TAB - 7 MISCELLANEOUS PINS GROUP..........................................................................................................................14 TAB - 8 I/O ADDRESS MAPPING ..................................................................................................................................15 TAB - 9 LOCAL MEMORY MAPPING .............................................................................................................................15 TAB - 10 PAGE 0 OF MAC CORE REGISTERS MAPPING.................................................................................................16 TAB - 11 PAGE 1 OF MAC CORE REGISTERS MAPPING.................................................................................................17 3 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 1.0 Introduction 1.1 General Description: The AX88196 provides industrial standard NE2000 registers level compatable instruction set. Various drivers are easy acquired, maintenance and usage. No much additional effort to be paid. Software is easily port to various embedded system with no pain and tears The AX88196 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller with embedded 8K*16 bit SRAM. The AX88196 supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88196 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and supports both 10Mbps/100Mbps media-independent interface (MII) and legacy pure 10Mbps SNI interface to simplify the design. Using Serial Network Interface (SNI) transceiver, Home LAN PHY or 10BASE-2 BNC type media can be supported. As well as, the chip also provides Standard Print Port ( parallel port interface ), can be used for printer server device or treat as simple general I/O port. The main difference between AX88196 and AX88195 are : 1) Replace memory I/F with SNI and SPP I/F. 2) Canceling SAX address decoding. 3) Fix interrupt status can’t always clean up problem of AX88195. AX88196 use 128-pin LQFP low profile package, 25MHz operation, dual 5V and 3.3V CMOS process with 5V I/O tolerance or pure 3.3V operation. 1.2 AX88196 Block Diagram: SMDC SMDIO EECS EECK EEDI EEDO SPP / GIO 8K* 16 SRAM and Memory Arbiter SEEPROM I/F NE2000 Registers STA SNI I/F Remote DMA FIFOs MAC Core MII I/F Print Port or General I/O Host Interface Ctl BUS Fig - 1 AX88196 Block Diagram SA[9:0] SD[15:0] 4 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 1.3 AX88196 Pin Connection Diagram The AX88196 is housed in the 128-pin plastic light quad flat pack. Fig - 2 AX88196 Pin Connection Diagram shows the AX88196 pin connection diagram. TXD[1] TXD[2] TXD[3] LVDD CLKO VSS LCLK/XTALIN XTALOUT VSS EECS EECK EEDI EEDO LVDD SAL[0] SAL[1] SAL[2] SAH[0] SAH[1] SAH[2] NC NC VSS /IOCS16 NC NC /CS AEN/PSEN RDY/DTACK /RESET RESET LVDD 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 TXD[0] TX_EN TX_CLK VSS MDC MDIO RXD[3] RXD[2] RXD[1] RXD[0] RX_CLK CRS COL RX_DV RX_ER VSS SCRS SRXD SRXC TEST SCOL HVDD /SLINK NC CPU[0] CPU[1] STXE VSS STXD /CLK_DIV3 STXC IO_BASE[0] AX88196 LOCAL CPU BUS 10/100BASE MAC CONTROLLER 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 HVDD IO_BASE[1] IO_BASE[2] PD0 PD1 VSS PD2 PD3 PD4 PD5 LVDD PD6 PD7 /ERR SLCT VSS PE /ACK BUSY /STRB LVDD /ATFD /INIT /SLIN VSS NC SD[0] SD[1] SD[2] SD[3] VSS SD[4] /UDS SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] SA[9] VSS /IRQ IRQ NC R/W /IOWR /IORD NC NC /LDS /BHE HVDD SD[15] SD[14] SD[13] SD[12] VSS SD[11] SD[10] SD[9] SD[8] HVDD SD[7] SD[6] SD[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Fig - 2 AX88196 Pin Connection Diagram 5 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 1.3.1 AX88196 Pin Connection Diagram for ISA Bus Mode TXD[0] TX_EN TX_CLK VSS MDC MDIO RXD[3] RXD[2] RXD[1] RXD[0] RX_CLK CRS COL RX_DV RX_ER VSS SCRS SRXD SRXC TEST SCOL HVDD /SLINK NC CPU[0] CPU[1] STXE VSS STXD /CLK_DIV3 STXC IO_BASE[0] TXD[1] TXD[2] TXD[3] LVDD CLKO VSS LCLK/XTALIN XTALOUT VSS EECS EECK EEDI EEDO LVDD SAL[0] SAL[1] SAL[2] SAH[0] SAH[1] SAH[2] NC NC VSS /IOCS16 NC NC /CS AEN RDY /RESET RESET LVDD 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AX88196 LOCAL CPU BUS 10/100BASE MAC CONTROLLER (for ISA Bus I/F) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 HVDD IO_BASE[1] IO_BASE[2] PD0 PD1 VSS PD2 PD3 PD4 PD5 LVDD PD6 PD7 /ERR SLCT VSS PE /ACK BUSY /STRB LVDD /ATFD /INIT /SLIN VSS NC SD[0] SD[1] SD[2] SD[3] VSS SD[4] Fig - 3 AX88196 Pin Connection Diagram for ISA Bus Mode SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] SA[9] VSS IRQ NC /IOWR /IORD NC NC /BHE HVDD SD[15] SD[14] SD[13] SD[12] VSS SD[11] SD[10] SD[9] SD[8] HVDD SD[7] SD[6] SD[5] 6 ASIX ELECTRONICS CORPORATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AX88196 Local CPU BUS MAC Controller 1.3.2 AX88196 Pin Connection Diagram for 80x86 Mode TXD[0] TX_EN TX_CLK VSS MDC MDIO RXD[3] RXD[2] RXD[1] RXD[0] RX_CLK CRS COL RX_DV RX_ER VSS SCRS SRXD SRXC TEST SCOL HVDD /SLINK NC CPU[0] CPU[1] STXE VSS STXD /CLK_DIV3 STXC IO_BASE[0] TXD[1] TXD[2] TXD[3] LVDD CLKO VSS LCLK/XTALIN XTALOUT VSS EECS EECK EEDI EEDO LVDD SAL[0] SAL[1] SAL[2] SAH[0] SAH[1] SAH[2] NC NC VSS NC NC NC /CS NC RDY /RESET RESET LVDD 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AX88196 LOCAL CPU BUS 10/100BASE MAC CONTROLLER (for x86 Interface) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 HVDD IO_BASE[1] IO_BASE[2] PD0 PD1 VSS PD2 PD3 PD4 PD5 LVDD PD6 PD7 /ERR SLCT VSS PE /ACK BUSY /STRB LVDD /ATFD /INIT /SLIN VSS NC SD[0] SD[1] SD[2] SD[3] VSS SD[4] Fig - 4 AX88196 Pin Connection Diagram for 80x86 Mode SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] SA[9] VSS IRQ NC /IOWR /IORD NC NC /BHE HVDD SD[15] SD[14] SD[13] SD[12] VSS SD[11] SD[10] SD[9] SD[8] HVDD SD[7] SD[6] SD[5] 7 ASIX ELECTRONICS CORPORATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AX88196 Local CPU BUS MAC Controller 1.3.3 AX88196 Pin Connection Diagram for MC68K Mode TXD[1] TXD[2] TXD[3] LVDD CLKO VSS LCLK/XTALIN XTALOUT VSS EECS EECK EEDI EEDO LVDD SAL[0] SAL[1] SAL[2] SAH[0] SAH[1] SAH[2] NC NC VSS NC NC NC /CS NC /DTACK /RESET RESET LVDD 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 TXD[0] TX_EN TX_CLK VSS MDC MDIO RXD[3] RXD[2] RXD[1] RXD[0] RX_CLK CRS COL RX_DV RX_ER VSS SCRS SRXD SRXC TEST SCOL HVDD /SLINK NC CPU[0] CPU[1] STXE VSS STXD /CLK_DIV3 STXC IO_BASE[0] AX88196 LOCAL CPU BUS 10/100BASE MAC CONTROLLER (for 68K Interface) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 HVDD IO_BASE[1] IO_BASE[2] PD0 PD1 VSS PD2 PD3 PD4 PD5 LVDD PD6 PD7 /ERR SLCT VSS PE /ACK BUSY /STRB LVDD /ATFD /INIT /SLIN VSS NC SD[0] SD[1] SD[2] SD[3] VSS SD[4] Fig - 5 AX88196 Pin Connection Diagram for MC68K Mode /UDS SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] SA[9] VSS /IRQ NC R/W NC NC NC /LDS HVDD SD[15] SD[14] SD[13] SD[12] VSS SD[11] SD[10] SD[9] SD[8] HVDD SD[7] SD[6] SD[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 8 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 1.3.4 AX88196 Pin Connection Diagram for MCS-51 Mode TXD[0] TX_EN TX_CLK VSS MDC MDIO RXD[3] RXD[2] RXD[1] RXD[0] RX_CLK CRS COL RX_DV RX_ER VSS SCRS SRXD SRXC TEST SCOL HVDD /SLINK NC CPU[0] CPU[1] STXE VSS STXD /CLK_DIV3 STXC IO_BASE[0] TXD[1] TXD[2] TXD[3] LVDD CLKO VSS LCLK/XTALIN XTALOUT VSS EECS EECK EEDI EEDO LVDD SAL[0] SAL[1] SAL[2] SAH[0] SAH[1] SAH[2] NC NC VSS NC NC NC /CS /PSEN NC /RESET RESET LVDD 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AX88196 LOCAL CPU BUS 10/100BASE MAC CONTROLLER (for MCS-51 Interface) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 HVDD IO_BASE[1] IO_BASE[2] PD0 PD1 VSS PD2 PD3 PD4 PD5 LVDD PD6 PD7 /ERR SLCT VSS PE /ACK BUSY /STRB LVDD /ATFD /INIT /SLIN VSS NC SD[0] SD[1] SD[2] SD[3] VSS SD[4] Fig - 6 AX88196 Pin Connection Diagram for MCS-51 Mode SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] SA[9] VSS /IRQ NC /IOWR /IORD NC NC NC HVDD NC NC NC NC VSS NC NC NC NC HVDD SD[7] SD[6] SD[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 2.0 Signal Description The following terms describe the AX88196 pin-out: All pin names with the “/” suffix are asserted low. The following abbreviations are used in following Tables. I O I/O OD Input Output Input/Output Open Drain PU PD P Pull Up Pull Down Power Pin 2.1 Local CPU Bus Interface Signals Group SIGNAL SAL[2:0] TYPE I/PD PIN NO. 113 – 111 DESCRIPTION System Address Select Low : Signals SAL[2:0] are additional address signal input lines which active low enable higher I/O address decoder on chip. System Address Select High : Signals SAH[2:0] are additional address signal input lines which active high enable higher I/O address decoder on chip. System Address : Signals SA[9:0] are address bus input lines which lower I/O spaces on chip. SA[0] also means Upper Data Strobe (/UDS) active low signal in 68K application mode Bus High Enable or Lower Data Strobe : Bus High Enable is active low signal in some 16 bit application mode which enable high bus (SD[15:8]) active. The signal also name as Lower Data Strobe (LDS) for 68K application mode. System Data Bus : Signals SD[15:0] constitute the bi-directional data bus. SAH[2:0] I/PU 116 – 114 SA[9:1], SA[0]/UDS /BHE or /LDS SD[15:0] I 10 – 1 I 18 I/O IREQ/IREQ O 20 – 23, 25 – 28, 30 – 33, 35 – 38 12 RDY/DTACK OD 125 /CS /IORD /IOWR or R/W /OCS16 I I I 123 15 14 OD 120 Interrupt Request : When ISA BUS or 80186 CPU mode is select. IREQ is asserted high to indicate the host system that the chip requires host software service. When MC68K or MCS-51 CPU mode is select. /IREQ is asserted low to indicate the host system that the chip requires host software service. Ready : This signal is set low to insert wait states during Remote DMA transfer. /Dtack : When Motorola CPU type is select, the pin is active low inform CPU that data is accepted. Chip Select When the /CS signal is asserted, the chip is selected. I/O Read :The host asserts /IORD to read data from AX88196 I/O space. When Motorola CPU type is select , the pin is useless. I/O Write :The host asserts /IOWR to write data into AX88196 I/O space. When Motorola CPU type is select, the pin is active high for read operation at the same time. I/O is 16 Bit Port : The /IOIS16 is asserted when the address at the range corresponds to an I/O address to which the chip responds, and the I/O port addressed is capable of 16-bit access. 10 ASIX ELECTRONICS CORPORATION AX88196 AEN or /PSEN I/PD 124 Local CPU BUS MAC Controller Address Enable : The signal is asserted when the address bus is available for DMA cycle. When negated (low), AX88196 an I/O slave device may respond to addresses and I/O command. PSEN : This signal is active low for 8051 program access. For I/O device, AX88196, this signal is active high to access the chip. This signal is for 8051 bus application only. Tab - 1 Local CPU bus interface signals group 2.2 MII interface signals group SIGNAL RXD[3:0] CRS RX_DV TYPE I I I PIN NO. 90 – 87 85 83 DESCRIPTION Receive Data : RXD[3:0] is driven by the PHY synchronously with respect to RX_CLK. Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either the transmit or receive medium is non-idle. Receive Data Valid : RX_DV is driven by the PHY synchronously with respect to RX_CLK. Asserted high when valid data is present on RXD [3:0]. Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is asserted for one or more RX_CLK periods to indicate to the port that an error has detected. Receive Clock : RX_CLK is a continuous clock that provides the timing reference for the transfer of the RX_DV,RXD[3:0] and RX_ER signals from the PHY to the MII port of the repeater. Collision : this signal is driven by PHY when collision is detected. Transmit Enable : TX_EN is transition synchronously with respect to the rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles on TXD [3:0] for transmission. Transmit Data : TXD[3:0] is transition synchronously with respect to the rising edge of TX_CLK. For each TX_CLK period in which TX_EN is asserted, TXD[3:0] are accepted for transmission by the PHY. Transmit Clock : TX_CLK is a continuous clock from PHY. It provides the timing reference for the transfer of the TX_EN and TXD[3:0] signals from the MII port to the PHY. Station Management Data Clock : The timing reference for MDIO. All data transfers on MDIO are synchronized to the rising edge of this clock. MDC is a 2.5MHz frequency clock output. Station Management Data Input / Output : Serial data input/output transfers from/to the PHYs . The transfer protocol conforms to the IEEE 802.3u MII specification. RX_ER I 82 RX_CLK I 86 COL TX_EN I O 84 95 TXD[3:0] O 99 – 96 TX_CLK I 94 MDC O 92 MDIO I/O/PU 91 Tab - 2 MII interface signals group 11 ASIX ELECTRONICS CORPORATION AX88196 2.3 EEPROM Signals Group SIGNAL EECS EECK EEDI EEDO TYPE O O O I/PU PIN NO. 106 107 108 109 Local CPU BUS MAC Controller DESCRIPTION EEPROM Chip Select : EEPROM chip select signal. EEPROM Clock : Signal connected to EEPROM clock pin. EEPROM Data In : Signal connected to EEPROM data input pin. EEPROM Data Out : Signal connected to EEPROM data output pin. Tab - 3 EEPROM bus interface signals group 2.4 SNI Interface pins group SIGNAL STXC STXD TYPE I O PIN NO. 66 68 DESCRIPTION Transmit Clock : this signal is driven by PHY with 20MHz clock. Transmit Data : STXD is transition synchronously with respect to the rising edge of STXC. For each STXC period in which STXE is asserted, STXD is accepted for transmission by the PHY. Transmit Enable : STXE is transition synchronously with respect to the rising edge of STXC. STXE indicates that the port is presenting data on STXD for transmission. Collision : this signal is driven by PHY when collision is detected. Receive Clock : SRXC is driven by PHY for received data synchronization. Receive Data : SRXD is driven by the PHY synchronously with respect to SRXC. Carrier Sense : Asynchronous signal SCRS is asserted by the PHY when either the transmit or receive medium is non-idle. Link indicator : Active low indicate the SNI interface is link to network. When SNI is not used must keep the pin no connection or pull high the signal. STXE O 70 SCOL SRXC SRXD SCRS /SLINK I I I I I/PU 76 78 79 80 74 Tab - 4 Serial Network Interface pins group 2.5 Standard Printer Port Interface pins group SIGNAL PD[7:0] TYPE I/O/PU PIN NO. 52, 53 55-58 60, 61 46 47 48 50 51 41 42 43 DESCRIPTION Parallel Data :The bi-directional parallel data bus is used to transfer information between CPU and peripherals. Default serve as input, using /DOE bit of register offset x1Ah to set the direction. Busy : This is a status input from the printer, high indicating that the printer is not ready to receive new data. Acknowledge : A low active input from the printer indicating that it has received the data and is ready to accept new data. Paper Empty : A status input from the printer, high indicating that the printer is out of paper. Slect : This high active input from the printer indicating that it has power on. Error : A low active input from the printer indicating that there is an error condition at the printer. Slect In : This active low output selects the printer. Init : This signal is used to initiate the printer when low. Auto Feed :This output goes low to cause the printer to automatically 12 BUSY /ACK PE SLCT /ERR /SLCTIN /INIT /ATFD I I I I I O O O ASIX ELECTRONICS CORPORATION AX88196 /STRB O 45 Local CPU BUS MAC Controller feed one line after each line is printed. Strobe : A low active pulse on this output is used to strobe the print data into the printer. Tab - 5 Standard Printer Port Interface pins group 2.6 Power on configuration setup signals pins group SIGNAL IO_BASE[2:0] TYPE I /PU PIN NO. 62, 63,65 DESCRIPTION IO_BASE[2] IO_BASE[1] IO_BASE[0] IO_BASE 0 0 0 300h 0 0 1 320h 0 1 0 340h 0 1 1 360h 1 0 0 380h 1 0 1 3A0h 1 1 0 200h 1 1 1 220h CPU[1] CPU[0] CPU TYPE 0 0 ISA BUS 0 1 80186 1 0 MC68K 1 1 MCS-51 (805X) CPU[1:0] I/PU 71, 72 Tab - 6 Power on configuration setup pins group 2.7 Miscellaneous pins group SIGNAL LCLK/XTALIN TYPE I DESCRIPTION CMOS Local Clock : A 25Mhz clock, +/- 100 ppm, 40%-60% duty cycle. Crystal Oscillator Input : A 25Mhz crystal, +/- 25 ppm can be connected across XTALIN and XTALOUT. 104 Crystal Oscillator Output : A 25Mhz crystal, +/- 25 ppm can be connected across XTALIN and XTALOUT. If a single-ended external clock (LCLK) is connected to XTALIN, the crystal output pin should be left floating. 101 Clock Output : This clock is source from LCLK/XTALIN. 67 Clock Devide 3 Enable : Active low to enable the devided 3 circuit. That internally devides LCLK/XTALIN input frequeny by 3 and then feed into internal circuit for system clock used. Default value set to logic high, this function is disabled. 127 Reset : Reset is active high then place AX88196 into reset mode immediately. During Falling edge the AX88196 loads the power on setting data. User can select either RESET or /RESET for applications. 126 /Reset : Reset is active low then place AX88196 into reset mode immediately. During rising edge the AX88196 loads the power on setting data. User can select either RESET or /RESET for applications. 77 Test Pin : Active LOW The pin is just for test mode setting purpose only. Must be pull high when normal operation. 13, 16, 17, No Connection : for manufacturing test only. 39, 73, 117, 13 ASIX ELECTRONICS CORPORATION PIN NO. 103 XTALOUT O CLKO /CLK_DIV3 O I/PU RESET I/PD /RESET I/PU /TEST I/PU NC N/A AX88196 LVDD P Local CPU BUS MAC Controller 118, 121, 122 44, 54, Power Supply : +3.3V DC. 100, 110, 128 19, 29, 64, Power Supply : +5V DC. 75 Note : for pure 3.3V single power solution, all the HVDD pin can connect to +3.3V. Care should be taken that HVDD input power must be greater or equal ( > = ) than LVDD. 11, 24, 34, Power Supply : +0V DC or Ground Power. 40, 49,59, 69, 81,93, 102, 105, 119 HVDD P VSS P Tab - 7 Miscellaneous pins group 14 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 3.0 Memory and I/O Mapping There are four memory or I/O mapping used in AX88196. 1. 2. 3. EEPROM Memory Mapping I/O Mapping Local Memory Mapping 3.1 EEPROM Memory Mapping User can define by themselves and can access via I/O address offset 14H MII/EEPROM registers 3.2 I/O Mapping SYSTEM I/O OFFSET 0000H 001FH Tab - 8 I/O Address Mapping FUNCTION MAC CORE REGISTER 3.3 SRAM Memory Mapping OFFSET 4000H 7FFF Tab - 9 Local Memory Mapping FUNCTION NE2000 COMPATABLE MODE 8K X 16 SRAM BUFFER 15 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 4.0 Registers Operation All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS in the Command Register. PAGE 0 (PS1=0,PS0=0) OFFSET 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H, 11H 12H 13H 14H 15H 16H 17H 18H - 1AH 1BH - 1EH 1FH READ Command Register ( CR ) Page Start Register ( PSTART ) Page Stop Register ( PSTOP ) Boundary Pointer ( BNRY ) Transmit Status Register ( TSR ) Number of Collisions Register ( NCR ) Current Page Register ( CPR ) Interrupt Status Register ( ISR ) Current Remote DMA Address 0 ( CRDA0 ) Current Remote DMA Address 1 ( CRDA1 ) Reserved Reserved Receive Status Register ( RSR ) Frame Alignment Errors ( CNTR0 ) CRC Errors ( CNTR1 ) Missed Packet Errors ( CNTR2 ) Data Port IFGS1 IFGS2 MII/EEPROM Access Inter-frame Gap (IFG) Reserved Standard Printer Port (SPP) Reserved Reset WRITE Command Register ( CR ) Page Start Register ( PSTART ) Page Stop Register ( PSTOP ) Boundary Pointer ( BNRY ) Transmit Page Start Address ( TPSR ) Transmit Byte Count Register 0 ( TBCR0 ) Transmit Byte Count Register 1 ( TBCR1 ) Interrupt Status Register ( ISR ) Remote Start Address Register 0 ( RSAR0 ) Remote Start Address Register 1 ( RSAR1 ) Remote Byte Count 0 ( RBCR0 ) Remote Byte Count 1 ( RBCR1 ) Receive Configuration Register ( RCR ) Transmit Configuration Register ( TCR ) Data Configuration Register ( DCR ) Interrupt Mask Register ( IMR ) Data Port IFGS1 IFGS2 MII/EEPROM Access Test Register Inter-frame Gap (IFG) Reserved Standard Printer Port (SPP) Reserved Reserved Tab - 10 Page 0 of MAC Core Registers Mapping 16 ASIX ELECTRONICS CORPORATION AX88196 PAGE 1 (PS1=0,PS0=1) OFFSET 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H, 11H 12H 13H 14H 15H 16H 17H 18H - 1AH 1BH - 1EH 1FH READ Command Register ( CR ) Physical Address Register 0 ( PARA0 ) Physical Address Register 1 ( PARA1 ) Physical Address Register 2 ( PARA2 ) Physical Address Register 3 ( PARA3 ) Physical Address Register 4 ( PARA4 ) Physical Address Register 5 ( PARA5 ) Current Page Register ( CPR ) Multicast Address Register 0 ( MAR0 ) Multicast Address Register 1 ( MAR1 ) Multicast Address Register 2 ( MAR2 ) Multicast Address Register 3 ( MAR3 ) Multicast Address Register 4 ( MAR4 ) Multicast Address Register 5 ( MAR5 ) Multicast Address Register 6 ( MAR6 ) Multicast Address Register 7 ( MAR7 ) Data Port Inter-frame Gap Segment 1 IFGS1 Inter-frame Gap Segment 2 IFGS2 MII/EEPROM Access Inter-frame Gap (IFG) Reserved Standard Printer Port (SPP) Reserved Reset Local CPU BUS MAC Controller WRITE Command Register ( CR ) Physical Address Register 0 ( PAR0 ) Physical Address Register 1 ( PAR1 ) Physical Address Register 2 ( PAR2 ) Physical Address Register 3 ( PAR3 ) Physical Address Register 4 ( PAR4 ) Physical Address Register 5 ( PAR5 ) Current Page Register ( CPR ) Multicast Address Register 0 ( MAR0 ) Multicast Address Register 1 ( MAR1 ) Multicast Address Register 2 ( MAR2 ) Multicast Address Register 3 ( MAR3 ) Multicast Address Register 4 ( MAR4 ) Multicast Address Register 5 ( MAR5 ) Multicast Address Register 6 ( MAR6 ) Multicast Address Register 7 ( MAR7 ) Data Port Inter-frame Gap Segment 1 IFGS1 Inter-frame Gap Segment 2 IFGS2 MII/EEPROM Access Test Register Inter-frame Gap (IFG) Reserved Standard Printer Port (SPP) Reserved Reserved Tab - 11 Page 1 of MAC Core Registers Mapping 17 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 4.1 Command Register (CR) Offset 00H (Read/Write) FIELD 7:6 NAME DESCRIPTION PS1,PS0 PS1,PS0 : Page Select The two bit selects which register page is to be accessed. PS1 PS0 00 page 0 01 page 1 RD2,RD1 RD2,RD1,RD0 : Remote DMA Command ,RD0 These three encoded bits control operation of the Remote DMA channel. RD2 could be set to abort any Remote DMA command in process. RD2 is reset by AX88196 when a Remote DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA has been aborted. The Remote Start Address are not restored to the starting address if the Remote DMA is aborted. RD2 RD1 RD0 0 0 0 Not allowed 0 0 1 Remote Read 0 1 0 Remote Write 0 1 1 Not allowed 1 X X Abort / Complete Remote DMA TXP TXP : Transmit Packet This bit could be set to initiate transmission of a packet START START : This bit is used to active AX88196 operation. STOP STOP : Stop AX88196 This bit is used to stop the AX88196 operation. 5:3 2 1 0 4.2 Interrupt Status Register (ISR) Offset 07H (Read/Write) FIELD 7 NAME DESCRIPTION RST Reset Status : Set when AX88196 enters reset state and cleared when a start command is issued to the CR. Writing to this bit is no effect. RDC Remote DMA Complete Set when remote DMA operation has been completed CNT Counter Overflow Set when MSB of one or more of the Tally Counters has been set. OVW OVERWRITE : Set when receive buffer ring storage resources have been exhausted. TXE Transmit Error Set when packet transmitted with one or more of the following errors n Excessive collisions n FIFO Underrun RXE Receive Error Indicates that a packet was received with one or more of the following errors CRC error Frame Alignment Error FIFO Overrun Missed Packet PTX Packet Transmitted Indicates packet transmitted with no error PRX Packet Received Indicates packet received with no error. 6 5 4 3 2 1 0 18 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 4.3 Interrupt mask register (IMR) Offset 0FH (Write) FIELD 7 6 5 4 3 2 1 0 NAME RDCE CNTE OVWE TXEE RXEE PTXE PRXE DESCRIPTION Reserved DMA Complete Interrupt Enable. Default “low” disabled. Counter Overflow Interrupt Enable. Default “low” disabled. Overwrite Interrupt Enable. Default “low” disabled. Transmit Error Interrupt Enable. Default “low” disabled. Receive Error Interrupt Enable. Default “low” disabled. Packet Transmitted Interrupt Enable. Default “low” disabled. Packet Received Interrupt Enable. Default “low” disabled. 4.4 Data Configuration Register (DCR) Offset 0EH (Write) FIELD 7 6:2 1 NAME DESCRIPTION RDCR Remote DMA always completed Reserved BOS Byte Order Select 0: MS byte placed on AD15:AD8 and LS byte on AD7-AD0 (80186). 1: MS byte placed on AD7::AD0 and LS byte on AD15:AD0(MC68K) WTS Word Transfer Select 0 : Selects byte-wide DMA transfers. 1 : Selects word-wide DMA transfers. 0 4.5 Transmit Configuration Register (TCR) Offset 0DH (Write) FIELD 7 NAME DESCRIPTION FDU Full Duplex : This bit indicates the current media mode is Full Duplex or not. 0 : Half duplex 1 : Full duplex PD Pad Disable 0 : Pad will be added when packet length less than 60. 1 : Pad will not be added when packet length less than 60. RLO Retry of late collision 0 : Don’t retransmit packet when late collision happens. 1 : Retransmit packet when late collision happens. Reserved LB1,LB0 Encoded Loop-back Control These encoded configuration bits set the type of loop-back that is to be performed. LB1 LB0 Mode 0 0 0 Normal operation Mode 1 0 1 Internel NIC loop-back Mode 2 1 0 PHYcevisor loop-back CRC Inhibit CRC 0 : CRC appended by transmitter. 1 : CRC inhibited by transmitter. 6 5 4:3 2:1 0 19 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 4.6 Transmit Status Register (TSR) Offset 04H (Read) FIELD 7 6:4 3 2 1 0 NAME DESCRIPTION OWC Out of window collision Reserved ABT Transmit Aborted Indicates the AX88196 aborted transmission because of excessive collision. COL Transmit Collided Indicates that the transmission collided at least once with another station on the network. Reserved PTX Packet Transmitted Indicates transmission without error. 4.7 Receive Configuration (RCR) Offset 0CH (Write) FIELD 7 6 NAME DESCRIPTION Reserved INTT Interrupt Trigger Mode for ISA and 80186 modes 0 : Low active 1 : High active (default) Interrupt Trigger Mode for MCS-51 and MC68K modes 0 : High active 1 : Low active (default) MON Monitor Mode 0 : Normal Operation 1 : Monitor Mode, the input packet will be checked on NODE ADDRESS and CRC but not buffered into memory. PRO PRO : Promiscuous Mode Enable the receiver to accept all packets with a physical address. AM AM : Accept Multicast Enable the receiver to accept packets with a multicast address. That multicast address must pass the hashing array. AB AB : Accept Broadcast Enable the receiver to accept broadcast packet. AR AR : Accept Runt Enable the receiver to accept runt packet. SEP SEP : Save Error Packet Enable the receiver to accept and save packets with error. 5 4 3 2 1 0 4.8 Receive Status Register (RSR) Offset 0CH (Read) FIELD 7 6 5 4 3 2 1 0 NAME DIS PHY MPA FO FAE CR PRX DESCRIPTION Reserved Receiver Disabled Multicast Address Received. Missed Packet FIFO Overrun Frame alignment error. CRC error. Packet Received Intact 20 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 4.9 Inter-frame gap (IFG) Offset 16H (Read/Write) FIELD 7 6:0 NAME DESCRIPTION Reserved IFG Inter-frame Gap. Default value 15H. 4.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) FIELD 7 6:0 NAME DESCRIPTION Reserved IFG Inter-frame Gap Segment 1. Default value 0cH. 4.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) FIELD 7 6:0 NAME DESCRIPTION Reserved IFG Inter-frame Gap Segment 2. Default value 11H. 4.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write) FIELD 7 6 5 4 3 2 1 NAME DESCRIPTION EECLK EECLK EEPROM Clock EEO EEO EEPROM Data Out EEI EEI EEPROM Data In EECS EECS EEPROM Chip Select MDO MDO MII Data Out MDI MDI MII Data In MDIR MII STA MDIO signal Direction MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit let MDIO as output signal. MDC MDC MII Clock 0 4.13 Test Register (TR) Offset 15H (Write) FIELD 7 6 NAME DESCRIPTION Reserved MPSEL Media Priority Select : default value is logic 0 MPSEL /SLINK Media Selected 0 0 SNI 0 1 MII 1 x Depand on MPSET bit MPSET Media Set by Program : The signal is valid only when MPSEL is set to high. When MPSET is logic 0 , SNI is selected. When MPSET is logic 1 , MII is selected. TF16T Test for Collision, default value is logic 0 TPE Test pin Enable, default value is logic 0 IFG Select Test Pins Output, default value is logic 0 5 4 3 2:0 21 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 4.14 SPP Data Port Register (SPP_DPR) Offset 18H (Read/Write) FIELD 7:0 NAME DP Printer Data Port DESCRIPTION 4.15 SPP Status Port Register (SPP_SPR) Offset 19H (Read) FIELD 7 6 5 4 3 2:0 NAME /BUSY /ACK PE SLCT /ERR DESCRIPTION Reading a ‘0’ indicates that the printer is not ready to receive new data. Reading a ‘0’ indicates that the printer has received the data and is ready to accept new data. Reading a ‘1’ indicates that the printer is out of paper. Reading a ‘1’ indicates that the printer has power on. Reading a ‘0’ indicates that there is an error condition at the printer. Reserved 4.16 SPP Command Port Register (SPP_CPR) Offset 1AH (Read/Write) FIELD 7:6 5 4 3 2 1 0 NAME /DOE IRQEN SLCTIN /INIT ATFD STRB DESCRIPTION Reserved Seting to ‘0’ enable print data output to printer. Default sets to ‘1’. IRQ enable : printer port interrupt is not supportted. Seting to ‘1’ selects the printer. Seting to ‘0’ initiates the printer Seting to ‘1’ causes the printer to automatically feed one line after each line is printed. Seting a low-high-low pulse on this register is used to strobe the print data into the printer. 22 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 5.0 CPU I/O Read and Write Functions The AX88196 supports four kinds of CPU/BUS types access function, including ISA, 80186, MC68000 and MCS51. These Access methods are described as the following sections. 5.1 ISA bus type access functions. ISA bus I/O Read function Function Mode /CS /BHE Standby Mode H X Byte Access L H L H Word Access L L ISA bus I/O Write function Function Mode /CS /BHE Standby Mode H X Byte Access L H L H Word Access L L A0 X L H L /IORD X L L L /IOWR X H H H SD[15:8] High-Z Not Valid Not Valid Odd-Byte SD[7:0] High-Z Even-Byte Odd-Byte Even-Byte A0 X L H L /IORD X H H H /IOWR X L L L SD[15:8] X X X Odd-Byte SD[7:0] X Even-Byte Odd-Byte Even-Byte 5.2 80186 CPU bus type access functions. 80186 CPU bus I/O Read function Function Mode /CS /BHE Standby Mode H X Byte Access L H L L Word Access L L 80186 CPU bus I/O Write function Function Mode /CS /BHE Standby Mode H X Byte Access L H L L Word Access L L A0 X L H L /IORD X L L L /IOWR X H H H SD[15:8] High-Z Not Valid Odd-Byte Odd-Byte SD[7:0] High-Z Even-Byte Not Valid Even-Byte A0 X L H L /IORD X H H H /IOWR X L L L SD[15:8] X X Odd-Byte Odd-Byte SD[7:0] X Even-Byte X Even-Byte 23 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 5.3 MC68K CPU bus type access functions. 68K bus I/O Read function Function Mode /CS /UDS Standby Mode H X Byte Access L H L L Word Access L L 68K bus I/O Write function Function Mode /CS /UDS Standby Mode H X Byte Access L H L L Word Access L L /LDS X L H L R/W X H H H SD[15:8] High-Z Not Valid Even-Byte Even-Byte SD[7:0] High-Z Odd-Byte Not Valid Odd-Byte /LDS X L H L R/W X L L L SD[15:8] X X Even-Byte Even-Byte SD[7:0] X Odd-Byte X Odd-Byte 5.4 MCS-51 CPU bus type access functions. 8051 bus I/O Read function Function Mode /CS /PSEN Standby Mode H X X L Byte Access L H L H 8051 bus I/O Write function Function Mode /CS /PSEN Standby Mode H X X L Byte Access L H L H SA0 X X L H /IORD X X L L /IOWR X X H H SD[15:8] High-Z High-Z Not Valid Not Valid SD[7:0] High-Z High-Z Even-Byte Odd-Byte SA0 X X L H /IORD X X H H /IOWR X X L L SD[15:8] X X X X SD[7:0] X X Even-Byte Odd-Byte 24 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 6.0 Electrical Specification and Timings 6.1 Absolute Maximum Ratings SYM Min Max Units Ta 0 +85 °C Ts -55 +150 °C HVdd -0.3 +6 V LVdd -0.3 +4.6 V HVin -0.3 HVdd+0.5 V LVin -0.3 LVdd+0.5 V Output Voltage HVout -0.3 HVdd+0.5 V LVin -0.3 LVdd+0.5 V Lead Temperature (soldering 10 seconds maximum) Tl -55 +220 °C Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability. Note : The power supply voltages must always fulfill HVdd >= LVdd inequality. Operating Temperature Storage Temperature Supply Voltage Supply Voltage Input Voltage Description 6.2 General Operation Conditions Description Operating Temperature Supply Voltage SYM Min Ta 0 HVdd +4.75V LVdd +2.70 +3.00 Tpy 25 +5.00V +3.00 +3.30 Max +75 +5.25V +3.30 +3.60 Units °C V V V Note : The power supply voltages must always fulfill HVdd >= LVdd inequality. 6.3 DC Characteristics (Vdd=5.0V, Vss=0V, Ta=0°C to 75°C) Description Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Input Leakage Current Output Leakage Current (Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 75°C) Description Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Input Leakage Current Output Leakage Current Description Power Consumption (Dual power) Power Consumption (Single power 3.3V) SYM Vil Vih Vol Voh Iil Iol Min 2 Vdd-0.4 -1 -1 Tpy 0.8 0.4 +1 +1 Max Units V V V V uA uA SYM Vil Vih Vol Voh Iil Iol SYM DPt5v DPt3v SPt3v Min 1.9 Vdd-0.4 -1 -1 Min 20 32 50 Tpy 0.8 0.4 +1 +1 Tpy Max Units V V V V uA uA Units mA mA mA Max 25 ASIX ELECTRONICS CORPORATION AX88196 6.4 A.C. Timing Characteristics 6.4.1 XTAL / CLOCK Thigh LCLK/XTALIN Local CPU BUS MAC Controller Tr Tf Tcyc Tlow CLKO Tod Typ. Max 40* 16 20 24 16 20 24 1 4 10 * Note : The Tcyc can be from 16.6ns to 50ns, that is frequency from 60MHz to 20MHz. Tcyc Thigh Tlow Tr/Tf Tod CYCLE TIME CLK HIGH TIME CLK LOW TIME CLK SLEW RATE LCLK/XTALIN TO CLKO OUT DELAY Symbol Description Min Units ns ns ns ns 6.4.2 Reset Timing LCLK/XTALIN RESET /RESET Symbol Trst Reset pulse width Description Min 100 Typ. - Max - Units LClk 26 ASIX ELECTRONICS CORPORATION AX88196 6.4.3 ISA Bus Access Timing Tsu(AEN) AEN Local CPU BUS MAC Controller Th(AEN) Tsu(A) /BHE SA[9:0],SAL,SAH Tv(CS16-A) /IOCS16 Ten(RD) /IOWR,/IORD Th(A) Tdis(CS16-A) Tv(RDY) RDY Tdis(RDY) Tdis(RD) Read Data SD[15:0](Dout) Tsu(WR) Write Data SD[15:0](Din) DATA Input Establish DATA Valid Th(WR) Symbol Tsu(A) Th(A) Tsu(AEN) Th(AEN) Tv(CS16-A) Tdis(CS16-A) Tv(RDY) Tdis(RDY) Ten(RD) Tdis(RD) Tsu(WR) Th(WR) Description ADDRESS SETUP TIME ADDRESS HOLD TIME AEN SETUP TIME AEN HOLD TIME /IOCS16 VALID FROM ADDRESS CHANGE /IOCS16 DISABLE FROM ADDRESS CHANGE RDY VALID FROM /IORD OR /IOWR RDY DISABLE FROM /IORD OR /IOWR OUTPUT ENABLE TIME FROM /IORD OUTPUT DISABLE TIME FROM /IORD DATA SETUP TIME DATA HOLD TIME Min 0 5 0 5 0 0.5 5 5 Typ. - Max 20 6 20 20 4 - Units ns ns ns ns ns ns ns ns ns ns ns ns 27 ASIX ELECTRONICS CORPORATION AX88196 6.4.4 80186 Type I/O Access Timing Tsu(A) /BHE SA[9:0],SAL,SAH Tw(RW) /IOWR,/IORD Tv(RDY) RDY Ten(RD) Read Data SD[15:0](Dout) Tsu(WR) Write Data SD[15:0](Din) Local CPU BUS MAC Controller Th(A) Tdis(RDY) Tdis(RD) DATA Valid Th(WR) DATA Input Establish Symbol Tsu(A) Th(A) Tv(RDY) Tdis(RDY) Ten(RD) Tdis(RD) Tsu(WR) Th(WR) Tw(RW) Description ADDRESS SETUP TIME ADDRESS HOLD TIME RDY VALID FROM /IORD OR /IOWR RDY DISABLE FROM /IORD OR /IOWR OUTPUT ENABLE TIME FROM /IORD OUTPUT DISABLE TIME FROM /IORD DATA SETUP TIME DATA HOLD TIME /IORD OR /IOWR WIDTH TIME Min 0 5 0 0.5 5 5 *60 Typ. - Max 20 20 4 - Units ns ns ns ns ns ns ns ns ns *Note : 60 ns at internal operation clock is 20MHz. 50 ns at internal operation clock is 25MHz. 28 ASIX ELECTRONICS CORPORATION AX88196 6.4.5 68K Type I/O Access Timing Tsu(A) SA[9:1],SAL,SAH Tv(DS-WR) /UDS,/LDS Local CPU BUS MAC Controller Th(A) Tw(DS) Tdis(WR-DS) (Read) R/W Ten(DS) (Write) R/W Tv(DTACK) /DTACK Tdis(DTACK) Tdis(DS) (Read Data) SD[15:0](Dout) Tsu(DS) (Write Data) SD[15:0](Din) DATA Input Establish DATA Valid Th(DS) Symbol Tsu(A) Th(A) Tv(DS-WR) Tdis(WR-DS) Tv(DTACK) Tdis(DTACK) Ten(DS) Tdis(DS) Tsu(DS) Th(DS) Tw(DS) Description ADDRESS SETUP TIME ADDRESS HOLD TIME /UDS OR /LDS VALID FROM /W /W DISABLE FROM /UDS OR /LDS DACK VALID FROM /UDS OR /LDS DACK DISABLE FROM /UDS OR /LDS OUTPUT ENABLE TIME FROM /UDS OR /LDS OUTPUT DISABLE TIME FROM /UDS OR /LDS DATA SETUP TIME DATA HOLD TIME /UDS OR /LDS WIDTH TIME Min 0 5 0 5 0 0.5 5 5 *60 Typ. - Max 20 20 4 - Units ns ns ns ns ns ns ns ns ns ns ns *Note : 60 ns at internal operation clock is 20MHz. 50 ns at internal operation clock is 25MHz. 29 ASIX ELECTRONICS CORPORATION AX88196 6.4.6 8051 Bus Access Timing /PSEN Tsu(PSEN) Tsu(A) SA[9:0],SAL,SAH Ten(RD) /IOWR,/IORD Local CPU BUS MAC Controller Th(PSEN) Th(A) Tw(RW) Tv(RDY) (For Reference) RDY Tdis(RDY) Tdis(RD) Read Data SD[7:0](Dout) Tsu(WR) Write Data SD[7:0](Din) DATA Input Establish DATA Valid Th(WR) Symbol Tsu(A) Th(A) Tsu(PSEN) Th(PSEN) Ten(RD) Tdis(RD) Tsu(WR) Th(WR) Tw(RW) Description ADDRESS SETUP TIME ADDRESS HOLD TIME /PSEN SETUP TIME /PSEN HOLD TIME OUTPUT ENABLE TIME FROM /IORD OUTPUT DISABLE TIME FROM /IORD DATA SETUP TIME DATA HOLD TIME /IORD OR /IOWR WIDTH TIME Min 0 5 0 5 0.5 5 5 *60 Typ. - Max 20 4 - Units ns ns ns ns ns ns ns ns ns Note : 60 ns at internal operation clock 20MHz. 50 ns at internal operation clock 25MHz. 30 ASIX ELECTRONICS CORPORATION AX88196 6.4.7 MII Timing Ttclk Local CPU BUS MAC Controller Ttch Ttcl TXCLK Ttv TXD Tth TXEN Trclk Trch Trcl RXCLK Trs RXD Trh RXDV Trs1 RXER Symbol Ttclk Ttclk Ttch Ttch Trch Trch Ttv Tth Trclk Trclk Trch Trch Trcl Trcl Trs Trh Trs1 Description Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) low time(100Mbps) low time(10Mbps) Clock to data valid Data output hold time Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) low time(100Mbps) low time(10Mbps) data setup time data hold time RXER data setup time Min 14 140 14 140 5 14 140 14 140 6 10 10 Typ. 40 400 40 400 - Max 26 260 26 260 20 26 260 26 260 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 31 ASIX ELECTRONICS CORPORATION AX88196 6.4.8 SNI Timing Ttclk Local CPU BUS MAC Controller Ttch Ttcl STXC Ttv STXD Tth STXE Trclk Trch Trcl SRXC Trs SRXD Trh SCRS Symbol Ttclk Ttch Trch Ttv Tth Trclk Trch Trcl Trs Trh Cycle time(10Mbps) high time(10Mbps) low time(10Mbps) Clock to data valid Data output hold time Cycle time(10Mbps) high time(10Mbps) low time(10Mbps) data setup time data hold time Description Min 45 45 5 45 45 10 5 Typ. 100 100 - Max 55 55 26 55 55 - Units ns ns ns ns ns ns ns ns ns ns 32 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller 7.0 Package Information He E A A2 A1 Hd D pin 1 b e θ SYMBOL MIN. A1 A2 A b D E e Hd He L L1 θ 0 15.60 15.60 0.30 0.155 13.90 13.90 1.3 MILIMETER NOM 0.1 1.4 1.5 1.7 0.16 14.00 14.00 0.40 16.00 16.00 0.50 1.00 10 16.40 16.40 0.70 0.26 14.10 14.10 MAX 33 ASIX ELECTRONICS CORPORATION L L1 AX88196 Local CPU BUS MAC Controller Appendix A: Application Note A.1 Using Crystal 25MHz or 20MHz AX88196 CLKO To PHY 25MHz XTALIN XTALOUT 25MHz Crystal 8pf 2Mohm 8pf Note : The capacitors (8pf) may be various depend on the specification of crystal. While designing, please refer to the suggest circuit provided by crystal supplier. A.2 Using Oscillator 25MHz or 20MHz AX88190A CLKO To PHY 20MHz XTALIN XTALOUT NC 3.3V Power OSC 20MHz A.3 Using 60MHz Oscillator/Crystal AX88196 /CLK_DIV3 Pull Low Devided By 3 XTALIN CLKO 20MHz XTALOUT NC To PHY 60MHz 3.3V Power OSC 60MHz 34 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller A.4 Dual power (5V and 3.3V/3.0V) application RJ45 MAGNETIC +5V PHY/TxRx Optional EEPROM AX88196 +5V +5V HVdd +5V +3.3V LVdd +5V CPU I/F A.5 Single power (3.3V/3.0V) application RJ45 MAGNETIC +3.3V PHY/TxRx Optional EEPROM AX88196 +3.3V +3.3V HVdd +3.3V LVdd +3.3V +3.3V CPU I/F 35 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller A.6 Dual power (5V and 3.3V) application with 3.3V PHY The 510 and 1K Ohm resisters are just for voltage adjustment RXD[3:0] CRS RX_DV RX_ER RX_CLK COL TX_EN TXD[3:0] TX_CLK MDC MDIO AX88196 510 ohm 1k ohm RXD[3:0] CRS RX_DV RX_ER RX_CLK COL TX_EN TXD[3:0] TX_CLK MDC MDIO PHY 36 ASIX ELECTRONICS CORPORATION AX88196 Local CPU BUS MAC Controller Errata of AX88196 Version ED2 1. SNI (Serial Network Interface) has bug for HomePNA application. Solution: Using MII interface for HomePNA solution. Refer to “Demonstration Circuit” on page 37 to 41. 2. SPP (Standard Printer Port) is fail on 186 and 68K modes. Because of can't read out correct information of x19h status port. Solution: This version do not support SPP function on the two modes. If user want to use general purpose port for reading external status. Please using x18h data port to replaces it. 3. SPP command port readback value is from internal registers instead of external pins Solution: ASIX will not fix the problem at this moment. Care must be taken when doing the external pins diagnostic. 4. DTACK can’t fit 68K CPU timing in 68K mode Solution : Using the DTACK automatic insertion function in 68K CPU. 37 ASIX ELECTRONICS CORPORATION AX88196 10/100BASE Fast Ethernet MAC Controller Demonstration Circuit : AX88196 + Ethernet PHY + HomePNA 1M8 PHY AX88196 L 10BASE-T/100BASE-TX & 1M HomePNA ISA1 GND RESET 5V C2 0.1u C1 + 47u/16v B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 GND RESDRV +5V IRQ -5V DRQ -12V NOWS# +12V GND SMWTC# SMRDC LOWC# LORC# DAK# DRQ DAK# DRQ REFRSH# BCLK IRQ IRQ IRQ IRQ IRQ DAK# T/C BALE +5V OSC GND M16# IO16# IRQ IRQ IRQ IRQ IRQ DAK# DRQ DAK# DRQ DAK# DRQ DAK# DRQ +5V MASTER16# GND ISA VCC U2 3.3V C8 0.1u C9 + 47u/16v 4 OUT IN OUT ADJ/GND 3 2 1 5V 3.3V GND C10 0.1u C11 + 47u/16v IOCHK# D D D D D D D D CHRDY AEN SA SA SA SA SA SA SA SA SA SA