5962-0054001Q9A

Features • Integer Unit Based on SPARC V7 High-performance RISC Architecture • Optimized Integrated 32/64-bit Floating-point Unit • On-chip Peripherals – EDAC and Parity Generator and Checker – Memory Interface Chip Select Generator Waitstate Generation Memory Protection – DMA Arbiter – Timers General Purpose Timer (GPT) Real-time Clock Timer (RTCT) Watchdog Timer (WDT) – Interrupt Controller with 5 External Inputs – General Purpose Interface (GPI) – Dual UART Speed Optimized Code RAM Interface 8- or 40-bit boot-PROM (Flash) Interface IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes Fully Static Design Performance: 20 MIPs/5 MFlops (Double Precision) at SYSCLK = 25 MHz Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs Operating Range: 4.5V to 5.5V(1) -55 °C to +125°C Tested up to Total Dose of 300 KRADs (Si) according to MIL STD 883 Method 1019 SEU Event Rate Better than 3 E-8 Error/Component/Day (Worst Case) No Single Event Latch-up below an LET Threshold of 80 MeV/mg/cm 2 Quality Grades: ESCC with 9512/003 and QML-Q or V with 5962-00540 Package: 256 MQFPF; Bare Die 1. For 3.3V capability see the TSC695FL datasheet on the Atmel site. • • • • • • • • • • • Rad-Hard 32-bit SPARC Embedded Processor TSC695F Note: Description The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit RISC embedded processor implementing the SPARC architecture V7 specification. It has been developed with the support of the ESA (European Space Agency), and offers a full development environment for embedded space applications. The processor is manufactured using the Atmel 0.5 µm radiation tolerant ( ≥ 3 00 KRADs ( Si)) CMOS enhanced process (RTP). It has been specially designed for space, as it has on-chip concurrent transient and permanent error detection. The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers a high security watchdog, two timers, an interrupt controller, parallel and serial interfaces. Fault tolerance is supported using parity on internal/external buses and an EDAC on the external data bus. The design is highly testable with the support of an On-Chip Debugger (OCD), and a boundary scan through JTAG interface. Rev. 4118J–AERO–08/04 Block Diagram Figure 1. TSC695F Block Diagram TAP 32-bit Integer Unit DMA Arbiter Access Controller Wait State Controller Address Interface EDAC General Purpose Interface UART B UART A Interrupt Controller Parity Gen./Check. DMA Ctrl Clock & Parity Reset Managt Gen./Chk. 32/64-bit Floating-Point Unit Parity Gen./Chk. Mem Ctrl Ready/Busy Add.+Size+ASI Error Managt General Purpose Timer Real Time Clock Timer Watch Dog Data+Check bits Parities GPI bits RxD, TxD Interrupts Pin Descriptions Table 1. Pin Descriptions S ignal RA[31:0] RAPAR RASI[3:0] RSIZE[1:0] RASPAR CPAR D[31:0] CB[6:0] DPAR RLDSTO ALE DXFER LOCK RD WE WRT MHOLD MDS MEXC PROM8 BA[1:0] ROMCS ROMWRT MEMCS[9:0] MEMWR Type I/O, I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O O O O I O O I O O For pin assignment, refer to package section. Active Description 32-bit registered address bus Output buffer: 400 pF MHOLD+FHOLD +BHOLD+FCCV Output buffer: 400 pF Output buffer: 400 pF High Registered address bus parity 4-bit registered address space identifier 2-bit registered bus transaction size High High Registered ASI and SIZE parity Control bus parity 32-bit data bus 7-bit check-bit bus High High Low High High High Low High Low Low Low Low Low Low Low Low Data bus parity Registered atomic load-store Address latch enable Data transfer Bus lock Read access Write enable Advanced write Memory bus hold Memory data strobe Memory exception Select 8-bit wide PROM Latched address used for 8-bit wide boot PROM PROM chip select ROM write enable Memory chip select Memory write strobe 2 TSC695F 4118J–AERO–08/04 TSC695F Table 1. Pin Descriptions (Continued) Signal OE BUFFEN DDIR DDIR IOSEL[3:0] IOWR EXMCS BUSRDY BUSERR DMAREQ DMAGNT DMAAS DRDY IUERR CPUHALT SYSERR SYSHALT SYSAV NOPAR INULL INST FLUSH DIA RTC RxA/RxB TxA/TxB GPI[7:0] GPIINT EXTINT[4:0] EXTINTACK IWDE EWDINT WDCLK CLK2 SYSCLK RESET SYSRESET TMODE[1:0] DEBUG TCK TRST TMS TDI TDO VCCI/VSSI VCCO/VSSO Type O O O O O O O I I I O I O O O O I O I O O O O O I O I/O O I O I I I I O O I I I I I I I O Low High Low Low High High High High Active Low Low High Low Low Low Low Low Low Low Low High Low Low Low Low Low High Low High High High High High Description Memory output enable Data buffer enable Data buffer direction Data buffer direction I/O chip select I/O and exchange memory write strobe Exchange memory chip select Bus ready Bus error DMA request DMA grant DMA address strobe Data ready during DMA access IU error Processor (IU & FPU) halt and freeze System error System halt System availability No parity Integer unit nullify cycle Instruction fetch FPU instruction flush Delay instruction annulled Real Time Clock Counter output Receive data UART ’A’ and ’B’ Transmit data UART ’A’ and ’B’ GPI input/output GPI interrupt External interrupt External interrupt acknowledge Internal watch dog enable External watch dog input interrupt Watch dog clock Double frequency clock System clock Output reset System input reset Factory test mode Software debug mode Test (JTAG) clock Test (JTAG) reset Test (JTAG) mode select Test (JTAG) data input Test (JTAG) data output Main internal power Output driver power Output buffer: 400 pF Used to check the execute stage of IU instruction pipeline Input trigger Input trigger Input trigger Input trigger Input trigger Functional mode=00 pull-up ≈ 37 k Ω pull-up ≈ 37 k Ω pull-up ≈ 37 k Ω - Note: If not specified, the output buffer type is 150 pF, the input buffer type is TTL. 3 4118J–AERO–08/04 System Architecture The TSC695F is to be used as an embedded processor requiring only memory and application specific peripherals to be added to form a complete on-board computer. All other system support functions are provided by the core. Figure 2. System Architecture Based on TSC695F DMA Unit Ax[31:0] Xtd PROM Xchg Mem Boot PROM Master Local Memory Glue Logic Xtd RAM I/O 0 to I/O 3 DPAR DMAGNT DMAREQ DMAAS Xtd I/O (BUFFEN, DDIR) Xtd general MEMCtrl FPU Memory Interface RA[31:0] CB[6:0] (ROMCS, EXMCS, IOSEL[3:0], MEMWR, IOWR, OE, BUSRDY,...) RAMCtrl (MEMCS[9:0], MEMWR, OE) SYSCLK ALE RAM Memory DMA A[31:0] IU DMA D[31:0] (0 WS) Peripherals User Application TSC695F 4 TSC695F 4118J–AERO–08/04 TSC695F Product Description Integer Unit The Integer Unit (IU) is designed for highly dependable space and military applications, and includes support for error detection. The RISC architecture makes the creation of a processor that can execute instructions at a rate approaching one instruction per processor clock possible. To achieve that rate of execution, the IU employs a four-stage instruction pipeline that permits parallel execution of multiple instructions. • • Fetch - The processor outputs the instruction address to fetch the instruction. Decode - The instruction is placed in the instruction register and is decoded. The processor reads the operands from the register file and computes the next instruction address. Execute - The processor executes the instruction and saves the results in temporary registers. Pending traps are prioritized and internal traps are taken during this stage. Write - If no trap is taken, the processor writes the result to the destination register. • • All four stages operate in parallel, working on up to four different instructions at a time. A basic ‘single-cycle’ instruction enters the pipeline and completes infour cycles. By the time it reaches the write stage, three more instructions have entered and are moving through the pipeline behind it. So, after the first four cycles, a single-cycle instruction exits the pipeline and a single-cycle instruction enters the pipeline on every cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but they are called single cycle because with this type of instruction the processor can complete one instruction per cycle after the initial four-cycle delay. Floating-point Unit The FLoating Point Unit (FPU) is designed to provide execution of single and doubleprecision floating-point instructions concurrently with execution of integer instructions by the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floating-point standard. The FPU is designed for highly dependable space and military applications, and includes support for concurrent error detection and testability. The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and write stages (F, D, E and W). The fetch unit captures instructions and their addresses from the data and address buses. The decode unit contains logic to decode the floatingpoint instruction opcodes. The execution unit handles all instruction execution. The execution unit includes a floating-point queue (FP queue), which contains stored floatingpoint operate (FPop) instructions under execution and their addresses. The execution unit controls the load unit, the store unit, and the datapath unit. The FPU depends upon the IU to access all addresses and control signals for memory access. Floating-point loads and stores are executed in conjunction with the IU, which provides addresses and control signals while the FPU supplies or stores the data. Instruction fetch for integer and floating-point instructions is provided by the IU. The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR is a 32-bit status and control register. It keeps track of rounding modes, floating-point trap types, queue status, condition codes, and various IEEE exception information. The floating-point queue contains the floating-point instruction currently under execution, along with its corresponding address. 5 4118J–AERO–08/04 Instruction Set TSC695F instructions fall into six functional categories: load/store, arithmetic/logical/shift, control transfer, read/write control register, floating-point, and miscellaneous. Please refer to SPARC V7 Instruction-set Manual. Note: The execution of IFLUSH will cause an illegal instruction trap. On-chip Peripherals Memory Interface Table 2. Memory Mapping Memory Contents Boot PROM Start Address 0x 0000 0000 Size (bytes) 128K → 16M Data Size and Parity Options 8-bit mode 40-bit mode Extended PROM 0x 0100 0000 Max: 15M 8-bit mode 40-bit mode Exchange Memory System Registers RAM (8 blocks) Extended RAM I/O Area 0 I/O Area 1 I/O Area 2 I/O Area 3 Extended I/O Area Extended General 0x 01F0 0000 0x 01F8 0000 0x 0200 0000 0x 0400 0000 0x 1000 0000 0x 1100 0000 0x 1200 0000 0x 1300 0000 0x 1400 0000 0x 8000 0000 4k → 512k 512K (124 used) 8*32K → 8*4M Max: 192M 0 → 16M 0 → 16M 0 → 16M 0 → 16M Max: 1728M Max: 2G No parity/-All data sizes allowed Parity option/-All data sizes allowed No parity/-No EDAC/-Only byte write Parity + EDAC mandatory/-Only word write No parity/-No EDAC/-Only byte write Parity + EDAC mandatory/-Only word write The TSC695F is designed to allow easy interfacing to internal/external memory resources. Parity + EDAC option/-Only word write Parity/-Only word read/write access Parity + EDAC option/-All data sizes allowed System Registers The system registers are only writable by IU in the supervisor mode or by DMA during halt mode. Table 3. System Registers Address Map System Register Name System Control Register Software Reset Power Down System Fault Status Register Failing Address Register Error & Reset Status Register Test Control Register SYSCTR SWRST PDOWN SYSFSR FAILAR ERRRSR TESCTR Address 0x 01F8 0000 0x 01F8 0004 0x 01F8 0008 0x 01F8 00A0 0x 01F8 00A4 0x 01F8 00B0 0x 01F8 00D0 6 TSC695F 4118J–AERO–08/04 TSC695F Table 3. System Registers Address Map (Continued) System Register Name Memory Configuration Register I/O Configuration Register Waitstate Configuration Register Access Protection Segment 1 Base Register Access Protection Segment 1 End Register Access Protection Segment 2 Base Register Access Protection Segment 2 End Register Interrupt Shape Register Interrupt Pending Register Interrupt Mask Register Interrupt Clear Register Interrupt Force Register Watchdog Timer Register Watchdog Timer Trap Door Set Real Time Clock Timer Register Real Time Clock Timer Register General Purpose Timer Register General Purpose Timer Register Timers Control Register General Purpose Interface Configuration Register General Purpose Interface Data Register UART ’A’ Rx & Tx Register UART ’B’ Rx & Tx Register UART Status Register MCNFR IOCNFR WSCNFR APS1BR APS1ER APS2BR APS2ER INTSHR INTPDR INTMKR INTCLR INTFCR WDOGTR WDOGST RTCCR RTCSR GPTCR GPTSR TIMCTR GPICNFR GPIDATR UARTAR UARTBR UARTSR Address 0x 01F8 0010 0x 01F8 0014 0x 01F8 0018 0x 01F8 0020 0x 01F8 0024 0x 01F8 0028 0x 01F8 002C 0x 01F8 0044 0x 01F8 0048 0x 01F8 004C 0x 01F8 0050 0x 01F8 0054 0x 01F8 0060 0x 01F8 0064 0x 01F8 0080 0x 01F8 0084 0x 01F8 0088 0x 01F8 008C 0x 01F8 0098 0x 01F8 00A8 0x 01F8 00AC 0x 01F8 00E0 0x 01F8 00E4 0x 01F8 00E8 Wait-state and Time-out Generator It is possible to control the wait-state generation by programming a Wait-state Configuration Register. The maximum programmable number of wait-states is applied by default at reset. It is possible to program the number of wait-states for the following combinations: – – – – RAM read and write PROM read and write (i.e. EEPROM or Flash write) Exchange Memory read/write Four individual I/O peripherals read/write A bus time-out function of 256 system clock cycles is provided for the bus ready controlled memory areas, i.e., the Extended PROM, Exchange Memory, Extended RAM, 7 4118J–AERO–08/04 Extended I/O and the Extended General areas. EDAC The TSC695F includes a 32-bit EDAC (Error Detection And Correction). Seven bits (CB[6:0]) are used as check bits over the data bus. The Data Bus Parity signal (DPAR) is used to check and generate the odd parity over the 32-bit data bus. This means that altogether 40 bits are used when the EDAC is enabled. The TSC695F EDAC uses a 7-bit Hamming code which detects any double bit error on the 40-bit bus as a non-correctable error. In addition, the EDAC detects all bits stuck-atone and stuck-at-zero failure for any nibble in the data word as a non-correctable error. Stuck-at-one and stuck-at-zero for all 32 bits of the data word is also detected as a noncorrectable error. Memory and I/O Parity The TSC695F handles parity towards memory and I/O in a special way. The processor can be programmed to use no parity, only parity or parity and EDAC protection towards memory and to use parity or no towards I/O. The signal used for the parity bit is DPAR. Programming the Memory Configuration Register, the TSC695F provides chip selects for two redundant memory banks for replacement of faulty banks. • • Unimplemented Areas - Access to all unimplemented memory areas are handled by the TSC695F and detected as illegal. RAM Write Access Protection - The TSC695F can be programmed to detect and mask write accesses in any part of the RAM. The protection scheme is enabled only for data area, not for the instruction area. The programmable write access protection is based on two segments. Boot PROM Write Protection - The TSC695F supports a qualified PROM write for an 8-bit wide PROM and/or for a 40-bit wide PROM. Memory Redundancy Memory Access Protection • DMA DMA Interface The TSC695F supports Direct Memory Access (DMA). The DMA unit requests access to the processor bus by asserting the DMA request signal (DMAREQ). When the DMA unit receives the DMAGNT signal in response, the processor bus is granted. In case the processor is in the power-down mode the processor is permanent tri-stated, and a DMAREQ will directly give a DMAGNT. The TSC695F includes a DMA session time-out function. The TSC695F always has the lowest priority on the system bus. A trap is a vectored transfer of control to the supervisor through a special trap table that contains the first four instructions of each trap handler. The base address of the table is established by supervisor and the displacement, within the table, is determined by the trap type. Two categories of traps can appear. Bus Arbiter Traps 8 TSC695F 4118J–AERO–08/04 TSC695F Synchronous Traps Table 4. Synchronous Traps Trap Priority Trap Type (tt) Comments Sources: SYSRESET* pin software reset watchdog reset IU or System error reset Severe error requiring a re-boot TSC695F enters (if not masked) in halt or reset mode Error not removable, PC & nPC OK TSC695F enters (if not masked) in halt or reset mode Special case of non-restartable, precise error. TSC695F enters (if not masked) in halt or reset mode Retrying instruction but PC & nPC have to be re-adjusted TSC695F enters (if not masked) in halt or reset mode Retrying instruction TSC695F enters (if not masked) in halt or reset mode Parity error on control bus Parity error on data bus Parity error on address bus Access to protected or unimplemented area Uncorrectable error in memory Bus time out Bus error Reset Non-restartable, imprecise error Non-restartable, precise error Register file error Hardware Error Restartable, late error Restartable, precise error 1 2.1 2.2 2.3 2.4 2 2.5 – 64h 62h 65h 63h 61h Instruction access (Error on instruction fetch) 3 Illegal Instruction Privileged instruction FPU disabled Overflow Window Underflow 7 8 9.1 9.2 9.3 9.4 9.5 4 5 6 01h 02h 03h 04h 05h 06h 07h During SAVE instruction or trap taken During RESTORE instruction or RETT instruction Non-restartable error Data bus error Restartable error Sequence error Unimplemented FPop FPU exception Parity error on FPU data bus Can be removed restarting the instruction IEEE exceptions: 9 9.6 08h 4118J–AERO–08/04 – Memory address not aligned – – – Severe error, cannot restart the instruction – – Invalid operation Division by zero Overflow Underflow Inexact 9 Table 4. Synchronous Traps (Continued) Trap Data access exception (Error on data load) Tag overflow Trap instructions Priority Trap Type (tt) Comments Idem “instruction access” System register access violation TADDccTV and TSUBccTV instructions Trap on integer condition codes (Ticc) 10 11 12 09h 0Ah 80h to FFh Table 5. Interrupts or Asynchronous Traps Trap Watchdog time-out External INT 4 Real time clock timer General purpose timer External INT 3 External INT 2 DMA time-out DMA access error UART Error Correctable error in memory UART B UART A Data ready Transmitter ready Data ready Transmitter ready Priority 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Trap Type (tt) Comments 1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h 17h 16h 15h 14h 13h 12h Internal or external (EWDINT pin) EXTINTAK on only one of EXTINT[4:0] External INT 1 External INT 0 EXTINTAK on only one of EXTINT[4:0] EXTINTAK on only one of EXTINT[4:0] Logical OR of: IU hardware error masked IU error mode masked System hardware error masked Masked hardware errors 27 11h It is possible to mask each individual interrupt (except Watchdog time-out). The interrupts in the Interrupt Pending Register are cleared automatically when the interrupt is acknowledged. By programming the Interrupt Shape Register, it is possible to define the external interrupts to either be active low or active high and to define the external interrupts to either be edge or level sensitive. 10 TSC695F 4118J–AERO–08/04 – – EXTINTAK on only one of EXTINT[4:0] EXTINTAK on only one of EXTINT[4:0] – – – Data read OK but source not updated – – TSC695F Timers General Purpose Timer In software debug mode the timers are controlled by a system register bit and the external pin DEBUG. The General Purpose Timer (GPT) provides, in addition to a generalized counter function, a mechanism for setting the step size in which actual time counts are performed. GPT is clocked by the internal system clock. They are possible to program to be either of single-shot type or periodical type and in both cases generate an interrupt when the delay time has elapsed. The current value of the scaler and counter of the GPT can be read. Real Time Clock Timer The only functional differences between the two timers are that the Real Time Clock Timer (RTCT) has an 8-bit scaler (16-bit scaler for GPT) and that the RTCT interrupt has higher priority than the GPT interrupt. RTCT information is available on RTC output pin. Watchdog Timer Setting the external pin IWDE to VCC enables the internal watchdog timer. Otherwise the watchdog function must be externally provided. The watchdog is supplied from a separate external input (WDCLK). After reset, the timer is enabled and starts running with the maximum range. If the timer is not refreshed (reprogrammed) before the counter reaches zero value, an interrupt is sent. Simultaneo usly, the timer starts counting a reset time -out period. If the timer is not acknowledged before the reset time-out period elapses, a reset is applied to TSC695F. UARTs Two full duplex asynchronous receiver transmitters (UART) are included. In software debug mode the UART’s are controlled by system register bits. The data format of the UART’s is eight bits. It is possible to choose between even or odd parity, or no parity, and between one and two stop bits. The UART’s provide double buffering, i.e. each UART consists of a transmitter holding register, a receiver holding register, a transmitter shift register, and a receiver shift register. Each of these registers are 8-bit wide. For each UART a RX and TX Register is provided. The UART’s generate an interrupt each time a byte has been received or a byte has been sent. There is another interrupt to indicate errors. The baud rate of both the UART’s is programmable. The clock is derived either from the system clock or can use the watchdog clock. General Purpose Interface The General Purpose Interface (GPI) is an 8-bit parallel I/O port. Each pin can be configured as an input or an output. A falling or rising edge detection is made on each selected GPI inputs. Every input transition on GPI generates an external positive pulse on GPIINT pin of two SYSCLK width. Execution Modes Reset Mode Reset mode is entered when: – – – – The SYSRES input is asserted Software reset which is caused by the software writing to a Software Reset Register Watchdog reset which is caused by a Watchdog counter time-out Error reset which is caused by a hardware parity error 11 4118J–AERO–08/04 This RESET output has a minimum of 1024 SYSCLK width to allow the usage of Flash memories. The error and Reset Status Register contain the source of the last processor reset. Run Mode In this mode the IU/FPU is executing, while all peripherals are running (if software enabled). System Halt mode is entered when the SYSHALT input is asserted. In this mode, the IU and FPU are frozen, while the timers (includeing the internal watchdog timer) and UART’s are stopped. This mode is entered by writing to the Power-down Register. In this mode, the IU and FPU are frozen. The TSC695F leaves the power-down mode if an external interrupt is asserted. Error Halt mode is entered under the following circumstances: – – A internal hardware parity error. The IU enters error mode. System Halt Mode Power Down Mode Error Halt Mode The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRESET. Error Handler The TSC695F has one error output signal (SYSERR) which indicates that an unmasked error has occurred. Any error signalled on the error inputs from the IU and the FPU is latched and reflected in the Error and Reset Status Register. By default, an error leads to a processor halt. The TSC695F includes: – – – – – Parity checking and generation (if required) on the external data bus Parity checking on the external address bus Parity checking on ASI and SIZE Parity checking and generation on all system registers Parity generation and checking on the internal control bus to the IU Parity Checking All external parity checking can be disabled using the NOPAR signal. System Clock The TSC695F uses CLK2 clock input directly and creates a system clock signal by dividing CLK2 by two. It drives SYSCLK pin with a nominal 50% duty cycle for the application. It is highly recommended that only SYSCLK rising edge is used as reference as far as possible. The SYSAV bit in the Error and Reset Status Register can be used by software to indicate system availability. The TSC695F includes a number of software test facilities such as EDAC test, Parity test, Interrupt test, Error test and a simple Test Access Port. These test functions are controlled using the Test Control Register. System Availability Test Mode 12 TSC695F 4118J–AERO–08/04 TSC695F Test and Diagnostic Hardware Functions Test Access Port A variety of TSC695F test and diagnostic hardware functions, including boundary scan, internal scan, clock control and On-chip Debugger, are controlled through an IEEE 1149.1 (JTAG) standard Test Access Port (TAP). The TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695F chip. These pins are: • • • • • TCK (input): Test Clock TMS (input): Test Mode Select TDI (input): Test Data Input TDO (output): Test Data Output TRST (input): Test Reset Instruction Register Five standard instructions are supported by the TSC695F TAP. Binary Value 00. 0000 00. 0001 00. 0011 11. 1111 10. 0000 Name of Instruction EXTEST SAMPLE/PRELOAD INTEST BYPASS IDCODE Data Register Boundary Scan Register Boundary Scan Register Boundary Scan Register Bypass Register Device ID Register Scan Chain Accessed Boundary scan chain Boundary scan chain Boundary scan chain Bypass register ID register scan chain Debugging The design is highly testable with the support of an On-Chip Debugger (OCD), an internal and boundary scan through JTAG interface. 13 4118J–AERO–08/04 Electrical Characteristics Absolute Maximum Ratings Military Range............................................... -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Supply Voltage................................................... -0.5V to +7.0V Input Voltage......................................................-0.5V to +7.0V Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Characteristics Table 6. DC Characteristics at VDD 5V ± 10% Symbol VIL VIH trigger Parameter Input Low Voltage for trigger input Input High Voltage for trigger input Input Hysteresis for trigger input Input Low Voltage for TTL input Input High Voltage for TTL input Output Low Voltage for 400 pF buffer Output High Voltage for 400 pF buffer Output Low Voltage for 150 pF buffer Output High Voltage for 150 pF buffer Min – 3.0 – – 2.2 Typ – – 0.9 – – Max 0.8 – – 0.8 – Unit V V V V V Test Conditions VCC = 4.5 to 5.5V VCC = 4.5 to 5.5V VCC = 4.5 to 5.5V VCC = 4.5 to 5.5V VCC = 4.5 to 5.5V VCC = 4.5 to 5.5V IOL = 12 mA VCC = 4.5 to 5.5V IOH = -16 mA VCC = 4.5 to 5.5V IOL = 4 mA VCC = 4.5 to 5.5V IOH = -6 mA VCC = 5.5V, f = 25 MHz trigger ∆VT VIL TTL VIH TTL VOL400 pF VOH 400 pF VOL150 pF VOH 150 pF – 0.3 0.4 V 2.4 0.3 – V – 0.3 0.4 V 2.4 – 4.3 – – – – – – – 230 210 170 41 38 30 V Icc OP Operating Supply Current for core processor – – – mA VCC = 5.5V, f = 20 MHz VCC = 5.5V, f = 10 MHz VCC = 5.5V, f = 25MHz IccPD Power Down Supply Current for core processor – – mA VCC = 5.5V, f = 20 MHz VCC = 5.5V, f = 10 MHz 14 TSC695F 4118J–AERO–08/04 TSC695F Capacitance Ratings Parameter CIN COUT CIO Description Input Capacitance Output Capacitance Input/Output Capacitance Max 7 pF 8 pF 8 pF AC Characteristics Table 7. AC Characteristics (SYSCLK Freq. = 25 MHz − 5V ±10%) Cload = 50 pF, Vref = 2.5V Parameter t1 t2 t3 t4 t5 t6 t7 Min (ns) 20 40 9.75 – – – – Max (ns) – – – 6.5 12.5 15 23.5 Comment CLK2 period SYSCLK period CLK2 high and low pulse width RA(31:0) RAPAR RSIZE RLDSTO output delay MEMCS*(9:0) ROMCS* EXMCS* output delay DDIR DDIR* output delay MEMWR* IOWR*output delay formula: 13.5 ns + 1/4 t2 OE* HL output delay formula: 10.5 ns + 1/4 t2 Data setup time during load Data setup time during load NOPAR = 0 rpa = rec = either 1 or 0 Data hold time during load Data output delay Data output valid to HZ – guaranteed by design CB output delay ALE* output delay BUFFEN* HL output delay formula: 11 ns + 1/4 t2 MHOLD* output delay – guaranteed by design MDS* DRDY* output delay MEXC* output delay RASI(3:0) RSIZE(1:0) RASPAR setup time RASI(3:0) RSIZE(1:0) RASPAR hold time BOOT PROM address output delay Reference Edge – – – SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK- or SYSCLK+ t8 t9_1 t9 t9_2 t10 t11 t12 t13 t14 t15 t16 t17 t20 t21 t22 t23 – 11.5 9 5 – 8 – – – – – – 10 3 – 20.5 – – – 28 – 19 13 21 15 15 15 – – 13 SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLKSYSCLK+ SYSCLK+ SYSCLK- SYSCLK+ SYSCLK+ SYSCLK+ SYSCLKSYSCLK+ SYSCLK+ SYSCLK+ 15 4118J–AERO–08/04 Table 7. AC Characteristics (SYSCLK Freq. = 25 MHz − 5V ±10%) Cload = 50 pF, Vref = 2.5V (Continued) Parameter t24 t25 t27 Min (ns) 12 0 – Max (ns) – – 15 Comment BUSRDY* setup time BUSRDY* hold time IOSEL output delay DMAAS setup time formula of max: 1/2 t2 DMAAS hold time formula of max: 1/2 t2 DMAREQ* setup time DMAGNT* output delay RA(31:0) RAPAR CPAR setup time RA(31:0) RAPAR CPAR hold time TCK period TMS setup time TMS hold time TDI setup time TDI hold time TDO output delay INULL output delay RESET* CPUHALT* output delay SYSERR* SYSAV output delay IUERR* output delay EXTINT(4:0) setup time EXTINT(4:0) hold time EXTINTACK output delay OE* LH output delay (no DMA mode) BUFFEN* LH output delay INST output delay Reference Edge SYSCLK+ SYSCLK+ SYSCLK+ HL SYSCLK- LH t28 12 20 SYSCLK+ t29 t30 t31 t32 t33 t36 t37 t38 t39 t40 t41 t46 t48 t49 t50 t52 t53 t54 t56 t57 t60 t61 t80 t81 0 12 – 10 3 100 10 4 10 10 – – – – – 12 0 – – – – 20 12 0 20 – 15 – – – – – – – 20 22 22 20 20 – – 15 8.5 9 22 – SYSCLKSYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ TCK+ TCK+ TCK+ TCK+ TCKSYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLKSYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ Data output delay to low-Z – guaranteed by design formula: 10 ns + 1/4 t2 SYSCLK+ BUSERR* setup time SYSCLK+ 64 BUSERR* hold time formula: 24 ns + t2 SYSCLK+ 16 TSC695F 4118J–AERO–08/04 Figure 3. 150 pF Buffer Response (Data from simulation) 17 TSC695F 4118J–AERO–08/04 Figure 4. 400 pF Buffer Response (Data from simulation) 18 TSC695F 4118J–AERO–08/04 TSC695F Figure 5. OE*/400 pF Buffer Response (Data from simulation) 19 4118J–AERO–08/04 Timing Diagrams Figure 6. RAM Fetch, RAM Load and RAM Store Sequence - n Waitstates for Read, m Waitstates for Write 20 2 (RAM load) t1 t3 t3 3 (RAM fetch) 4 (RAM store) 5 (RAM fetch) n ws t2 n ws m ws n ws t4_1 LA1 FA2 SA1 FA3 1 (RAM fetch) CLK2 n ws SYSCLK t4_1 t4_1 t4_1 TSC695F t14 t5 t5 t5 t5 t6 t6 t7 t7 t8 t56 t56 t8 t10 t9 LD1 FD2 previous stored data RA [31:0] FA1 t14 ALE MEMCS* [0] M EMCS* [1] ROMCS* DDIR MEMWR* BUFFEN* OE* t11 t61 SD1 t12 FD3 D [31:0] t10 t9 LP1 FP2 FD1 t11 t61 SP1 previous stored parity t12 FP3 DPAR t10 t9 LC1 FP1 t61 FC2 previous stored checkbyte t13 SC1 t12 FC3 CB [6:0] t60 FC1 t60 t60 t60 INST t16 t16 MHOLD* t17 t17 t17 t17 t17 t17 t17 4118J–AERO–08/04 MDS* 1 (RAM fetch) t2 4118J–AERO–08/04 2 (RAM atomic load store) 3 (RAM fetch) SYSCLK t4_1 ALSA FA5 t4_1 RA [31:0] FA1 ALE* t5 t5 MEMCS* [0] t5 t5 MEMCS* [1] t6 t6 t6 t6 DDIR t7 t7 MEMWR* BUFFEN* t8 t56 t8 t56 t8 OE* t10 t9 byte from RAM word from RAM t10 t61 t9 t11 word to RAM t12 FD5 Figure 7. RAM “Atomic-load-store” byte Sequence - 0 Waitstate D [31:0] t10 t9 t9 FD1 t10 t61 t11 parity to RAM t13 checkbyte from RAM checkbyte to RAM t60 t12 FC5 t12 FP5 DPAR FP1 parity from RAM t10 t9 checkbyte from RAM t60 parity from RAM t10 t61 t9 CB [6:0] FC1 INST t16 held to update the full word t16 MHOLD* MDS* t46 t46 INULL t4_1 t4_2 t4_1 RLDSTO t4_2 TSC695F LOCK 21 Figure 8. RAM Load-double and RAM Store-double Sequence - 0 Waitstate 22 2 (RAM double load) t2 3 (RAM fetch) 4 (RAM double store) 5 (RAM fetch) t4_1 LA1 LA2 FA2 SA1 SA2 FA3 1 (RAM fetch) SYSCLK t4_1 t4_1 t4_1 t4_1 t4_1 RA [31:0] FA1 TSC695F t5 t5 t5 t5 t5 t5 t5 t5 t6 t6 t7 t7 t7 t7 t56 t8 t56 t8 t9 t61 FD2 ALE* MEMCS* [0] MEMCS* [1] DDIR MEMWR* BUFFEN* t8 OE* t10 t11 SD1 LD1 LD2 t11 SD2 t12 FD3 D [31:0] t9 t61 FP2 FD1 t10 t11 LP1 LP2 t11 SP1 SP2 t12 FP3 DPAR t9 t61 FC2 LC1 LC2 FP1 t10 t13 SC1 t13 SC2 t12 FC3 CB [6:0] FC1 t60 t60 INST t16 t16 MHOLD* MDS* t46 t46 INULL t4_2 t4_2 4118J–AERO–08/04 LOCK 1 (RAM fetch) load t2 internal error correction 4118J–AERO–08/04 2 (RAM load correctable data) 3 (RAM fetch) 4 (RAM fetch) SYSCLK t14 t14 ALE* t4_1 t4_1 t4_1 RA[31-0] LA1 t5 t5 FA2 FA1 FA3 MEMCS*[0] t5 t5 MEMCS*[1] DDIR MEMWR* IOWR* t8 t56 t56 t8 Figure 9. RAM Load with Correctable Error - 0 Waitstate OE* BUFFEN* t10 FD1 FC1 FP1 t16 LP1 1-bit error on 40-bit data FP2 t16 LC1 FC2 FD2 t9 t9 D[31-0] t10 LD1 FD2 FD3 data correction made inside FC2 FP2 FC3 FP3 CB[6-0] DPAR MHOLD* MEXC* t17 t17 MDS* t60 t60 INST TSC695F INULL 23 Figure 10. RAM Load with Uncorrectable Error - 0 Waitstate 24 2 (RAM load) load t2 internal error detection exception trap 3 (RAM fetch) 4 (null cycle) 5 (RAM fetch) 6 (RAM fetch) t14 t14 t4_1 t4_1 t4_1 t4_1 1 (RAM fetch) SYSCLK TSC695F LD1 t5 t5 FA2 FA3 TA1 TA2 t5 t5 t8 t56 t8 t56 t10 t9 LD1 LC1 LP1 2-bit error on 40-bit data t16 FP2 FP2 t16 FC2 FC2 FD2 FD2 t9 FD2 FC2 FP2 FD3 FC3 FP3 TD1 TC1 TP1 TD2 TC2 TP2 t10 t20 t20 t17 t17 t60 t60 t60 t60 t46 t46 ALE* RA[31-0] FA1 MEMCS*[0] MEMCS*[1] DDIR MEMWR* IOWR* OE* BUFFEN* D[31-0] FD1 CB[6-0] FC1 DPAR FP1 MHOLD* MEXC* MDS* INST 4118J–AERO–08/04 INULL 1 (RAM fetch) internal error fetch trap 4118J–AERO–08/04 2 (RAM load) 3 (RAM fetch) 4 (null cycle) 5 (RAM fetch) 6 (RAM fetch) t2 SYSCLK ALE* t4_1 t4_1 RA[31-0] FA2 FA3 TA1 t5 t5 FA1 unimplemented address LA1 TA2 MEMCS*[0] MEMCS*[1] DDIR MEMWR* IOWR* BUFFEN* t56 t8 t8 t56 Figure 11. RAM Load with Unimplemented Area Access - 0 Waitstate OE* t9 no data t16 t16 t9 D[31-0] t10 FD1 t10 FD2 FD3 TD1 TD2 MHOLD* t20 t20 MEXC* t17 t17 MDS* t60 t60 t60 t60 INST t46 t46 TSC695F INULL 25 Figure 12. I/O Store Sequence with BUSRDY* and n Waitstates (Timing for 0 Waitstate = Timing for 1 Waitstates) 26 2 (i/o store) (n-1) ws t2 rdy waiting end of cycle 3 (RAM fetch) t4_1 SA1 t4_1 FA2 1 (RAM fetch) start of cycle SYSCLK TSC695F t5 t5 t27 t27 t25 t24 t24 t6 t6 t7 t7 t15 t57 t56 t8 t10 t61 t11 SD1 previous stored data ALE* t4_1 RA[31-0] FA1 MEMCS*[0] IOSEL*[0] BUSRDY* DDIR MEMWR* IOWR* BUFFEN* OE* t9 t12 FD2 D[31-0] t60 FD1 t60 INST t16 t16 MHOLD* 4118J–AERO–08/04 MDS* 1 (RAM fetch) (n-1) ws t2 rdy waiting end of cycle 4118J–AERO–08/04 start of cycle 2 (i/o load) 3 (RAM fetch) SYSCLK t14 t14 ALE* t4_1 LA1 t4_1 FA2 RA[31-0] t5 FA1 t5 MEMCS*[0] t27 t27 IOSEL*[0] t25 t24 t24 BUSRDY* DDIR MEMWR* IOWR* t15 t57 BUFFEN* t8 t56 t8 t56 OE* t10 data driven by external buffers (c.f BUFFEN*) t9 LD1 t9 t10 FD2 D[31-0] t60 t60 FD1 Figure 13. I/O Load Sequence with BUSRDY* and n Waitstates (Timing for 0 ws = Timing for 1 ws) INST t16 t16 MHOLD* t17 t17 TSC695F MDS* 27 Figure 14. EXCHANGE RAM Store with BUSDRY* and n Waitstates 28 2 (xchgRAM store) start of cycle t2 rdy waiting in between n ws end of cycle 3 (RAM fetch) t4_1 SA1 t5 t5 t4_1 FA2 t5 t5 t6 t6 t7 t7 t7 t7 t15 t57 t56 t8 t25 t24 t24 t24 t25 t61 previous stored data t60 t60 t11 SD1 t12 FD2 t16 t16 1 (RAM fetch) SYSCLK TSC695F ALE* RA[31-0] FA1 MEMCS*[0] EXMCS* DDIR MEMWR* IOWR* BUFFEN* OE* BUSRDY* D[31-0] FD1 INST MHOLD* MDS* 4118J–AERO–08/04 1 (RAM fetch) start of cycle t2 rdy waiting n ws end of cycle 4118J–AERO–08/04 2 (xchgRAM load) 3 (RAM fetch) SYSCLK t14 t14 ALE* t4_1 t4_1 RA[31-0] LA1 t5 t5 FA1 FA2 MEMCS*[0] t5 t5 EXMCS* DDIR MEMWR* IOWR* t15 t57 Figure 15. EXCHANGE RAM Load with BUSDRY* and n Waitstates BUFFEN* t56 t24 t24 t25 t8 OE* t24 t25 BUSRDY* t9 LD1 data driven by external buffers (c.f BUFFEN*) t60 t60 t10 FD2 D[31-0] FD1 INST t16 t16 MHOLD* t17 t17 TSC695F MDS* 29 Figure 16. 8-bit BOOT PROM Fetch (or Load Word) - n Waitstates 30 2 (8-bit ROM fetch or load word) byte 0 (n-1) ws t2 end of cycle byte 1 (n-1) ws byte 2 (n-1) ws byte 3 (n-1) ws 3 (ROM fetch) t14 t4 1 (ROM fetch) start of cycle TSC695F t4_1 10 SYSCLK ALE* t4_1 RSIZE[0,1] t4_1 FA2 t23 0 t5 1 2 3 t23 t23 (address mod. 4) t23 0 t4_1 FA2 RA[31-0] FA1 BA[0,1] t5 t5 ROMCS* MEMCS*[0] DDIR MEMWR* t57 t15 t15 BUFFEN* t56 data driven by external buffers (c.f BUFFEN*) t10 t9 FD2-0 t9 FD2-1 t10 t9 FD2-2 t10 t8 t8 OE* D[31-8] D[7-0] t10 t9 FD2-3 t60 t60 (1 = fetch, t16 0 = load word) t16 INST t16 MHOLD* t17 t17 t17 4118J–AERO–08/04 MDS* 1 (RAM fetch) (n-1) ws t2 start of cycle (n-1) ws 2 (8-bit ROM write) 3 (RAM fetch) 4 (8-bit ROM write) 5 (RAM fetch) 4118J–AERO–08/04 start of cycle SYSCLK ALE* t4_1 SA1 addr.=mod. 4 t23 00 01 addr.=mod. 4 +1 FA2 SA2 t4_1 t4_1 RA[31-0] FA1 t4_1 FA3 t23 00 BA[0,1] t4_1 00 t5 t5 10 00 t4_1 t4_1 t4_1 10 t5 RSIZE[0,1] 10 t5 MEMCS*[0] t5 t5 t5 t5 Figure 17. 8-bit BOOT PROM 2x Store byte - n Waitstate ROMCS* t6 t6 t6 t6 DDIR t7 t7 t7 t7 MEMWR* IOWR* t57 t15 t57 t15 BUFFEN* t8 t56 t56 OE* t61 t11 byte D[7:0] SD1 t12 t9 FD2 t60 t60 t61 t11 t12 byte D[7:0] SD2 t9 D[31-0] FD1 t60 INST t16 t16 t16 t16 MHOLD* TSC695F MDS* 31 Figure 18. DMA RAM load with or without Correctable Error and DMA RAM Store - 0 Waitstates 32 3 (DMA session) (0 cycle min) 1st DMA load (0 ws) (0 cycle min) nth DMA store (0 ws) lead-out t2 t14 t14 t14 t32 D SAn (held to the end of RAM access) t22 t33 t32 t33 t14 4 (RAM fetch) 5 (RAM fetch) cont' 1 (RAM fetch) 2 (RAM fetch) (null cycle)lead-in SYSCLK ALE* TSC695F t4_1 t4_1 t21 D SSn t22 t30 early time for DMAREQ* desassertion t31 t28 t31 t31 t5 t17 t8 t56 t7 corrected data if needed t6 t7 t6 t17 t5 t17 t17 t8 t56 t32 t33 t32 t33 t32 t33 t32 t33 t29 t28 t29 t31 t31 t5 t5 t31 t21 10 (only word access) RA[31-0] FA1 D LA1 (held to the end of RAM access) t22 t21 D LS1 t4_1 FA2 t4_1 FS2 t4_1 FZ2 t4_1 FA2 FA3 FS3 FZ3 RASI[3-0] FS1 t4_1 FS2 t4_1 t21 10 (only word access) t22 RSIZE[1-0] FZ1 t4_1 FZ2 t30 DMAREQ* DMAGNT* DMAAS RD WRT (pull-up on WE*) t5 MEMCS*[9-0] DRDY* OE* MEMWR* DDIR D[31-0] t10 t9 FD1 DPAR t10 t9 FP1 CB[7-0] t10 t9 FC1 t16 t10 t10 t11 t12 t9 t9 t10 t9 D LD1 D LD1 FD2 D SDn (from RAM) (from TSC695F) (held to the end of RAM access) t10 t10 t11 t12 t13 t13 t9 t9 D LP1 D LP1 FP2 DSPn (from RAM) Parity generated by TSC695F if dpe =1, (from TSC695F) else, same timing as D[31-0] t10 t10 corrected parity if needed t13 t13 t9 t9 D LC1 FC2 D SCn (from RAM) t16 4118J–AERO–08/04 MHOLD* 4118J–AERO–08/04 Sampled Latched Taken Figure 19. Edge Triggered Interrupt Timing Prioritized SYSCLK FA0 FA1 FA2 FA3 FA4 TTA0 TTA1 TSA0 TSA1 TSA2 RA[31:0] FA(-1) ALE* FD0 FD1 FD2 FD3 FD4 TD0 TD1 TSD0 TSD1 D[31:0] FD(-1) INULL t53 t52 EXTINT[i] t54 t54 EXTINTACK TSC695F 33 Figure 20. Halt Timing 34 TSC695F FAn 09H 10 t14 t14 10 10 09H 09H FAn+1 FAn+1 FAn+2 09H 10 t16 t16 t49 t49 t48 t48 FDn FDn+1 FDn+2 SYSCLK RA[31:0] FAn-1 RASI[3:0] 09H RSIZE[1:0] 10 ALE* SYSHALT* MHOLD* SYSAV CPUHALT* D[31:0] FDn-1 4118J–AERO–08/04 4118J–AERO–08/04 SYSCLK FAn-1 09H 10 t14 10 10 09H 09H FAn FAn+1 RA[31:0] RASI[3:0] Figure 21. External Error with Halt Timing RSIZE[1:0] ALE* t50 t50 IUERR* t49 SYSERR* t16 MHOLD* t49 SYSAV t48 CPUHALT* FDn-1 FDn D[31:0] TSC695F 35 Figure 22. Reset Timing 36 FA n+1 0H 4H 8H t14 t14 t46 t47 t48 t48 TSC695F SYSCLK SYSRESET* RA[31:0] FA n RASI[3:0] RSIZE[1:0] ALE* INULL RESET* 4118J–AERO–08/04 TSC695F Figure 23. External Error signaling with BUSERR* and BUSRDY* SYSCLK t24 B USRDY* t80 B USERR* t20 MEXC* t81 t80 37 4118J–AERO–08/04 Package Drawings 256-lead MQFP-F Package 38 TSC695F 4118J–AERO–08/04 TSC695F 256-lead MQFP-F Pin Assignments Table 8. Pin Assignments Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal GPIINT GPI[7] VCCO VSSO GPI[6] GPI[5] GPI[4] GPI[3] VCCO VSSO GPI[2] GPI[1] GPI[0] D[31] D[30] VCCO VSSO D[29] D[28] VCCI VSSI D[27] D[26] VCCO VSSO D[25] D[24] D[23] D[22] VCCO VSSO D[21] D[20] D[19] D[18] Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Signal D[0] RSIZE[1] RSIZE[0] RASI[3] VCCO VSSO RASI[2] RASI[1] RASI[0] RA[31] RA[30] VCCO VSSO RA[29] RA[28] RA[27] VCCO VSSO RA[26] RA[25] RA[24] VCCI VSSI VCCO VSSO RA[23] RA[22] RA[21] VCCO VSSO RA[20] RA[19] RA[18] VCCO VSSO Pin 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 Signal RA[0] VCCO VSSO RAPAR RASPAR DPAR VCCO VSSO SYSCLK TDO TRST TMS TDI TCK CLK2 DRDY DMAAS VCCO VSSO DMAGNT EXMCS VCCI VSSI DMAREQ BUSERR BUSRDY ROMWRT NOPAR SYSHALT CPUHALT VCCO VSSO SYSERR SYSAV EXTINT[4] Pin 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 Signal DXFER MEXC VCCO VSSO RESET SYSRESET BA[1] BA[0] CB[6] CB[5] VCCO VSSO CB[4] CB[3] CB[2] CB[1] VCCO VSSO CB[0] ALE VCCI VSSI PROM8 ROMCS MEMCS[9] VCCO VSSO MEMCS[8] MEMCS[7] MEMCS[6] MEMCS[5] MEMCS[4] MEMCS[3] VCCO VSSO 39 4118J–AERO–08/04 Table 8. Pin Assignments (Continued) Pin 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Signal VCCO VSSO D[17] D[16] VCCI VSSI D[15] D[14] VCCO VSSO D[13] D[12] D[11] D[10] VCCO VSSO D[9] D[8] D[7] D[6] VCCO VSSO D[5] D[4] D[3] D[2] VCCO VSSO D[1] Pin 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Signal RA[17] RA[16] RA[15] VCCO VSSO RA[14] VCCI VSSI RA[13] RA[12] VCCO VSSO RA[11] RA[10] RA[9] VCCO VSSO RA[8] RA[7] RA[6] VCCO VSSO RA[5] RA[4] RA[3] VCCO VSSO RA[2] RA[1] Pin 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 Signal EXTINT[3] EXTINT[2] EXTINT[1] EXTINT[0] VCCI VSSI EXTINTACK IUERR VCCO VSSO CPAR TXA RXA RXB TXB IOWR IOSEL[3] VCCO VSSO IOSEL[2] IOSEL[1] IOSEL[0] WRT WE VCCO VSSO RD RLDSTO LOCK Pin 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 Signal MEMCS[2] MEMCS[1] MEMCS[0] VCCI VSSI OE VCCO VSSO MEMWR BUFFEN DDIR VCCO VSSO DDIR MHOLD MDS WDCLK IWDE EWDINT TMODE[1] TMODE[0] DEBUG INULL DIA VCCO VSSO FLUSH INST RTC 40 TSC695F 4118J–AERO–08/04 TSC695F Ordering Information Table 9. Possible Order Entries Temperature Part-Number TSC695F-25MA-E TSC695F-25MA 5962-0054001QXC 5962-0054001VXC 5962R0054001VXC 951200301 TSC695F-25MB-E 5962-0054001Q9A 5962-0054001V9A Supply Voltage 5V 5V 5V 5V 5V 5V 5V 5V 5V Range 25°C -55° to +125°C -55° to +125°C -55° to +125°C -55° to +125°C -55° to +125°C 25°C -55° to +125°C -55° to +125°C Maximum Speed (MHz) 25 25 25 25 25 25 25 25 25 Packaging MQFP-F256 MQFP-F256 MQFP-F256 MQFP-F256 MQFP-F256 MQFP-F256 Die Die Die Quality Flow Engineering Samples Standard Mil. QML-Q QML-V QMLV-RHA ESCC B Engineering Samples QML-Q QML-V 41 4118J–AERO–08/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 e-mail literature@atmel.com Web Site http://www.atmel.com Disclaimer: A tmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. 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