AT17F040A-30QI

Features • Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) • 3.3V Output Capability • 5V Tolerant I/O Pins • Program Support using the Atmel ATDH2200E System or Industry Third Party • • • • • • • • • • • • Programmers In-System Programmable (ISP) via 2-wire Bus Simple Interface to SRAM FPGAs Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, Excalibur™, Stratix®, Cyclone™ and APEX™ Devices Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Low-power CMOS FLASH Process Available in 8-lead LAP, 20-lead PLCC and 32-lead TQFP Packages Emulation of Atmel’s AT24CXXX Serial EEPROMs Low-power Standby Mode Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System Reconfiguration Fast Serial Download Speeds up to 33 MHz Endurance: 5,000 Write Cycles Typical Green (Lead/Halide-free/ROHS compliant) Packages FPGA Configuration Flash Memory AT17F040A AT17F080A 1. Description The AT17FxxxA Series of In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17FxxxA Series device is packaged in the 8-lead LAP, 20-lead PLCC and 32-lead TQFP, see Table 1-1. The AT17FxxxA Series Configurator uses a simple serial-access procedure to configure one or more FPGA devices. The AT17FxxxA Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. Table 1-1. Package 8-lead LAP 20-lead PLCC 32-lead TQFP AT17FxxxA Series Packages AT17F040A Yes Yes Yes AT17F080A Yes Yes Yes 2823D–CNFG–2/08 2. Pin Configuration 8-lead LAP DATA DCLK RESET/OE nCS 1 2 3 4 8 7 6 5 VCC SER_EN (A2) nCASC GND 20-lead PLCC 3 2 1 20 19 32-lead TQFP NC DATA NC VCC NC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 NC DATA NC NC NC VCC NC NC nCS GND PAGESEL0 (A2) nCASC NC 9 10 11 12 13 DCLK NC NC PAGESEL1 RESET/OE 4 5 6 7 8 18 17 16 15 14 SER_EN NC PAGE_EN READY NC NC DCLK NC NC NC PAGESEL1 RESET/OE NC 1 2 3 4 5 6 7 8 NC SER_EN NC PAGE_EN READY NC NC NC 2 AT17F040A/080A 2823D–CNFG–2/08 NC nCS NC GND NC PAGESEL0 (A2) nCASC NC AT17F040A/080A 3. Block Diagram READY Power-on Reset Reset Clock/Oscillator Logic DCLK PAGE_EN PAGESEL0 PAGESEL1 Config. Page Select nCASC(A2) Serial Download Logic 2-wire Serial Programming DATA Flash Memory CE/WE/OE Data Address nCS Control Logic RESET/OE SER_EN 4. Device Description The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration device without requiring an external intelligent controller. The RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17FxxxA Series Configurator. If nCS is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of nCS. When the configurator has driven out all of its data and nCASC is driven Low, the device tristates the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. 3 2823D–CNFG–2/08 5. Pin Description Table 5-1. Pin Description AT17F040A/080A Name DATA DCLK PAGE_EN PAGESEL0 PAGESEL1 RESET/OE nCS GND nCASC A2 READY SER_EN VCC I/O I/O I I I I I I – O 20 PLCC 2 4 16 11 7 8 9 10 12 32 TQFP 31 2 21 14 6 7 10 12 15 20 23 27 I O I – 15 18 20 5.1 DATA(1) Three-state DATA output for FPGA configuration. Open-collector bi-directional pin for configuration programming. 5.2 DCLK(1) Three-state clock. Functions as an input when the Configurator is in programming mode (i.e. SER_EN is Low) and as an output during FPGA configuration. 5.3 PAGE_EN(2) Input used to enable page download mode. When PAGE_EN is high the configuration download address space is partitioned into 4 equal pages. This gives users the ability to easily store and retrieve multiple configuration bitstreams from a single configuration device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no effect. Notes: 1. This pin has an internal 20 kΩ pull-up resistor. 2. This pin has an internal 30 kΩ pull-down resistor. 4 AT17F040A/080A 2823D–CNFG–2/08 AT17F040A/080A 5.4 PAGESEL[1:0](2) Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial configuration download. The address space for each of the pages is shown in Table 5-2. When SER_EN is Low (ISP mode) these pins have no effect. Table 5-2. Address Space AT17F040A (4 Mbits) 00000 – 0FFFFh 10000 – 1FFFFh 20000 – 2FFFFh 30000 – 3FFFFh 00000 – 3FFFFh AT17F080A (8 Mbits) 00000 – 1FFFFh 20000 – 3FFFFh 40000 – 5FFFFh 60000 – 7FFFFh 00000 – 7FFFFh Paging Decodes PAGESEL = 00, PAGE_EN = 1 PAGESEL = 01, PAGE_EN = 1 PAGESEL = 10, PAGE_EN = 1 PAGESEL = 11, PAGE_EN = 1 PAGESEL = XX, PAGE_EN = 0 5.5 RESET/OE(1) Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with nCS Low) enables the data output driver. 5.6 nCS(1) Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the address counter and enables the data output driver. A High level on nCS disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low). 5.7 GND Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended. 5.8 nCASC Cascade Select Output (when SER_EN i s High). This output goes Low when the internal address counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value is the highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the 4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the address maximum value is the highest address in the device, see Table 5-2 on page 5. In a daisy chain of AT17FxxxA Series devices, the nCASC pin of one device must be connected to the nCS input of the next device in the chain. It will stay Low as long as nCS is Low and OE is High. It will then follow nCS until OE goes Low; thereafter, nCASC will stay High until the entire EEPROM is read again. 5.9 A2(1) Device selection input, (when SER_EN Low). The input is used to enable (or chip select) the device during programming (i.e., when SER_EN is Low). Refer to the AT17FxxxA Programming Specification available on the Atmel web site for additional details. Notes: 1. This pin has an internal 20 k pull-up resistor. 2. This pin has an internal 30 kΩ pull-down resistor. 5 2823D–CNFG–2/08 5.10 READY Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. (recommended 4.7 kΩ pull-up on this pin if used). 5.11 SER_EN(1) The serial enable input must remain High during FPGA configuration operations. Bringing SER_EN L ow enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. 5.12 VCC +3.3V (±10%). Notes: 1. This pin has an internal 20 kΩ pull-up resistor. 6 AT17F040A/080A 2823D–CNFG–2/08 AT17F040A/080A 6. FPGA Master Serial Mode Summary The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17FxxxA Serial Configuration PROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Altera applications. 7. Control of Configuration Most connections between the FPGA device and the AT17FxxxA Serial Configurator PROM are simple and self-explanatory. • The DATA output of the AT17FxxxA Series Configurator drives DIN of the FPGA devices. • The DCLK output of the AT17FxxxA device drives the DCLK input data of the FPGA. • The nCASC output of a AT17FxxxA Series Configurator drives the nCS input of the next Configurator in a cascade chain of configurator devices. • SER_EN must be at logic High level (internal pull-up resistor provided) except during ISP. • The READY pin is available as an open-collector indicator of the device’s reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. • PAGE_EN must REMAIN Low if download paging is not desired. If paging is desired, PAGE_EN must be High and the PAGESEL pins must be set to High or Low such that the desired page is selected, see Table 5-2 on page 5. 8. Cascading Serial Configuration Devices For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator asserts its nCASC output Low and disables its DATA line driver. The second configurator recognizes the Low level on its nCS input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level. 9. Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The AT17FxxxA parts are read/write at 3.3V nominal. Refer to the AT17FxxxA Programming Specification available on the Atmel web site (www.atmel.com) for more programming details. AT17FxxxA devices are supported by the Atmel ATDH2200 programming system along with many third party programmers. 7 2823D–CNFG–2/08 10. Standby Mode The AT17FxxxA Series Configurators enter a low-power standby mode whenever SER_EN is High and nCS is asserted High. In this mode, the AT17FxxxA Configurator typically consumes less than 1 mA of current at 3.3V. The output remains in a high-impedance state regardless of the state of the OE input. 11. Absolute Maximum Ratings* Operating Temperature................................... -40° C to +85 ° C Storage Temperature .................................... -65 ° C to +150° C Voltage on Any Pin with Respect to Ground ..............................-0.5V to VCC +0.5V Supply Voltage (VCC) .........................................-0.5V to +4.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.)............ 260° C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. 12. Operating Conditions AT17FxxxA Series Configurator Symbol Description Commercial VCC Industrial Supply voltage relative to GND -0° C to +70° C Supply voltage relative to GND -40° C to +85° C Min 2.97 2.97 Max 3.63 3.63 Units V V 13. DC Characteristics AT17F040A Symbol VIH VIL VOH VOL VOH VOL ICCA IL ICCS Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode at Freq. Max. Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode Industrial 3 3 mA -10 2.4 Industrial 0.4 50 10 3 -10 0.4 50 10 3 V mA µA mA Commercial 0.4 2.4 0.4 V V Min 2.0 0 2.4 Max VCC 0.8 AT17F080A Min 2.0 0 2.4 Max VCC 0.8 Units V V V 8 AT17F040A/080A 2823D–CNFG–2/08 AT17F040A/080A 14. AC Characteristics nCS TSCE RESET/OE TLC CLK TOE TCE DATA TOH TCAC TOH TDF THC THOE TSCE THCE 15. AC Characteristics when Cascading RESET/OE nCS CLK TCDF DATA LAST BIT FIRST BIT TOCK nCASC TOCE TOOE TOCE 9 2823D–CNFG–2/08 16. AC Characteristics AT17F040A/080A Symbol TOE(2) TCE(2) TCAC(2) Description Commercial OE to Data Delay Industrial nCS to Data Delay (1) Min Typ Max 50 55 55 60 30 30 Units ns ns ns ns ns ns ns ns Commercial Industrial(1) Commercial DCLK to Data Delay Industrial Data Hold from nCS, OE, or DCLK Industrial nCS or OE to Data Float Delay Industrial DCLK Low Time Industrial DCLK High Time Industrial nCS Setup Time to DCLK (to guarantee proper counting) nCS Hold Time from DCLK (to guarantee proper counting) RESET/OE Low Time (guarantees counter is reset) Maximum Input Clock Frequency SEREN = 0 Write Cycle Time(4) (1) Commercial TOH TDF(3) (1) 0 0 15 15 15 15 15 15 20 25 0 0 20 20 10 10 12 12 13 13 Commercial (1) ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz µs µs s s Commercial TLC (1) Commercial THC (1) Commercial Industrial(1) Commercial Industrial (1) TSCE THCE Commercial Industrial(1) Commercial Industrial (1) THOE FMAX Commercial Industrial (1) TWR TEC Notes: Erase Cycle Time(4) Commercial Industrial (1) 1. Preliminary specifications for military operating range only. 2. AC test lead = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. 4. See the AT17FxxxA Programming Specfication for procedural information. 10 AT17F040A/080A 2823D–CNFG–2/08 AT17F040A/080A 16.1 AC Characteristics When Cascading AT17F040A Symbol TCDF(3) TOCK(2) TOCE(2) TOOE(2) Notes: Description Commercial DCLK to Data Float Delay Industrial Commercial DCLK to nCASC Delay Industrial Commercial nCS to nCASC Delay Industrial Commercial RESET/OE to nCASC Delay Industrial 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. 25 35 ns 40 35 40 35 ns ns 55 35 55 35 ns ns 50 50 50 50 ns ns Min Max 50 AT17F080A Min Max 50 Units ns 17. Thermal Resistance Coefficients Package Type 20J Plastic Leaded Chip Carrier (PLCC) θJC [° C/W] θJA [° C/W] (1) AT17F040A AT17F080A – – 32A Thin Plastic Quad Flat Package (TQFP) θJC [° C/W] θJA [° C/W](1) 17 62 17 62 Note: 1. Airflow = 0 ft/min. 11 2823D–CNFG–2/08 18. Ordering Information Memory Size Ordering Code AT17F040A-30QC 4-Mbit AT17F040A-30QI AT17F080A-30QC 8-Mbit AT17F080A-30QI Notes: 32A - 32 TQFP 32A - 32 TQFP 32A - 32 TQFP Package(1) 32A - 32 TQFP Operation Range Commercial (0° C to 70° C) Industrial (-40° C to 85° C) Commercial (0° C to 70° C) Industrial (-40° C to 85° C) 1. For the -30JC and -30JI package, customers may migrate to the AT17FxxxA-30JU. 19. Green Package Options (Pb/Halide-free/RoHS Compliant) Memory Size 4-Mbit 8-Mbit Ordering Code AT17F040A-30CU AT17F040A-30JU AT17F080A-30CU AT17F080A-30JU Package 8CN4 -8 LAP 20J - 20 PLCC 8CN4 -8 LAP 20J - 20 PLCC Operation Range Industrial (-40° C to 85° C Package Type 8CN4 20J 32A 8-lead, 6 mm x 6 mm x 1.04 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOIC Packages 20-lead, Plastic J-leaded Chip Carrier (PLCC) 32-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) 12 AT17F040A/080A 2823D–CNFG–2/08 AT17F040A/080A 20. Packaging Information 20.1 8CN4 – LAP Marked Pin1 Indentifier E D A A1 Top View L1 8 1 Side View Pin1 Corner 0.10 mm TYP e 7 2 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A 6 3 MIN 0.94 0.30 0.45 5.89 5.89 NOM 1.04 0.34 0.50 5.99 5.99 1.27 BSC 1.10 REF MAX 1.14 0.38 0.55 6.09 6.09 NOTE A1 b 5 4 b D E e e1 L L1 1 e1 L Bottom View Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm 0.95 1.25 1.00 1.30 1.05 1.35 1 1 2/15/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27mm, Leadless Array Package (LAP) GPC DMH DRAWING NO. 8CN4 REV. D 13 2823D–CNFG–2/08 20.2 20J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) e E1 B E B1 D2/E2 D1 D A A2 A1 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 9.779 8.890 9.779 8.890 7.366 0.660 0.330 NOM – – – – – – – – – – 1.270 TYP MAX 4.572 3.048 – 10.033 9.042 10.033 9.042 8.382 0.813 0.533 Note 2 Note 2 NOTE 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 20J REV. B R 14 AT17F040A/080A 2823D–CNFG–2/08 AT17F040A/080A 20.3 32A – TQFP PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN – 0.05 0.95 8.75 6.90 8.75 6.90 0.30 0.09 0.45 NOM – – 1.00 9.00 7.00 9.00 7.00 – – – 0.80 TYP MAX 1.20 0.15 1.05 9.25 7.10 9.25 7.10 0.45 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 32A REV. B R 15 2823D–CNFG–2/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support configurator@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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