AT17LV010-10DP

Features • EE Programmable 1,048,576 x 1-bit Serial Memory Designed to Store Configuration • • • • • • • • • • • • Programs for Field Programmable Gate Arrays (FPGAs) Very Low-power CMOS EEPROM Process In-System Programmable (ISP) via Two-Wire Bus Simple Interface to SRAM FPGAs Compatible with AT40K Devices Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Programmable Reset Polarity Low-power Standby Mode High-reliability – Endurance: 5,104 Read Cycles – Data Retention: 10 Years No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2 Tested up to a Total Dose of (according to MIL STD 883 Method 1019) – 20 krads (Si) Read-only mode when Biased – 60 krads (Si) Read-only mode when Unbiased Operating Range: 3.0V to 3.6V, -55°C to +125°C Available in 400 mils Wide 28 Pins DIL Flat Pack Space FPGA Configuration EEPROM AT17LV01010DP Description The AT17LV010-10DP is a FPGA Configuration Serial EEPROM provides an easy-touse, cost-effective configuration memory for Field Programmable Gate Arrays. It is packaged in the 28-pin 400 mils wide FP package. Configurator uses a simple serialaccess procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. The device also supports a write-protection mechanism within its programming mode. Rev. Rev. 4265C–AERO–05/05 1 Pin Configuration Figure 1. 28-pin Flat Pack RESET/OE NC WP2 CE GND NC NC NC NC NC CE0(A2) NC NC READY 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC* NC WP1 CLK DATA NC NC NC NC VCC NC SER_EN NC NC Note: * indicates this pin must not be used. 2 AT17LV010-10DP 4265C–AERO–05/05 AT17LV010-10DP Block Diagram Device Description The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller. The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17LV010-10DP configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tristated. When OE is subsequently driven Low, the counter and the DATA output pin are enabled. When RESET/OE is driven High again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document will describe RESET/OE. 3 4265C–AERO–05/05 Pin Description DATA CLK WP1 Tri-state DATA output for configuration. Open-collector bi-directional pin for programming. Clock input. Used to increment the internal address and bit counter for reading and programming. WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. For most applications, RESET should be programmed active Low. This document describes the pin as RESET/OE. WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN Low). Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended. Chip Enable Output (active Low). This output goes Low when the address counter has reached its maximum value. In a daisy chain of AT17LV010-10DP devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is read again. Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor. Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. It is recommended to use a 4.7 kΩ pull-up resistor when this pin is used. Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. 3.3V (±0.3V). RESET/OE WP2 CE GND CEO A2 READY SER_EN VCC 4 AT17LV010-10DP 4265C–AERO–05/05 AT17LV010-10DP FPGA Master Serial Mode Summary The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17LV Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40KEL applications. Control of Configuration Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and self-explanatory. • • • • • The DATA output of the AT17LV010-10DP configurator drives DIN of the FPGA devices. The master FPGA CCLK output drives the CLK input of the AT17LV010-10DP configurator. The CEO output of any AT17LV010-10DP configurator drives the CE input of the next configurator in a cascaded chain of EEPROMs. SER_EN must be connected to VCC (except during ISP). The READY pin is available as an open-collector indicator of the device’s reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. Cascading Serial Configuration EEPROMs For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level. AT17LV010-10DP Reset Polarity Programming Mode The AT17LV010-10DP configurator allows the user to program the reset polarity as either RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms. The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the Two-Wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. For more information see application note: http://www.atmel.com/dyn/resources/prod_documents/doc0437.pdf Standby Mode The AT17LV010-10DP configurator enter a low-power standby mode whenever CE is asserted High. In this mode, the AT17LV010-10DP configurator consumes less than 100 µA of current at 3.3V. The output remains in a high-impedance state regardless of the state of the OE input. 5 4265C–AERO–05/05 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125 °C Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground .............................. -0.1V to VDD +0.5V Supply Voltage (VCC) .........................................-0.5V to +7.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Operating Conditions 3.3V Symbol VDD Description -55 to +125°C Min 3.0 Max 3.6 Units V DC Characteristics VDD = 3.3V ± 0.3V Symbol Description AT17LV010-10DP Min VIH VIL VOH VOL ICCOP IL ICCS High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode Input or Output Leakage Current (VIN = VDD or GND) Supply Current, Standby Mode -10 2.0 0 2.4 0.4 5 10 150 Max VDD 0.8 Units V V V V mA µA µA 6 AT17LV010-10DP 4265C–AERO–05/05 AT17LV010-10DP AC Characteristics CE TSCE RESET/OE TLC CLK TOE TCE DATA TOH TCAC TOH TDF THC THOE TSCE THCE AC Characteristics when Cascading RESET/OE CE CLK TCDF DATA LAST BIT FIRST BIT TOCK CEO TOCE TOOE TOCE 7 4265C–AERO–05/05 AC Characteristics VCC = 3.3V ± 0.3V Military Symbol TOE(1) TCE(1) TCAC(1) TOH TDF(2) TLC THC TSCE THCE THOE FMAX Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold from CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) Maximum Clock Frequency 25 25 35 0 25 10 0 50 Min Max 55 60 60 Units ns ns ns ns ns ns ns ns ns ns MHz Notes: 1. AC test lead = 60 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. AC Characteristics when Cascading VCC = 3.3V ± 0.3V Military Symbol TCDF(2) TOCK TOCE (1) (1) Description CLK to Data Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay Maximum Clock Frequency Min Max 50 55 40 40 10 Units ns ns ns ns MHz TOOE(1) FMAX Notes: 1. AC test lead = 60 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. 8 AT17LV010-10DP 4265C–AERO–05/05 AT17LV010-10DP Ordering Information Memory Size 1 Mbit 1 Mbit 1 Mbit Ordering Code AT17LV010-10DP-E AT17LV010-10DP-MQ AT17LV010-10DP-SV Package 28-pin Flat Pack 28-pin Flat Pack 28-pin Flat Pack Operation Range Engineering Samples Military Level B Space Level B 9 4265C–AERO–05/05 Packaging Information DP (FP28.4) 10 AT17LV010-10DP 4265C–AERO–05/05 A tmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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