AT24C04BN-SH-T

Features • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 5.5V) Internally Organized 512 x 8 (4K), or 1024 x 8 (8K) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility Write Protect Pin for Hardware Data Protection 16-byte Page (4K, 8K) Write Modes Partial Page Writes Allowed Self-timed Write Cycle (5 ms max) High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years • 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin Mini-MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages • Lead-free/Halogen-free • Die Sales: Wafer Form, Tape and Reel and Bumped Wafers • • • • • • • • • • Two-wire Serial EEPROM 4K (512 x 8) 8K (1024 x 8) Description The AT24C04B/08B provides 4096/8192 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 512/1024 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C04B/08B is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin MiniMAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. In addition, the AT24C04B/08B is available in 1.8V (1.8V to 5.5V) version. Table 0-1. Pin Name A0 - A2 SDA SCL WP NC GND VCC AT24C04B AT24C08B Pin Configuration Function Address Inputs Serial Data Serial Clock Input Write Protect No Connect Ground Power Supply 8-lead Ultra-Thin Mini-MAP (MLP 2x3) VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND 8-ball dBGA2 VCC WP SCL SDA 8 7 6 5 1 A0 2 A1 3 A2 4 GND Bottom View 8-lead TSSOP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 A2 GND Bottom View 8-lead SOIC 1 2 3 4 8 7 6 5 VCC WP SCL SDA Note: For use of 5-lead SOT23 4K: The softw a re A2 a nd A1 b its in the device a ddress word must b e set to zero to properly communicate. 8K: The software A2 bit in the device address word must be set to zero to properly communicate. 5-lead SOT23 SCL GND SDA 1 2 3 4 VCC 5 WP A0 A1 A2 GND 8-lead PDIP 1 2 3 4 8 7 6 5 VCC WP SCL SDA 5226D–SEEPR–7/08 Absolute Maximum Ratings Operating Temperature..................................–55°C to +125°C Storage Temperature .....................................–65°C to +150°C Voltage on Any Pin with Respect to Ground .................................... –1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 0-1. Block Diagram VCC GND WP SCL SDA START STOP LOGIC LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 R/W COMP SERIAL CONTROL LOGIC EN H.V. PUMP/TIMING DATA RECOVERY INC X DEC EEPROM LOAD DATA WORD ADDR/COUNTER Y DEC SERIAL MUX DIN DOUT DOUT/ACK LOGIC 2 AT24C04B/08B 5226D–SEEPR–7/08 AT24C04B/08B 1. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The AT24C04B uses the A2 and A1 inputs for hard wire addressing and a toal of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground (device addressing is discussed in detail under the Device Addressing section). The AT24C08B only uses the A2 input for hardware addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to ground (device addressing is discussed in detail under the Device Addressing section). Table 1-1. Write Protect Part of the Array Protected WP Pin Status At VCC At GND Full Array 24C04B/08B Normal Read/Write Operations 3 5226D–SEEPR–7/08 2. Memory Organization AT24C04B, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires an 9-bit data word address for random word addressing. AT24C08B, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. Table 2-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V Table 2-2. DC Characteristics Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, (unless otherwise noted) Symbol VCC1 VCC2 VCC3 VCC4 ICC ICC ISB1 ISB2 ISB3 ISB4 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current VCC = 1.8V Standby Current VCC = 2.5V Standby Current VCC = 2.7V Standby Current VCC = 5.0V Input Leakage Current Output Leakage Current Input Low Level(1) Input High Level (1) Test Condition Min 1.8 2.5 2.7 4.5 Typ Max 5.5 5.5 5.5 5.5 Units V V V V mA mA µA µA µA µA µA µA V V V V READ at 100 kHz WRITE at 100 kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = VCC or VSS –0.6 VCC x 0.7 IOL = 2.1 mA IOL = 0.15 mA 0.4 2.0 0.6 1.4 1.6 8.0 0.10 0.05 1.0 3.0 3.0 4.0 4.0 18.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 Output Low Level VCC = 3.0V Output Low Level VCC = 1.8V 1. VIL min and VIH max are reference only and are not tested. 4 AT24C04B/08B 5226D–SEEPR–7/08 AT24C04B/08B Table 2-3. AC Characteristics Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 1.8, 2.5, 2.7 Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Note: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time Clock Low to Data Out Valid Time the bus must be free before a new transmission can start Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Inputs Rise Time (1) 5.0-volt Min Max 1000 0.4 0.4 Units kHz µs µs 40 0.05 0.5 0.25 0.25 0 100 0.55 ns µs µs µs µs µs ns 0.3 100 .25 50 µs ns µs ns 5 1M ms Write Cycles Min Max 400 1.2 0.6 50 0.1 1.2 0.6 0.6 0 100 0.3 300 0.6 50 5 1M 0.9 Inputs Fall Time(1) Stop Setup Time Data Out Hold Time Write Cycle Time 5.0V, 25°C, Byte Mode 1. This parameter is ensured by characterization only. 5 5226D–SEEPR–7/08 3. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5-2 on page 8). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5-3 on page 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5-3 on page 8). ACKNOWLEDGE: A ll a ddresses a nd d a t a w ords a re seri a lly tr a nsmitted to a nd from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C04B/08B features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. 2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by a stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Start bit Dummy Clock Cycles Start bit Stop bit SCL 1 2 3 8 9 SDA 6 AT24C04B/08B 5226D–SEEPR–7/08 AT24C04B/08B 4. Bus Timing Figure 4-1. SCL: Serial Clock, SDA: Serial Data I/O® tF tHIGH tLOW tR SCL tSU.STA tHD.STA tLOW tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT 5. Write Cycle Timing Figure 5-1. SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK WORDn twr STOP CONDITION Note: (1) START CONDITION 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 7 5226D–SEEPR–7/08 Figure 5-2. Data Validity SDA SCL DATA STABLE DATA CHANGE DATA STABLE Figure 5-3. Start and Stop Definition SDA SCL START STOP Figure 5-4. Output Acknowledge SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE 8 AT24C04B/08B 5226D–SEEPR–7/08 AT24C04B/08B 6. Device Addressing The 4K and 8K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 8-1). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hard-wired input pins. The A0 pin is no connect. The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect. For the SOT23 Package Offering: The 4K EEPROM software A2 and A1 bits in the device address word must be set to zero to properly communicate. The 8K EEPROM software A2 bit in the device address word must be set to zero to properly communicate. 7. Write Operations BYTE WRITE: A w rite oper a tion requires a n 8 - bit d a t a w ord a ddress following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will a gain respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page 11). PAGE WRITE: The 4K/8K EEPROMs are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Inste ad, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 8-3 on page 11). The data word address lower four bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than sixteen data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. ACKNOWLEDGE POLLING: O nce the intern a lly timed write cycle h a s st a rted a nd the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. 9 5226D–SEEPR–7/08 8. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: T he intern a l d a t a w ord a ddress counter m a int a ins the l a st address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 8-4 on page 11). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word a ddress. Once the device a ddress word a nd d a t a w ord a ddress a re clocked in a nd acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initi a tes a c urrent address re ad by sending a d evice address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 8-5 on page 11). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random a ddress re a d. After the microcontroller receives a d a t a w ord, it responds with a n acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 8-6 on page 12). Figure 8-1. Device Address 10 AT24C04B/08B 5226D–SEEPR–7/08 AT24C04B/08B Figure 8-2. Byte Write Figure 8-3. Page Write Figure 8-4. Current Address Read Figure 8-5. Random Read 11 5226D–SEEPR–7/08 Figure 8-6. Sequential Read 12 AT24C04B/08B 5226D–SEEPR–7/08 AT24C04B/08B AT24C04B Ordering Information Ordering Code AT24C04B-PU (Bulk form only) AT24C04BN-SH-B(1) (NiPdAu Lead Finish) AT24C04BN-SH-T(2) (NiPdAu Lead Finish) AT24C04B-TH-B (1) Voltage 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 Package 8P3 8S1 8S1 8A2 8A2 8Y6 5TS1 8U3-1 Die Sale Operation Range (NiPdAu Lead Finish) AT24C04B-TH-T(2) (NiPdAu Lead Finish) AT24C04BY6-YH-T(2) (NiPdAu Lead Finish) AT24C04B-TSU-T (2) (2) Lead-free/Halogen-free/ Industrial Temperature (–40°C to 85°C) AT24C04BU3-UU-T AT24C04B-W-11(3) Notes: Industrial Temperature (–40°C to 85°C) 1. “-B” denotes bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel. 3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Package Type 8P3 8S1 8A2 8Y6 5TS1 8U3-1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8-lead, 2.0 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23) 8-ball, die Ball Grid Array Package (dBGA2) Options –1.8 Low-voltage (1.8V to 5.5V) 13 5226D–SEEPR–7/08 AT24C08B Ordering Information Ordering Code AT24C08B-PU (Bulk form only) AT24C08BN-SH-B(1) (NiPdAu Lead Finish) AT24C08BN-SH-T(2) (NiPdAu Lead Finish) AT24C08B-TH-B (1) Voltage 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 Package 8P3 8S1 8S1 8A2 8A2 8Y6 5TS1 8U3-1 Die Sale Operation Range (NiPdAu Lead Finish) AT24C08B-TH-T(2) (NiPdAu Lead Finish) AT24C08BY6-YH-T(2) (NiPdAu Lead Finish) AT24C08B-TSU-T (2) (2) Lead-free/Halogen-free/ Industrial Temperature (–40°C to 85°C) AT24C08BU3-UU-T AT24C08B-W-11(3) Notes: Industrial Temperature (–40°C to 85°C) 1. “-B” denotes bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel. 3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Package Type 8P3 8S1 8A2 8Y6 5TS1 8U3-1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8-lead, 2.0 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23) 8-ball, die Ball Grid Array Package (dBGA2) Options –1.8 Low-voltage (1.8V to 5.5V) 14 AT24C04B/08B 5226D–SEEPR–7/08 AT24C04B/08B 9. Part marking scheme 9.1 8-PDIP Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark TOP MARK | | | |---|---|---|---|---|---|---|---| A T M L U Y W W |---|---|---|---|---|---|---|---| 0 4 B 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 9.2 8-SOIC Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark TOP MARK | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 0 4 B 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 15 5226D–SEEPR–7/08 9.3 8-TSSOP Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| 0 4 B 1 |---|---|---|---|---| Y = SEAL YEAR 6: 7: 8: 9: 2006 2007 2008 2009 0: 1: 2: 3: 2010 2011 2012 2013 WW = SEAL WEEK 02 04 :: :: = = : : Week Week :::: :::: 2 4 : :: TOP MARK 50 = Week 50 52 = Week 52 BOTTOM MARK |---|---|---|---|---|---|---| P H |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| |---|---|---|---|---| 4 B 1 B U |---|---|---|---|---| * | XX = Device V = Voltage Indicator W = Write Protect Feature U = Material Set Pin 1 Indicator (Dot) BOTTOM MARK |---|---|---|---| Y M T C |---|---|---|---| Y = One Digit Year Code M = Seal Month (Use Alpha Designator A-L) TC = Trace Code 9.7 dBGA2 TOP MARK 17 5226D–SEEPR–7/08 LINE 1-------> LINE 2-------> Pin 1 This Corner XXX = Device U = Material Set Y = One Digit Year Code M = Seal Month (Use Alpha Designator A-L) TC = Trace Code 04BU YMTC |