AT24C256CW-SH-T

Features • Low-voltage and Standard-voltage Operation ⎯ 1.8 (VCC = 1.8V to 5.5V) • Internally Organized as 32,768 x 8 • Two-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility • Write Protect Pin for Hardware and Software Data Protection • 64-byte Page Write Mode (Partial Page Writes Allowed) • Self-timed Write Cycle (5 ms Max) • High Reliability ⎯ Endurance: One Million Write Cycles ⎯ Data Retention: 40 Years • Lead-free/Halogen-free Devices Available • 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead Ultra Thin Small Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages • Die Sales: Wafer Form, Waffle Pack and Bumped Wafers Two-wire Serial EEPROM 256K (32,768 x 8) AT24C256C Description The AT24C256C provides 262,144 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin SAP, 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is available in a 1.8V (1.8V to 5.5V) version. Table 1. Pin Name A0 – A2 SDA SCL WP GND Pin Configurations Function Address Inputs Serial Data Serial Clock Input Write Protect Ground A0 A1 A2 GND 8-lead PDIP 1 2 3 4 8 7 6 5 8-lead SOIC VCC WP SCL SDA A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-ball dBGA2 VCC 8 WP 7 SCL 6 SDA 5 1 2 8-lead TSSOP A0 A1 A2 GND 1 2 3 4 8 7 6 5 A0 VCC WP SCL SDA A1 3 A2 4 GND Bottom View 8-lead Ultra-Thin SAP VCC 8 WP 7 SCL 6 SDA 5 1 A0 2 A1 3 A2 4 GND 8568A–SEEPR–11/08 Bottom View Absolute Maximum Ratings* Operating Temperature ........................... • 55°C to +125°C Storage Temperature ............................ • 65°C to + 150°C Voltage on Any Pin with Respect to Ground................................ • 1.0 V +7.0V Maximum Operating Voltage..................................... 6.25V DC Output Current .................................................. 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 1. Block Diagram VCC GND WP SCL SDA START STOP LOGIC LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 R/W COMP SERIAL CONTROL LOGIC EN H.V. PUMP/TIMING DATA RECOVERY INC X DEC LOAD DATA WORD ADDR/COUNTER EEPROM Y DEC SERIAL MUX DIN DOUT DOUT/ACK LOGIC 2 AT24C256C 8568A–SEEPR–11/08 AT24C256C 1. Pin Descriptions SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to VCC) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 256K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing”) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less. 3 8568A–SEEPR–11/08 2. Memory Organization AT24C256C, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64 bytes each. Random word addressing requires a 15-bit data word address. Table 2. Pin Capacitance (1) Applicable over recommended operating range from: TA = 25°C, f = 1.0 MHz, VCC = +1.8V Symbol CI/O CIN Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, SCL) Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V Note: 1. This parameter is characterized and is not 100% tested. Table 3. DC Characteristics Applicable over recommended operating range from: TAI = − 40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol VCC1 ICC1 ICC2 ISB1 Parameter Supply Voltage Supply Current Supply Current Standby Current (1.8V option) Input Leakage Currentt VCC = 5.0V Output Leakage Currentt VCC = 5.0V Input Low Level (1) Test Condition Min 1.8 Typ Max 5.5 Units V mA mA μA μA μA μA V V V V VCC = 5.0V VCC = 5.0V VCC = 1.8V VCC = 5.0V VIN = VCC or VSS VOUT = VCC or VSS READ at 400 kHz WRITE at 400 kHz VIN = VCC or VSS 1.0 2.0 2.0 3.0 1.0 6.0 ILI ILO VIL VIH VOL2 VOL1 0.10 0.05 0.6 VCC x 0.7 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 Input High Level (1) Output Low Level Output Low Level VCC = 3.0V VCC = 1.8V IOL = 2.1 mA IOL = 0.15 mA Note: 1. VIL min and VIH max are reference only and are not tested. 4 AT24C256C 8568A–SEEPR–11/08 AT24C256C Table 4. AC Characteristics (Industrial Temperature) Applicable over recommended operating range from: TAI = − 40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. 1.8-volt Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance (1) 2.5, 5.0-volt Units Min Max 1000 0.4 0.4 kHz μs μs 50 0.05 0.5 .25 0.25 0 100 0.55 ns μs μs μs μs μs ns 0.3 100 0.25 50 5 1,000,000 5 μs ns μs ns ms Write Cycles Parameter Min Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time (1) Max 400 1.3 0.6 100 0.05 (1) Clock Low to Data Out Valid Time the bus must be free before a new transmission can start Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time Inputs Fall Time (1) 0.9 1.3 0.6 0.6 0 100 0.3 300 0.6 50 (1) Stop Set-up Time Data Out Hold Time Write Cycle Time 25°C, Page Mode, 3.3V Note: 1. This parameter is ensured by characterization and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 kΩ (2.5V, 5.5V), 10 kΩ (1.8V) Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 50 ns Input and output timing reference voltages: 0.5 VCC 5 8568A–SEEPR–11/08 3. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below. Figure 2. Data Validity SDA SCL DATA STABLE DATA CHANGE START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (refer to Figure 3). Figure 3. Start and Stop Definition DATA STABLE SDA SCL START STOP STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Figure 3). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a “0” during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C256C features a low-power standby mode that is enabled upon power-up and after the receipt of the stop bit and the completion of any internal operations. 6 AT24C256C 8568A–SEEPR–11/08 AT24C256C SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: a) Create a start bit condition, b) Clock 9 cycles, c) Create another start bit followed by stop bit condition as shown below. The device is ready for next communication after above steps has been completed. Figure 4. Software Reset Start bit Dummy Clock Cycles Start bit Stop bit SCL 1 2 3 8 9 SDA Figure 5. Bus Timing tF tHIGH tLOW tR SCL tSU.STA tHD.STA tLOW tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT Figure 6. Write Cycle Timing SCL SDA 8th BIT WORDn ACK twr STOP CONDITION (1) START CONDITION Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 7 8568A–SEEPR–11/08 Figure 7. Output Acknowledge SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE 8 AT24C256C 8568A–SEEPR–11/08 AT24C256C 4. Device Addressing The 256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 8). The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all two-wire EEPROM devices. Figure 8. 1 MSB Device Addressing 0 1 0 A2 A1 A0 R/W LSB The next three bits are the A2, A1, A0 device address bits to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high, and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the device will return to a standby state. DATA SECURITY: The AT24C256C has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at VCC. 9 8568A–SEEPR–11/08 5. Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a microcontroller, must then terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 9). Figure 9. Byte Write Note: * = DON’T CARE bit PAGE WRITE: The 256K EEPROM is capable of 64-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 10). Figure 10. Page Write Note: * = DON’T CARE bit The data word address lower six bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0”, allowing the read or write sequence to continue. 10 AT24C256C 8568A–SEEPR–11/08 AT24C256C 6. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read, and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte of the first page. Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (refer to Figure 11). Figure 11. Current Address Read RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition. (Refer to Figure 12) Figure 12. Random Read Note: * = DON’T CARE bit 11 8568A–SEEPR–11/08 SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition (refer to Figure 13). Figure 13. Sequential Read 12 AT24C256C 8568A–SEEPR–11/08 AT24C256C 7. AT24C256C Ordering Codes Ordering Code AT24C256C-PU (Bulk Form Only) (1) AT24C256CN-SH-B (NiPdAu Lead Finish) (2) AT24C256CN-SH-T (NiPdAu Lead Finish) (1) AT24C256CW-SH-B (NiPdAu Lead Finish) (2) AT24C256CW-SH-T (NiPdAu Lead Finish) (1) AT24C256C-TH-B (NiPdAu Lead Finish) (2) AT24C256C-TH-T (NiPdAu Lead Finish) (2) AT24C256CY7-YH-T (NiPdAu Lead Finish) (2) AT24C256CU2-UU-T AT24C256C-W-11 Voltage 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 Package 8P3 8S1 8S1 8S2 8S2 8A2 8A2 8Y7 8U2-1 Die Sale Operating Range Lead-free/Halogen-free Industrial Temperature (−40°C to 85°C) Industrial Temperature (−40°C to 85°C) Note: 1. “-B” denotes bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP and dBGA2 = 5K per reel. SAP = 3K per reel. EIAJ = 2K per reel. 3. Available in tape & reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Contact Serial Interface Marketing. Package Type 8P3 8S1 8S2 8U2-1 8A2 8Y7 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.200” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8-ball, die Ball Grid Array Package (dBGA2) 8-lead, 4.40 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP) Options 1.8 Low-voltage (1.8V to 5.5V) 13 8568A–SEEPR–11/08 8. Part Marketing Scheme 8-PDIP Top Mark Seal Year Seal Week --- --- --- --U Y W W --- --- --- --1 --- --- --- --Y= 6: 7: 8: 9: WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK 2010 2011 2012 2013 No Bottom Mark SEAL YEAR 2006 0: 2007 1: 2008 2: 2009 3: --A --2 * --- --- --- --T M L --- --- --E C Lot Number --- --- --- Pin 1 Indicator (Dot) 8-SOIC Top Mark Seal Year Seal Week --- --- --- --H Y W W --- --- --- --1 --- --- --- --Y= 6: 7: 8: 9: WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK 1 --A --2 * --- --- --- --T M L --- --- --E C Lot Number --- --- --- SEAL YEAR 2006 0: 2007 1: 2008 2: 2009 3: 2010 2011 2012 2013 Pin 1 Indicator (Dot) No Bottom Mark 8-TSSOP Top Mark Pin 1 Indicator (Dot) --- --- --- --* H Y W W --- --- --- --- --2 E C 1 --- --- --- --- --Y= 6: 7: 8: 9: SEAL YEAR 2006 0: 2007 1: 2008 2: 2009 3: WW 02 04 :: :: 50 52 = = = : : = = SEAL Week Week :::: :::: Week Week WEEK 2 4 : :: 50 52 2010 2011 2012 2013 Bottom Mark --- --- --- --- --- --- --X X --- --- --- --- --- --- --A A A A A A A Line 2 -----------> 2ECU YMTC