AT24C32CY6-YH-T

(Features • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8 to 5.5V) Internally Organized 4096 x 8, 8192 x 8 2-Wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 1 MHz (5.0V) and 400 KHz (1.8V Compatibility) Write Protect Pin for Hardware Data Protection 32-Byte Page Write Mode (Partial Page Writes Allowed) Self-Timed Write Cycle (5 ms max) High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years • Lead-free/Halogen-free Devices • 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3), and 8-ball dBGA2 Packages. • Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers • • • • • • • • • 2-Wire Serial EEPROM 32K (4096 x 8) 64K (8192 x 8) Description The AT24C32C/64C provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common 2wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32C/64C is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3) and, 8ball dBGA2 packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 1.8V (1.8 to 5.5V) version. AT24C32C AT24C64C Pin Configurations Pin Name A0 - A2 SDA SCL WP Function Address Inputs Serial Data Serial Clock Input Write Protect 8-lead Ultra Thin Mini-MAP (MLP 2x3) VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND 8-lead Ultra Lead Frame Land Grid Array (ULA) VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND 2-Wire, 32K Serial E2PROM Bottom View Bottom View 8-ball dBGA2 VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND 8-lead TSSOP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA Bottom View 8-lead SOIC A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 A2 GND 8-lead PDIP 1 2 3 4 8 7 6 5 VCC WP SCL SDA 5298A–SEEPR–1/08 Absolute Maximum Ratings* Operating Temperature...................................... -55 to +125°C Storage Temperature ......................................... -65 to +150°C Voltage on Any Pin with Respect to Ground ....................................... -1.0 to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. Block Diagram VCC GND WP SCL SDA START STOP LOGIC LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 R/W COMP SERIAL CONTROL LOGIC EN H.V. PUMP/TIMING DATA RECOVERY INC X DEC EEPROM LOAD DATA WORD ADDR/COUNTER Y DEC SERIAL MUX DIN DOUT DOUT/ACK LOGIC 2 AT24C32C/64C 5298A–SEEPR–1/08 AT24C32C/64C 2. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired or left not connected for hardware compatibility with other AT24CXX devices. When the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is 3pF, Atmel® recommends connecting the address pins to GND. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected high to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is 3pF, Atmel recommends connecting the pin to GND. 3 5298A–SEEPR–1/08 3. Memory Organization AT24C32C/64C, 32/64K SERIAL EEPROM: The 32K/64K is internally organized as 128/256 pages of 32 bytes each. Random word addressing requires a 12/13 bit data word address. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V to 5.5V Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40 to +85°C, VCC = +1.8 to +5.5V (unless otherwise noted) Symbol VCC1 ICC1 ICC2 ISB1 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Current Supply Current Standby Current (1.8V option) Input Leakage Current VCC = 5.0V Output Leakage Current VCC = 5.0V Input Low Level(1) Input High Level (1) Test Condition Min 1.8 Typ Max 5.5 Units V mA mA µA µA µA µA V V V V VCC = 5.0V VCC = 5.0V VCC = 1.8V VCC = 5.5V VIN = VCC or VSS VOUT = VCC or VSS READ at 400 kHz WRITE at 400 kHz VIN = VCC or VSS 0.4 2.0 1.0 3.0 1.0 6.0 0.10 0.05 −0.6 VCC x 0.7 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 Output Low Level Output Low Level VCC = 3.0V VCC = 1.8V IOL = 2.1 mA IOL = 0.15 mA 1. VIL min and VIH max are reference only and are not tested. 4 AT24C32C/64C 5298A–SEEPR–1/08 AT24C32C/64C AC Characteristics Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 1.8-volt Symbol fSCL tLOW tHIGH ti tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Notes: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time (1) 5.0-volt Min Max 1000 0.4 0.4 Units kHz µs µs 50 0.05 0.5 0.25 0.25 0 100 0.55 ns µs µs µs µs µs ns 0.3 100 0.25 50 µs ns µs ns 5 1,000,000 ms Write Cycles Min Max 400 1.3 0.6 100 0.05 1.3 0.6 0.6 0 100 0.3 300 0.6 50 5 0.9 Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time Inputs Fall Time (1) (1) Stop Set-up Time Data Out Hold Time Write Cycle Time 25°C, Page Mode, 3.3V 1. This parameter is ensured by characterization. 2. AC measurement conditions: RL (connects to VCC): 1.3 kΩ (2.5V, 5.0V), 10 kΩ (1.8V) Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 50 ns Input and output timing reference voltages: 0.5 VCC 5 5298A–SEEPR–1/08 4. Device Operation CLOCK and DATA TRANSITIONS: T he SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: A ll addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C32C/64C features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the Stop bit and the completion of any internal operations. SOFTWARE RESET: After an interruption in protocol, power loss or system reset, and 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Figure 4-1. Software Reset Start bit Dummy Clock Cycles Start bit Stop bit SCL 1 2 3 8 9 SDA 6 AT24C32C/64C 5298A–SEEPR–1/08 AT24C32C/64C 5. Bus Timing SCL: Serial Clock, SDA: Serial Data I/O tF tHIGH tLOW tR tLOW SCL tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT 6. Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK WORDn twr STOP CONDITION Note: (1) START CONDITION 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 7 5298A–SEEPR–1/08 7. Data Validity SDA SCL DATA STABLE DATA CHANGE DATA STABLE 8. Start and Stop Definition SDA SCL START STOP 9. Output Acknowledge SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE 8 AT24C32C/64C 5298A–SEEPR–1/08 AT24C32C/64C 10. Device Addressing The 32K/64K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 12-1 on page 11). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices. The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to standby state. DATA SECURITY: The AT24C32C/64C has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC. 11. Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 12-2 on page 11). PAGE WRITE: The 32K/64K EEPROM is capable of 32-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 12-3 on page 11). The data word address lower 5 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. ACKNOWLEDGE POLLING: O nce the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue. 9 5298A–SEEPR–1/08 12. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: T he internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 12-4 on page 12). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12-5 on page 12). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12-6 on page 12). Figure 12-1. Device Address Figure 12-2. Byte Write 10 AT24C32C/64C 5298A–SEEPR–1/08 AT24C32C/64C Figure 12-3. Page Write t Note: 1. * = DON’T CARE bits 2. t = DON’T CARE bit for AT24C32C Figure 12-4. Current Address Read Figure 12-5. Random Read Note: 1. * = DON’T CARE bits 11 5298A–SEEPR–1/08 Figure 12-6. Sequential Read 12 AT24C32C/64C 5298A–SEEPR–1/08 AT24C32C/64C AT24C32C Ordering Information Ordering Code AT24C32C-PU (Bulk form only) AT24C32CN-SH-B(1) (NiPdAu Lead Finish) AT24C32CN-SH-T(2) (NiPdAu Lead Finish) AT24C32C-TH-B(1) (NiPdAu Lead Finish) AT24C32C-TH-T(2) (NiPdAu Lead Finish) AT24C32CY6-YH-T(2) (NiPdAu Lead Finish) AT24C32CD3-DH-T(2) (NiPdAu Lead Finish) AT24C32CU2-UU-T(2) AT24C32C-W-11(3) Notes: 1. “-B” denotes Bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP and dBGA2 = 5K per reel. 3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Voltage 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 Package 8P3 8S1 8S1 8A2 8A2 8Y6 8D3 8U2-1 Die Sale Operation Range Lead-free/Halogen-free Industrial Temperature (-40°C to 85°C) Industrial Temperature (-40°C to 85°C) Package Type 8Y6 8P3 8S1 8A2 8U2-1 8D3 8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Ultra Thin Mini-MAP, Dual no Lead Package (DFN), (MLP 2x3) 8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic, Thin Shrink Small Outline Package (TSSOP) 8-ball, die Ball Grid Array Package (dBGA2) 8-lead, 1.80 mm x 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULA) Options -1.8 Low Voltage (1.8V to 5.5V) 13 5298A–SEEPR–1/08 AT24C64C Ordering Information Ordering Code AT24C64C-PU (Bulk form only) AT24C64CN-SH-B(1) (NiPdAu Lead Finish) AT24C64CN-SH-T(2) (NiPdAu Lead Finish) AT24C64C-TH-B(1) (NiPdAu Lead Finish) AT24C64C-TH-T(2) (NiPdAu Lead Finish) AT24C64CY6-YH-T(2) (NiPdAu Lead Finish) AT24C64CD3-DH-T(2) (NiPdAu Lead Finish) AT24C64CU2-UU-T(2) AT24C64C-W-11(3) Notes: 1. “-B” denotes Bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP and dBGA2 = 5K per reel. 3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Voltage 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 Package 8P3 8S1 8S1 8A2 8A2 8Y6 8D3 8U2-1 Die Sale Operation Range Lead-free/Halogen-free Industrial Temperature (-40°C to 85°C) Industrial Temperature (-40°C to 85°C) Package Type 8Y6 8P3 8S1 8A2 8U2-1 8D3 8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Ultra Thin Mini-MAP, Dual no Lead Package (DFN), (MLP 2x3) 8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic, Thin Shrink Small Outline Package (TSSOP) 8-ball, die Ball Grid Array Package (dBGA2) 8-lead, 1.80 mm x 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULA) Options -1.8 Low Voltage (1.8V to 5.5V) 14 AT24C32C/64C 5298A–SEEPR–1/08 AT24C32C/64C 13. Part Marking Scheme 13.1 8-PDIP Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark TOP MARK | | | |---|---|---|---|---|---|---|---| A T M L U Y W W |---|---|---|---|---|---|---|---| 3 2 C 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 13.2 8-SOIC Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark TOP MARK | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 3 2 C 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 15 5298A–SEEPR–1/08 13.3 8-TSSOP Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| 3 2 C 1 |---|---|---|---|---| Y = SEAL YEAR 6: 7: 8: 9: 2006 2007 2008 2009 0: 1: 2: 3: 2010 2011 2012 2013 WW = SEAL WEEK 02 04 :: :: = = : : Week Week :::: :::: 2 4 : :: TOP MARK 50 = Week 50 52 = Week 52 BOTTOM MARK |---|---|---|---|---|---|---| P H |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---|