AT25256

Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) • Low-voltage and Standard-voltage Operation • • • • • • • • – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 5.5V) 3 MHz Clock Rate 64-byte Page Mode and Byte Write Operation Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5 ms Typical) High-reliability – Endurance: 100,000 Write Cycles – Data Retention: >200 Years Automotive Grade, Extended Temperature and Lead-Free Devices Available 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead and 16-lead JEDEC SOIC, 14-lead and 20-lead TSSOP, and 8-lead Leadless Array Packages SPI Serial EEPROMs 128K (16,384 x 8) 256K (32,768 x 8) Description The AT25128/256 provides 131,072/262,144 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space saving 8-lead PDIP (AT25128/256), 8-lead EIAJ SOIC (AT25128/256), 8-lead and 16-lead JEDEC SOIC (AT25128), 14-lead TSSOP (AT25128), 20-lead TSSOP (AT25128/256), and 8-lead Leadless Array (AT25256) packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions. Table 1. Pin Configuration Pin Name CS SCK SI SO GND VCC WP HOLD NC DC Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input No Connect Don't Connect CS SO NC NC NC NC WP GND CS SO NC NC NC WP GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI AT25128(1) AT25256(2) Notes: 1. This device is not recommended for new designs. Please refer to AT25128A. 2. This device is not recommended for new designs. Please refer to AT25256A. 14-lead TSSOP NC CS SO SO NC NC WP GND DC NC 20-lead TSSOP* 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC VCC HOLD HOLD NC NC SCK SI DC NC 8-lead PDIP CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 8-lead Leadless Array VCC HOLD SCK SI 8 7 6 5 1 2 3 4 CS SO WP GND 16-lead SOIC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC HOLD NC NC NC NC SCK SI Bottom View 8-lead SOIC CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI *Note: Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility. Rev. 0872O–SEEPR–03/05 1 The AT25128/256 is enabled through the Chip Select pin (CS) and accessed via a 3wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate Erase cycle is required before Write. Block Write protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Absolute Maximum Ratings* Operating Temperature..................................–55°C to +125°C Storage Temperature .....................................–65°C to +150°C Voltage on Any Pin with Respect to Ground .................................... –1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 1. Block Diagram 16384/32768 x 8 2 AT25128/256 0872O–SEEPR–03/05 AT25128/256 Table 2. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol COUT CIN Note: Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V Table 3. DC Characteristics Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, TAE = –40°C to +125°C, VCC = +1.8V to +5.5V(unless otherwise noted) Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ISB1 ISB2 ISB3 IIL IOL VIL(1) VIH(1) VOL1 VOH1 VOL2 VOH2 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low-voltage Input High-voltage Output Low-voltage Output High-voltage Output Low-voltage Output High-voltage 4.5 ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 3.6V IOL = 3.0 mA IOH = –1.6 mA IOL = 0.15 mA IOH = –100 µA VCC - 0.2 VCC - 0.8 0.2 VCC = 5.0V at 1 MHz, SO = Open, Read VCC = 5.0V at 2 MHz, SO = Open, Read, Write VCC = 1.8V, CS = VCC VCC = 2.7V, CS = VCC VCC = 5.0V, CS = VCC VIN = 0V to VCC VIN = 0V to VCC, TAC = 0°C to 70°C –3.0 –3.0 –1.0 VCC x 0.7 Test Condition Min 1.8 2.7 4.5 2.0 3.0 0.1 0.2 2.0 Typ Max 5.5 5.5 5.5 3.0 5.0 2.0 2.0 5.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 Units V V V mA mA µA µA µA µA µA V V V V V V 1. VIL and VIH max are reference only and are not tested. 3 0872O–SEEPR–03/05 Table 4. AC Characteristics Applicable over recommended operating range from TAI = –40°C to + 85°C, TAE = –40°C to +125°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Symbol fSCK Parameter SCK Clock Frequency Voltage 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 150 200 800 150 200 800 250 250 1000 100 250 1000 150 250 1000 30 50 100 50 50 100 100 100 400 200 300 400 0 0 0 0 0 0 0 0 0 100 200 300 150 200 800 Min 0 0 0 Max 3.0 2.1 0.5 2 2 2 2 2 2 Units MHz tRI Input Rise Time µs tFI Input Fall Time µs tWH SCK High Time ns tWL SCK Low Time ns tCS CS High Time ns tCSS CS Setup Time ns tCSH CS Hold Time ns tSU Data In Setup Time ns tH Data In Hold Time ns tHD Hold Setup Time ns tCD Hold Hold Time ns tV Output Valid ns tHO Output Hold Time ns tLZ Hold to Output Low Z ns 4 AT25128/256 0872O–SEEPR–03/05 AT25128/256 Table 4. AC Characteristics (Continued) Applicable over recommended operating range from TAI = –40°C to + 85°C, TAE = –40°C to +125°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Symbol tHZ Parameter Hold to Output High Z Voltage 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 4.5 – 5.5 2.7 – 5.5 1.8 – 5.5 100K Min Max 100 200 300 200 250 1000 5 10 10 Units ns tDIS Output Disable Time ns tWC Endurance(1) Note: Write Cycle Time 5.0V, 25°C, Page Mode ms Write Cycles 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128/256 always operates as a slave. TRANSMITTER/RECEIVER: The AT25128/256 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128/256, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25128/256 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128/256. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25128/256 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”. 5 0872O–SEEPR–03/05 Figure 2. SPI Serial Interface AT25128/256 Functional Description The AT25128/256 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25128/256 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 5. Instruction Set for the AT25128/256 Instruction Name WREN WRDI RDSR WRSR READ WRITE Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010 Operation Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array 6 AT25128/256 0872O–SEEPR–03/05 AT25128/256 WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 6. Status Register Format Bit 7 WPEN Bit 6 X Bit 5 X Bit 4 X Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY Table 7. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 1 (WEN) Bit 2 (BP0) Bit 3 (BP1) Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle is in progress. Bit 1 = “0” indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. See Table 8. See Table 8. Bits 4 - 6 are “0”s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 9. Bits 0 – 7 are “1”s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128/256 is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 8. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR). Table 8. Block Write Protect Bits Status Register Bits Level 0 1(1/4) 2(1/2) 3(All) BP1 0 0 1 1 BP0 0 1 0 1 Array Addresses Protected AT25128 None 3000 - 3FFF 2000 - 3FFF 0000 - 3FFF AT25256 None 6000 - 7FFF 4000 - 7FFF 0000 - 7FFF 7 0872O–SEEPR–03/05 The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low. Table 9. WPEN Operation WPEN 0 0 1 1 X X WP X X Low Low High High WEN 0 1 0 1 0 1 Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable READ SEQUENCE (READ): Reading the AT25128/256 via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the READ op-code is transmitted via the SI line followed by the byte address to be read (see Table 10 on page 9). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the AT25128/256, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then a Write instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the Write op-code is transmitted via the SI line followed by the byte address and the data (D7 – D0) to be programmed (see Table 10 on page 9). Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle. 8 AT25128/256 0872O–SEEPR–03/05 AT25128/256 The AT25128/256 is capable of a 64-byte page write operation. After each byte of data is received, the six-low order address bits are internally incremented by one; the highorder bits of the address will remain constant. If more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25128/256 is automatically returned to the write disable state at the completion of a write cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication. Table 10. Address Key Address AN Don’t Care Bits AT25128 A13 - A0 A15 - A14 AT25256 A14 - A0 A15 Timing Diagrams (for SPI Mode 0 (0, 0)) Figure 3. Synchronous Data Timing VIH CS VIL t CSS VIH SCK VIL t SU VIH SI VIL tV VOH SO VOL HI-Z t HO t DIS HI-Z VALID IN tH t WH t WL t CSH t CS 9 0872O–SEEPR–03/05 Figure 4. WREN Timing Figure 5. WRDI Timing Figure 6. RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK SI INSTRUCTION SO HIGH IMPEDANCE DATA OUT 7 6 5 4 3 2 1 0 MSB 10 AT25128/256 0872O–SEEPR–03/05 AT25128/256 Figure 7. WRSR Timing Figure 8. READ Timing Figure 9. WRITE Timing 11 0872O–SEEPR–03/05 Figure 10. HOLD Timing CS tCD tCD SCK tHD HOLD tHZ tHD SO tLZ 12 AT25128/256 0872O–SEEPR–03/05 AT25128/256 AT25128(1) Ordering Information Ordering Code(2) AT25128-10PI-2.7 AT25128N-10SI-2.7 AT25128W-10SI-2.7 AT25128N1-10SI-2.7 AT25128T1-10TI-2.7 AT25128-10PI-1.8 AT25128N-10SI-1.8 AT25128W-10SI-1.8 AT25128N1-10SI-1.8 AT25128T1-10TI-1.8 AT25128N-10SJ-2.7 AT25128N-10SJ-1.8 AT25128N-10SE-2.7 Notes: Package 8P3 8S1 8S2 16S1 14A2 8P3 8S1 8S2 16S1 14A2 8S1 8S1 8S1 Operation Range Industrial Temperature (–40°C to 85°C) Industrial Temperature (–40°C to 85°C) Lead-Free/Industrial Temperature (–40°C to 85°C) High Grade/Extended Temperature (–40°C to 125°C) 1. This device is not recommended for new designs. Please refer to AT25128A. 2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. Package Type 8P3 8S1 8S2 16S1 14A2 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 16-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options –2.7 –1.8 Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 5.5V) 13 0872O–SEEPR–03/05 AT25256(1) Ordering Information Ordering Code(2) AT25256-10PI-2.7 AT25256W-10SI-2.7 AT25256-10CI-2.7 AT25256T2-10TI-2.7 AT25256-10PI-1.8 AT25256W-10SI-1.8 AT25256-10CI-1.8 AT25256T2-10TI-1.8 AT25256W-10SJ-2.7 AT25256W-10SJ-1.8 AT25256W-10SE-2.7 Notes: Package 8P3 8S2 8CN3 20A2 8P3 8S2 8CN3 20A2 8S2 8S2 8S2 Operation Range Industrial Temperature (–40°C to 85°C) Industrial Temperature (–40°C to 85°C) Lead-Free/Industrial Temperature (–40°C to 85°C) High Grade/Extended Temperature (–40°C to 125°C) 1. This device is not recommended for new designs. Please refer to AT25256A. 2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. Package Type 8P3 8S2 8CN3 20A2 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8-lead, 0.230" Wide, Leadless Array Package (LAP) 20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options –2.7 –1.8 Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 5.5V) 14 AT25128/256 0872O–SEEPR–03/05 AT25128/256 Packaging Information 8P3 – PDIP E E1 1 N Top View c eA End View D e D1 A2 A SYMBOL COMMON DIMENSIONS (Unit of Measure = inches) MIN – NOM – MAX NOTE A A2 b b2 b3 c D 0.210 0.195 0.022 0.070 0.045 0.014 0.400 – 2 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.130 0.018 0.060 0.039 0.010 0.365 – 5 6 6 3 3 4 3 b2 b3 4 PLCS L D1 E E1 e eA L b 0.310 0.250 0.100 BSC 0.300 BSC 0.325 0.280 Side View 4 0.150 2 0.115 0.130 Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B R 15 0872O–SEEPR–03/05 8S1 – JEDEC SOIC C 1 E E1 N ∅ L Top View End View e B A SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM – – – – – – – 1.27 BSC 0.40 0° – – 1.27 8° MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE A1 A A1 B C D D E1 E Side View e L ∅ Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 10/7/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B R 16 AT25128/256 0872O–SEEPR–03/05 AT25128/256 8S2 – EIAJ SOIC C 1 E E1 N L ∅ Top View End View e A SYMBOL b COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE A1 A A1 b C 1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 0° 1.27 BSC 2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85 8° 4 2, 3 5 5 D D E1 E L ∅ Side View e Notes: 1. 2. 3. 4. 5. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm. 10/7/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. R 8S2 REV. C 17 0872O–SEEPR–03/05 8CN3 – LAP Marked Pin1 Indentifier E D A A1 Top View 0.10 mm TYP 8 Side View L1 1 Pin1 Corner e 7 2 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.94 0.30 0.36 5.89 4.83 NOM 1.04 0.34 0.41 5.99 4.93 1.27 BSC 0.56 REF 0.62 0.92 0.67 0.97 0.72 1.02 Note 1 Note 1 MAX 1.14 0.38 0.46 6.09 5.03 Note 1 NOTE 6 3 A A1 b 5 4 b D E e1 L e e1 L L1 Bottom View Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm 11/8/04 DRAWING NO. 8CN3 REV. B R 1150 E.Cheyenne Mtn Blvd. Colorado Springs, CO 80906 TITLE 8CN3, 8-lead, (6 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) 18 AT25128/256 0872O–SEEPR–03/05 AT25128/256 16S1 – JEDEC SOIC 3 2 1 H N Top View e B A D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A MIN 1.35 0.33 0.19 9.80 3.80 NOM – – – – – 1.27 BSC 5.80 0.40 – – 6.20 1.27 4 MAX 1.75 0.51 0.25 10.00 4.00 2 3 5 NOTE Side View A2 C B C D E L E e H L End View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. L is the length of terminal for soldering to a substrate. 5. The lead width B, as measured 0.36 mm (0.014 in) or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024 in). 10/15/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 16S1, 16-lead, 0.150" Body, Plastic Gull Wing Small Outline (SOIC ) DRAWING NO. 16S1 REV. A 19 0872O–SEEPR–03/05 14A2 – TSSOP b L L1 E1 E End View e COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D MIN 4.90 NOM 5.00 6.40 BSC 4.30 – 0.80 0.19 4.40 – 1.00 – 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 5.10 NOTE 2, 5 Top View A D E A2 E1 A A2 b e Side View L L1 Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AB-1, for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 12/28/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 14A2,14-lead (4.4 x 5 mm Body), 0.65 Pitch, Thin Shrink Small Outline Package (TSSOP) DRAWING NO. REV. 14A2 A 20 AT25128/256 0872O–SEEPR–03/05 AT25128/256 20A2 – TSSOP b L L1 E E1 e End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D MIN 6.40 NOM 6.50 6.40 BSC 4.30 – 0.80 0.19 4.40 – 1.00 – 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 6.60 NOTE 2, 5 Top View D A A2 E E1 A A2 b e Side View Notes: L L1 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AC, for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 6/3/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 20A2, 20-lead (4.4 x 6.5 mm Body), 0.65 pitch, Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 20A2 REV. C R 21 0872O–SEEPR–03/05 A tmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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