AT25256B

Features • • • • • • • • • • Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Data Sheet Describes Mode 0 Operation Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 5.5V) 20 MHz Clock Rate (5V) 64-byte Page Mode and Byte Write Operation Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5 ms Max) High-reliability – Endurance: 1 Million Write Cycles – Data Retention: >100 Years Green (Pb/Halide-free/RoHS Compliant) Packaging Options Die Sales: Wafer Form, Waffle Pack, and Bumped Die SPI Serial EEPROMS 128K (16,384 x 8) 256K (32,768 x 8) • • Description The AT25128B/256B provides 131,072/262,144 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space saving 8-lead SOIC, 8-lead TSSOP, 8-ball VFBGA and 8-lead UDFN packages. In addition, the entire family is available in 1.8V (1.8V to 5.5V). The AT25128B/256B is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate Erase cycle is required before Write. Table 0-1. Pin CS SCK SI SO GND VCC WP HOLD AT25128B AT25256B Pin Configurations Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input 8-lead UDFN VCC HOLD SCK SI 8 7 6 5 1 CS 2 SO 3 WP 4 GND 8-lead SOIC CS SO WP GND 1 2 3 4 8 7 6 5 8-lead TSSOP VCC HOLD SCK SI CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 8-ball VFBGA VCC HOLD SCK SI 8 7 6 5 1 2 3 4 CS SO WP GND Bottom View Bottom View Block Write protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The H O L D pin may be used to suspend any serial communication without resetting the serial sequence. 8698B–SEEPR–3/10 1. Absolute Maximum Ratings* Operating Temperature ........................–55°C to +125°C Storage Temperature .........................–65°C to + 150°C Voltage on Any Pin with Respect to Ground.............................. –1.0 V +7.0V Maximum Operating Voltage................................. 6.25V DC Output Current .............................................. 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 1-1. Block Diagram 16384/32768 x 8 2 AT25128B/256B 8698B–SEEPR–3/10 AT25128B/256B Table 1-1. Pin Capacitance (1 Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol COUT CIN Notes: Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V Table 1-2. DC Characteristics Applicable over recommended operating range from TA = −40°C to +85°C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V(unless otherwise noted) Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ICC3 ISB1 ISB2 ISB3 IIL IOL VIL(1) VIH (1) Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Supply Current Standby Current Standby Current Standby Current Input Current Output Leakage Input Low-voltage Input High-voltage Output Low-voltage Output High-voltage Output Low-voltage Output High-voltage Test Condition Min 1.8 2.5 4.5 Typ Max 5.5 5.5 5.5 Units V V V mA mA mA µA µA µA µA µA V V V V VCC = 5.0V at 20 MHz, SO = Open, Read VCC = 5.0V at 10 MHz, SO = Open, Read, Write VCC = 5.0V at 1 MHz, SO = Open, Read, Write VCC = 1.8V, CS = VCC VCC = 2.5V, CS = VCC VCC = 5.0V, CS = VCC VIN = 0V to VCC VIN = 0V to VCC, TAC = 0°C to 70°C –3.0 –3.0 –1.0 VCC x 0.7 3.6V  VCC  5.5V 1.8V  VCC  3.6V IOL = 3.0 mA IOH = 1.6 mA IOL = 0.15 mA IOH = 100 µA VCC - 0.2 VCC - 0.8 9.0 5.0 2.2 0.2 0.5 2.0 10.0 7.0 3.5 3.0 3.0 5.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 VOL1 VOH1 VOL2 VOH2 Notes: 0.2 V V 1. VIL min and VIH max are reference only and are not tested. 3 8698B–SEEPR–3/10 Table 1-3. AC Characteristics Applicable over recommended operating range from TA = – 40°C to + 85°C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted) Symbol Parameter SCK Clock Frequency Voltage 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 20 40 80 20 40 80 100 100 200 100 100 200 100 100 200 5 10 20 5 10 20 5 10 20 5 10 20 0 0 0 0 0 0 20 40 80 Min 0 0 0 Max 20 10 5 2 2 2 2 2 2 Units MHz fSCK tRI Input Rise Time µs tFI Input Fall Time µs tWH SCK High Time ns tWL SCK Low Time ns tCS CS High Time ns tCSS CS Setup Time ns tCSH CS Hold Time ns tSU Data In Setup Time ns tH Data In Hold Time ns tHD HOLD Setup Time ns tCD HOLD Hold Time ns tV Output Valid ns tHO Output Hold Time ns 4 AT25128B/256B 8698B–SEEPR–3/10 AT25128B/256B Table 1-3. AC Characteristics (Continued) Applicable over recommended operating range from TA = – 40°C to + 85°C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted) Symbol Parameter HOLD to Output Low Z Voltage 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 4.5–5.5 2.5–5.5 1.8–5.5 1M Min 0 0 0 Max 25 50 100 25 50 100 25 50 100 5 5 5 Units ns tLZ tHZ HOLD to Output High Z ns tDIS Output Disable Time ns tWC Endurance (1) Write Cycle Time ms 3.3V, 25°C, Page Mode Write Cycles Notes: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. 2. Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128B/256B always operates as a slave. TRANSMITTER/RECEIVER: The AT25128B/256B has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL-OP CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128B/256B, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25128B/256B is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128B/256B. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25128B/256B in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”. 5 8698B–SEEPR–3/10 Figure 2-1. SPI Serial Interface AT25128B/256B 6 AT25128B/256B 8698B–SEEPR–3/10 AT25128B/256B 3. Functional Description The AT25128B/256B is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25128B/256B utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 3-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-tolow CS transition. Table 3-1. Instruction Set for the AT25128B/256B Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X 010 Operation Set Write Enable Latch Reset Write Enable Register Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array Instruction Name WREN WRDI RDSR WRSR READ WRITE WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 3-2. Bit 7 WPEN Status Register Format Bit 6 X Bit 5 X Bit 4 X Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY Table 3-3. Bit Bit 0 (RDY) Bit 1 (WEN) Bit 2 (BP0) Bit 3 (BP1) Read Status Register Bit Definition Definition Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write cycle is in progress. Bit 1 = 0 indicates the device is not write enabled. Bit 1 = “1” indicates the device is write enabled. See Table 2-4 on page 9. See Table 2-4 on page 9. Bits 4 – 6 are 0s when device is not an internal write cycle. Bit 7 (WPEN) See Table 3-5 on page 8 Bits 0 – 7 are “1”s during an internal write cycle. 7 8698B–SEEPR–3/10 WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128B/256B is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table 2-4. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR) Table 3-4. Level 0 1 (1/4) 2 (1/2) 3 (All) Block Write Protect Bits. Status Register Bits BP1 0 0 1 1 BP0 0 1 0 1 Array Addresses Protected AT25128B None 3000 – 3FFF 2000 – 3FFF 0000 – 3FFF AT25256B None 6000 – 7FFF 4000 – 7FFF 0000 – 7FFF The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the write protect enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the blockprotected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. Note: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low. Table 3-5. WPEN 0 0 1 1 X X WPEN Operation WP X X Low Low High High WEN 0 1 0 1 0 1 Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable READ SEQUENCE (READ): Reading the AT25128B/256B via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read op-code is transmitted via the SI line followed by the byte address to be read (Table 2-6). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. 8 AT25128B/256B 8698B–SEEPR–3/10 AT25128B/256B WRITE SEQUENCE (WRITE): In order to program the AT25128B/256B, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the Write op-code is transmitted via the SI line followed by the byte address and the data (D7 - D0) to be programmed (see Table 2-6 for the address key). Programming will start after the CS pin is brought high. (The Low-to-High transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has ended. Only the Read Status Register instruction is enabled during the Write programming cycle. The AT25128B/256B is capable of a 64-byte Page Write operation. After each byte of data is received, the six low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25128B/256B is automatically returned to the write disable state at the completion of a Write cycle. Note: If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 3-6. Address Key Address AN AT25128B A13 − A0 A15 − A14 AT25256B A14 − A0 A15 Don’t Care Bits 9 8698B–SEEPR–3/10 4. Timing Diagram (for SPI Mode 0 (0,0) Figure 4-1. VIH Synchronous Data Timing t CS CS VIL tCSS t CSH VIH SCK VIL t SU t WH t WL tH VIH SI VIL VALID IN tV t HO t DIS HI-Z VOH SO VOL HI-Z Figure 4-2. CS WREN Timing SCK SI WREN OP-CODE SO HI-Z Figure 4-3. CS WRDI Timing SCK SI WRDI OP-CODE SO HI-Z 10 AT25128B/256B 8698B–SEEPR–3/10 AT25128B/256B Figure 4-4. CS RDSR Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK SI INSTRUCTION DATA OUT SO HIGH IMPEDANCE 7 MSB 6 5 4 3 2 1 0 Figure 4-5. CS WRSR Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK DATA IN SI INSTRUCTION 7 6 5 4 3 2 1 0 SO HIGH IMPEDANCE Figure 4-6. CS READ Timing 0 1 2 3 4 5 6 7 8 23 24 25 26 27 28 29 30 SCK BYTE ADDRESS SI INSTRUCTION AN ... A0 DATA OUT SO HIGH IMPEDANCE 7 MSB 6 5 4 3 2 1 0 11 8698B–SEEPR–3/10 Figure 4-7. CS WRITE Timing 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31 SCK BYTE ADDRESS DATA IN SI INSTRUCTION 15 14 13 ... 3 2 1 0 7 6 5 4 3 2 1 0 SO HIGH IMPEDANCE Figure 4-8. CS HOLD Timing t CD t CD SCK t HD HOLD t HD t HZ SO tLZ 12 AT25128B/256B 8698B–SEEPR–3/10 AT25128B/256B 5. Ordering Code Detail AT25128B-SSHL-B Atmel Designator Shipping Carrier Option B or blank = Bulk (tubes) T = Tape and Reel Product Family Operating Voltage L = 1.8V to 5.5V Device Density 128 = 128k 256 = 156k Package Device Grade or Wafer/Die Thickness H = Green, NiPdAu lead finish, Industrial Temperature range (-40°C to +85°C) U = Green, matte Sn lead finish, Industrial Temperature range (-40°C to +85°C) 11 = 11mil wafer thickness Device Revision Package Option SS = X= MA = C= WWU WDT JEDEC SOIC TSSOP UDFN VFBGA = Wafer unsawn = Die in Tape and Reel 13 8698B–SEEPR–3/10 6. Part Markings AT25128B-SSHL Top Mark Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 5 D B L @ |---|---|---|---|---|---|---|---| * LOT NUMBER |---|---|---|---|---|---|---|---| | PIN 1 INDICATOR (DOT) @ = Country of Y = SEAL YEAR 6: 2006 0: 7: 2007 1: 8: 2008 2: 9: 2009 3: Ass’y 2010 2011 2012 2013 WW 02 04 :: :: 50 52 = = = : : = = SEAL Week Week :::: :::: Week Week WEEK 2 4 : :: 50 52 AT25128B-XHL Top Mark PIN 1 INDICATOR (DOT) | * |---|---|---|---|---|---| A T H Y W W |---|---|---|---|---|---| 5 D B L @ |---|---|---|---|---|---|---| ATMEL L O T N U M B E R |---|---|---|---|---|---|---| @ = Country of Y = SEAL YEAR 8: 2008 2: 9: 2009 3: 0: 2010 4: 1: 2011 5: Ass’y 2012 2013 2014 2015 WW 02 04 :: :: 52 = = = : : = SEAL Week Week :::: :::: Week WEEK 2 4 : :: 52 AT25128B-MAHL Top Mark |---|---|---| 5 D B |---|---|---| H L @ |---|---|---| Y X X |---|---|---| * | PIN 1 INDICATOR (DOT) Y = YEAR OF ASSEMBLY @ = Country of Ass’y XX= ATMEL LOT NUMBER TO COORESPOND WITH TRACE CODE LOG BOOK. (e.g. XX = AA, AB, AC,... AX, AY, AZ) Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 1: 2011 8: 2008 2: 2012 9: 2009 3: 2013 14 AT25128B/256B 8698B–SEEPR–3/10 AT25128B/256B AT25128B-CUL Top Mark |---|---|---|---| 5 D B U |---|---|---|---| B Y M X X |---|---|---|---|---| *