AT25320

Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) • Low-voltage and Standard-voltage Operation • • • • • • • • – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 5.5V) 3.0 MHz Clock Rate (5V) 32-byte Page Mode Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection Self-timed Write Cycle (5 ms Typical) High-reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years Automotive Grade Devices Available 8-lead PDIP, 8-lead JEDEC SOIC and 14-lead TSSOP Packages Description The AT25080/160/320/640 provides 8192/16384/32768/65536 bits of serial electrically-e ra sa ble pro gramma ble re ad on ly memo r y ( EEPROM ) or ga nize d a s 1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25080/160/320/640 is available in space saving 8-lead PDIP, 8lead JEDEC SOIC and 14-lead TSSOP packages. The AT25080/160/320/640 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. SPI Serial EEPROMs 8K (1024 x 8) 16K (2048 x 8) 32K (4096 x 8) 64K (8192 x 8) AT25080 AT25160 AT25320 AT25640 Pin Configuration Pin Name CS SCK SI SO GND VCC WP HOLD NC DC Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input No Connect Don’t Connect CS SO NC NC NC WP GND 8-lead PDIP CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 8-lead SOIC CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 14-lead TSSOP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI 0675M–SEEPR–9/03 1 BLOCK WRITE protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Block Diagram 2 AT25080/160/320/640 0675M–SEEPR–9/03 AT25080/160/320/640 Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Symbol COUT CIN Note: Test Conditions Output Capacitance (SO) Input Capacitance(CS, SCK, SI, WP, HOLD) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V DC Characteristics(1) Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ISB1 ISB2 ISB3 IIL IOL VIL (1) (1) Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low-voltage Input High-voltage Output Low-voltage Output High-voltage Output Low-voltage Output High-voltage Test Condition Min 1.8 2.7 4.5 Typ Max 3.6 5.5 5.5 3.0 5.0 Units V V V mA mA µA µA µA µA VCC = 5.0V at 1 MHz, SO = Open, Read VCC = 5.0V at 2 MHz, SO = Open, Read, Write VCC = 1.8V, CS = VCC VCC = 2.7V, CS = VCC VCC = 5.0V, CS = VCC VIN = 0V to VCC VIN = 0V to VCC, TAC = 0°C to 70°C -3.0 -3.0 -0.6 VCC x 0.7 4.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 3.6V IOL = 3.0 mA IOH = -1.6 mA IOL = 0.15 mA IOH = -100 µA VCC - 0.2 VCC - 0.8 0.1 0.2 2.0 1.0 2.0 5.0 3.0 VCC x 0.3 VCC + 0.5 0.4 µA V V V V VIH VOL1 VOH1 VOL2 VOH2 Note: 0.2 V V 1. VIL min and VIH max are reference only and are not tested. 3 0675M–SEEPR–9/03 AC Characteristics Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter SCK Clock Frequency Voltage 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 133 200 800 133 200 800 250 250 1000 250 250 1000 250 250 1000 50 50 100 50 50 100 100 100 400 200 200 400 0 0 0 0 0 0 133 200 800 ns Min 0 0 0 Max 3.0 2.1 0.5 2 2 2 2 2 2 Units MHz fSCK tRI Input Rise Time µs tFI Input Fall Time µs tWH SCK High Time ns tWL SCK Low Time ns tCS CS High Time ns tCSS CS Setup Time ns tCSH CS Hold Time ns tSU Data In Setup Time ns tH Data In Hold Time ns tHD Hold Setup Time tCD Hold Hold Time tV Output Valid ns tHO Output Hold Time ns 4 AT25080/160/320/640 0675M–SEEPR–9/03 AT25080/160/320/640 AC Characteristics (Continued) Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Hold to Output Low Z Voltage 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 1M Min 0 0 0 Max 100 100 100 100 100 100 250 250 1000 5 10 20 Units ns tLZ tHZ Hold to Output High Z ns tDIS Output Disable Time ns tWC Endurance(1) Note: Write Cycle Time 5.0V, 25°C, Page Mode ms Write Cycles 1. This parameter is characterized and is not 100% tested. 5 0675M–SEEPR–9/03 Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080/160/320/640 always operates as a slave. TRANSMITTER/RECEIVER: The AT25080/160/320/640 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: A fter the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. I NVALID OP-CODE: I f an invalid op-code is received, no data will be shifted into the AT25080/160/320/640, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25080/160/320/640 is selected when the CS p in is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HO LD: The HOL D pin is use d in conjunctio n with th e CS pin to select th e AT25080/160/320/640. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25080/160/320/640 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”. 6 AT25080/160/320/640 0675M–SEEPR–9/03 AT25080/160/320/640 SPI Serial Interface 7 0675M–SEEPR–9/03 Functional Description The AT25080/160/320/640 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25080/160/320/640 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 1. Instruction Set for the AT25080/160/320/640 Instruction Name WREN WRDI RDSR WRSR READ WRITE Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010 Operation Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array WRITE ENABLE (WREN): The device will power-up in the write disable state when V CC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 2. Status Register Format Bit 7 WPEN Bit 6 X Bit 5 X Bit 4 X Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY Table 3. Read Status Register Bit Definition Bit Bit 0 (RDY ) Bit 1 (WEN) Bit 2 (BP0) Bit 3 (BP1) Definition Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is in progress. Bit 1= 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. See Table 4 on page 9. See Table 4 on page 9. Bits 4 - 6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 5 on page 9. Bits 0 - 7 are 1s during an internal write cycle. 8 AT25080/160/320/640 0675M–SEEPR–9/03 AT25080/160/320/640 WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25080/160/320/640 is divided into four array segments. One quarter (1/4), one half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR). Table 4. Block Write Protect Bits Status Register Bits Level 0 1(1/4) 2(1/2) 3(All) BP1 0 0 1 1 BP0 0 1 0 1 AT25080 None 0300 -03FF 0200 -03FF 0000 -03FF Array Addresses Protected AT25160 None 0600 -07FF 0400 -07FF 0000 -07FF AT25320 None 0C00 -0FFF 0800 -0FFF 0000 -0FFF AT25640 None 1800 -1FFF 1000 -1FFF 0000 -1FFF The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the blockprotected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. NOTE: W hen the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low. Table 5. W PEN Operation WPEN 0 0 1 1 X X WP X X Low Low High High WEN 0 1 0 1 0 1 Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable 9 0675M–SEEPR–9/03 READ SEQUENCE (READ): Reading the AT25080/160/320/640 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ op-code is transmitted via the SI line followed by the byte address to be read (A15 - A0, Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ cycle. WRITE SEQUENCE (WRITE): In order to program the AT25080/160/320/640, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15 - A0) and the data (D7 - D0) to be programmed (Refer to Table 6). Programming will start after the CS pin is brought high. (The LOW-to-High transition of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during the WRITE programming cycle. The AT25080/160/320/640 is capable of a 32-byte PAGE WRITE operation. After each byte of data is received, the five low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 32 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25080/160/320/640 is automatically returned to the write disable state at the completion of a WRITE cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS i s brought high. A new CS f alling edge is required to re-initiate the serial communication. Table 6. Address Key Address AN Don't Care Bits AT25080 A9 - A0 A15 - A10 AT25160 A10 - A0 A15 - A11 AT25320 A11 - A0 A15 - A 12 AT25640 A12 - A0 A15 - A13 10 AT25080/160/320/640 0675M–SEEPR–9/03 AT25080/160/320/640 Timing Diagrams Synchronous Data Timing (for Mode 0) VIH CS VIL t CSS VIH SCK VIL t SU VIH SI VIL tV VOH SO VOL HI-Z t HO t DIS HI-Z VALID IN tH t WH t WL t CSH t CS WREN Timing WRDI Timing 11 0675M–SEEPR–9/03 RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK SI INSTRUCTION SO HIGH IMPEDANCE DATA OUT 7 6 5 4 3 2 1 0 MSB WRSR Timing CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SI INSTRUCTION 7 6 5 DATA IN 4 3 2 1 0 SO HIGH IMPEDANCE READ Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31 SCK SI INSTRUCTION BYTE ADDRESS 15 14 13 ... 3 2 1 0 SO HIGH IMPEDANCE DATA OUT 76543210 MSB 12 AT25080/160/320/640 0675M–SEEPR–9/03 AT25080/160/320/640 WRITE Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31 SCK SI INSTRUCTION BYTE ADDRESS DATA IN ... 3 2 1 0 7 6 5 4 3 2 1 0 15 14 13 SO HIGH IMPEDANCE HOLD Timing CS tCD tCD SCK t HD HO LD t HZ t HD SO t LZ 13 0675M–SEEPR–9/03 AT25080 Ordering Information Ordering Code AT25080-10PI-2.7 AT25080N-10SI-2.7 AT25080T1-10TI-2.7 AT25080-10PI-1.8 AT25080N-10SI-1.8 AT25080T1-10TI-1.8 Note: Package 8P3 8S1 14A2 8P3 8S1 14A2 Operation Range Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. Package Type 8P3 8S1 14A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 -1.8 Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 5.5V) 14 AT25080/160/320/640 0675M–SEEPR–9/03 AT25080/160/320/640 AT25160 Ordering Information Ordering Code AT25160-10PI-2.7 AT25160N-10SI-2.7 AT25160T1-10TI-2.7 AT25160-10PI-1.8 AT25160N-10SI-1.8 AT25160T1-10TI-1.8 Note: Package 8P3 8S1 14A2 8P3 8S1 14A2 Operation Range Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. Package Type 8P3 8S1 14A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 -1.8 Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 5.5V) 15 0675M–SEEPR–9/03 AT25320 Ordering Information Ordering Code AT25320-10PI-2.7 AT25320N-10SI-2.7 AT25320T1-10TI-2.7 Note: Package 8P3 8S1 14A2 Operation Range Industrial (-40°C to 85°C) For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. Package Type 8P3 8S1 14A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V) 16 AT25080/160/320/640 0675M–SEEPR–9/03 AT25080/160/320/640 AT25640 Ordering Information Ordering Code AT25640-10PI-2.7 AT25640N-10SI-2.7 AT25640T1-10TI-2.7 AT25640-10PI-1.8 AT25640N-10SI-1.8 AT25640T1-10TI-1.8 Note: Package 8P3 8S1 14A2 8P3 8S1 14A2 Operation Range Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. Package Type 8P3 8S1 14A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 -1.8 Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 5.5V) 17 0675M–SEEPR–9/03 Packaging Information 8P3 – PDIP 1 E E1 N Top View c eA End View D e D1 A2 A SYMBOL COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.018 0.060 0.039 0.010 0.365 0.210 0.195 0.022 0.070 0.045 0.014 0.400 2 5 6 6 3 3 b2 b3 4 PLCS L D1 E E1 e eA L b 0.325 0.280 4 3 Side View 4 0.130 0.1 Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B R 18 AT25080/160/320/640 0675M–SEEPR–9/03 AT25080/160/320/640 8S1 – JEDEC SOIC C 1 E E1 N ∅ L Top View End View e B A SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM – – – – – – – 1.27 BSC 0.40 0˚ – – 1.27 8˚ MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE A1 A A1 b C D D E1 E Side View e L ∅ Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 10/7/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B R 19 0675M–SEEPR–9/03 14A2 – TSSOP b L L1 E1 E End View e COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D MIN 4.90 NOM 5.00 6.40 BSC 4.30 – 0.80 0.19 4.40 – 1.00 – 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 5.10 NOTE 2, 5 Top View A D E A2 E1 A A2 b e Side View L L1 Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AB-1, for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 12/28/01 REV. A R 2325 Orchard Parkway San Jose, CA 95131 TITLE 14A2,14-lead (4.4 x 5 mm Body), 0.65 Pitch, Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 14A2 20 AT25080/160/320/640 0675M–SEEPR–9/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2003 . A ll rights reserved. Atmel® a nd combinations thereof, are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. 0675M–SEEPR–9/03 xM