AT25P1024C1-10CC-2.7

Features • • • • • Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) 2.1 MHz Clock Rate 128-Byte Page Mode Only for Write Operations Low Voltage and Standard Voltage Operation – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 3.6V) Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-Timed Write Cycle (5 ms Typical) High Reliability – Endurance: 100,000 Write Cycles – Data Retention: >40 Years – ESD Protection: >3000V 20-Pin JEDEC SOIC and 8-Pin Leadless Array Package • • • • SPI Serial EEPROMs 1M (131,072 x 8) • Description The AT25P1024 provides 1,048,576 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT25P1024 is available in space saving 20-pin JEDEC SOIC and 8-pin leadless array (LAP) packages. AT25P1024 Preliminary (continued) Pin Configurations Pin Name CS SCK SI SO GND VCC WP HOLD NC Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input No Connect VCC HOLD SCK SI 8 7 6 5 CS SO NC NC NC NC NC NC WP GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC HOLD NC NC NC NC NC NC SCK SI 20-Lead SOIC 8-Pin LAP 1 2 3 4 CS SO WP GND Bottom View Rev. 1082C–08/98 1 The AT25P1024 is enabled through the Chip Select pin (CS ) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely selftimed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD p in may be used to suspend any serial communication without resetting the serial sequence. Absolute Maximum Ratings* Operating Temperature .................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .................................... -1.0V to +7.0V Maximum Operating Voltage........................................... 6.25V DC Output Current ........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Block Diagram 131,072 x 8 2 AT25P1024 AT25P1024 Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Test Conditions COUT CIN Note: Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP HOLD) , 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ISB1 ISB2 ISB3 IIL IOL VIL(1) VIH (1) Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Condition Min 1.8 2.7 4.5 Typ Max 3.6 5.5 5.5 Units V V V mA mA µA µA µA µA µA V V V V VCC = 5.0V at 1 MHz, SO = Open Read VCC = 5.0V at 2 MHz, SO = Open Write VCC = 1.8V, CS = VCC VCC = 2.7V, CS = VCC VCC = 5.0V, CS = VCC VIN = 0V to VCC VIN = 0V to VCC, TAC = 0°C to 70°C -3.0 -3.0 -0.6 VCC x 0.7 4.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 3.6V IOL = 3.0 mA IOH = -1.6 mA IOL = 0.15 mA IOH = -100 µA VCC - 0.2 VCC - 0.8 2.0 4.0 0.1 0.2 2.0 5.0 7.0 3.0 3.0 7.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 VOL1 VOH1 VOL2 VOH2 Note: 0.2 V V 1. VIL and VIH max are reference only and are not tested. 3 AC Characteristics Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol fSCK Parameter SCK Clock Frequency Voltage 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 400 800 200 400 800 250 500 1000 100 250 1000 150 250 1000 30 50 100 50 50 100 100 100 400 200 300 400 0 0 0 0 0 0 200 400 800 Min 0 0 0 Max 2.1 1.0 0.5 2 2 2 2 2 2 Units MHz tRI Input Rise Time µs tFI Input Fall Time µs tWH SCK High Time ns tWL SCK Low Time ns tCS CS High Time ns tCSS CS Setup Time ns tCSH CS Hold Time ns tSU Data In Setup Time ns tH Data In Hold Time ns tHD Hold Setup Time ns tCD Hold Hold Time ns tV Output Valid ns tHO Output Hold Time ns 4 AT25P1024 AT25P1024 AC Characteristics (Continued) Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol tLZ Parameter Hold to Output Low Z Voltage 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100K Min 0 0 0 Max 100 200 300 100 200 300 200 250 1000 5 10 10 Units ns tHZ Hold to Output High Z ns tDIS Output Disable Time ns tWC Write Cycle Time ms Endurance(1) Note: 5.0V, 25°C, Page Mode Write Cycles 1. This parameter is characterized and is not 100% tested. 5 Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25P1024 always operates as a slave. TRANSMITTER/RE CEIV ER: The AT25P 1024 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25P1024, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25P1024 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25P1024. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD p in is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP ) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP g oing low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25P1024 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”. SPI Serial Interface MASTER: MICROCONTROLLER DATA OUT (MOSI) DATA IN (MISO) SERIAL CLOCK (SPI CK) SS0 SS1 SS2 SS3 SLAVE: AT25P1024 SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS 6 AT25P1024 AT25P1024 Functional Description The AT25P1024 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25P1024 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. Table 1. Instruction Set for the AT25P1024 Instruction Name WREN WRDI RDSR WRSR READ WRITE Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010 Bit 2 (BP0) Operation Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array Bit 3 (BP1) Table 3. Read Status Register Bit Definition Bit Bit 0 (RDY) Definition Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is in progress. Bit 1= 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. See Table 4. See Table 4. Bit 1 (WEN) Bits 4-6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 5. Bits 0-7 are 1s during an internal write cycle. WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): T he Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 2. Status Register Format Bit 7 WPEN Bit 6 X Bit 5 X Bit 4 X Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25P1024 is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR). Table 4. Block Write Protect Bits Status Register Bits Level 0 1(1/4) 2(1/2) 3(All) BP1 0 0 1 1 BP0 0 1 0 1 Array Addresses Protected AT25P1024 None 01800 - 01FFFF 010000 - 01FFFF 0000 - 01FFFF The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. 7 Writes are only allowed to sections of the memory which are not block-protected. Note: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low. Table 5. WPEN Operation WPEN 0 0 1 1 X X WP X X Low Low High High WEN 0 1 0 1 0 1 Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable READ SEQUENCE (READ): Reading the AT25P1024 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ op-code is transmitted via the SI line followed by the byte address to be read (Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS l ine should be driven high after the data comes out. The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ cycle. WRITE SEQUENCE (WRITE): In order to program the AT25P1024, two separate instructions must be executed. First, the device m ust be write enabled v ia the Write Enable (WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address and the data (D7-D0) to be programmed (Refer to Table 6). Programming will start after the CS pin is brought high. (The LOW to High transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during the WRITE programming cycle. The AT25P1024 is capable of a 128-byte PAGE WRITE operation ONLY. Content of the page in the array will not be guaranteed if less than 128 bytes of data is received (byte operation is not supported). After each byte of data is received, the seven low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 128 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25P1024 is automatically returned to the write disable state at the completion of a WRITE cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 6. Address Key Address AN Don’t Care Bits AT25P1024 A16 - A0 A23 - A17 8 AT25P1024 AT25P1024 Timing Diagrams (for SPI Mode 0 (0, 0)) Synchronous Data Timing VIH CS VIL t CSS VIH SCK VIL t SU VIH SI VIL tV VOH SO VOL HI-Z t HO t DIS HI-Z VALID IN tH t WH t WL t CSH t CS WREN Timing WRDI Timing 9 RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK SI INSTRUCTION SO HIGH IMPEDANCE DATA OUT 7 6 5 4 3 2 1 0 MSB WRSR Timing READ Timing CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38 3-BYTE ADDRESS SI INSTRUCTION 23 22 21 ... 3 2 1 0 SO HIGH IMPEDANCE 7 6 5 4 3 2 1 0 10 AT25P1024 AT25P1024 WRITE Timing CS 1051 1052 1053 1054 0 SCK 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 1055 128th BYTE DATA-IN 0 1st BYTE DATA-IN 3-BYTE ADDRESS SI INSTRUCTION 23 22 21 3 2 1 0 7 6 5 4 3 2 1 SO HIGH IMPEDANCE HOLD Timing CS tCD tCD SCK tHD HOLD tHZ tHD SO tLZ 11 Ordering Information tWC (max) (ms) 5 ICC (max) (µA) 7000 7000 10 2000 2000 10 1000 1000 ISB (max) (µA) 7.0 7.0 3.0 3.0 3.0 3.0 fMAX (kHz) 2100 2100 1400 1000 500 500 Ordering Code AT25P1024C1-10CC AT25P1024W1-10SC AT25P1024C1-10CI AT25P1024W1-10SI AT25P1024C1-10CC-2.7 AT25P1024W1-10SC-2.7 AT25P1024C1-10CI-2.7 AT25P1024W1-10SI-2.7 AT25P1024C1-10CC-1.8 AT25P1024W1-10SC-1.8 AT25P1024C1-10CI-1.8 AT25P1024W1-10SI-1.8 Package 8C1 20S 8C1 20S 8C1 20S 8C1 20S 8C1 20S 8C1 20S Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Package Type 8C1 20S 8-Lead, 0.300" Wide, Leadless Array Package (LAP) 20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Options Blank -2.7 -1.8 Standard Device (4.5V to 5.5V) Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 3.6V) 12 AT25P1024 AT25P1024 Packaging Information 8C1, 8-Lead, 0.300" Wide, Leadless Array Package (LAP) Dimensions in Inches and (Millimeters) 20S, 20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters) TOP VIEW SIDE VIEW 0.020 (0.508) 0.013 (0.330) 5.15 (0.203) 4.85 (0.191) PIN 1 0.299 (7.60) 0.420 (10.7) 0.291 (7.39) 0.393 (9.98) .050 (1.27) BSC 8.15 (0.321) 7.85 (0.309) 1.30 (0.051) 1.00 (0.039) 0.42 (0.017) 0.34 (0.013) 0.513 (13.0) 0.497 (12.6) 0.105 (2.67) 0.092 (2.34) BOTTOM VIEW 8 7 1.27 (0.050) TYP 6 5 0.64 (0.025) TYP 3 4 0.035 (0.889) 0.015 (0.381) 0 REF 8 0.013 (0.330) 0.009 (0.229) 1 2 0.41 (0.016) TYP 0.012 (0.305) 0.003 (0.076) 13