Features
• Fast Read Access Time – 90 ns • Dual Voltage Range Operation
– Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Compatible with JEDEC Standard AT27C010 Low Power CMOS Operation – 20 µA Max (Less than 1 µA Typical) Standby for VCC = 3.6V – 29 mW Max Active at 5 MHz for VCC = 3.6V JEDEC Standard Packages – 32-lead PLCC – 32-lead TSOP – 32-lead VSOP High Reliability CMOS Technology – 2,000V ESD Protection – 200 mA Latchup Immunity Rapid Programming Algorithm – 100 µs/Byte (Typical) CMOS and TTL Compatible Inputs and Outputs – JEDEC Standard for LVTTL and LVBO Integrated Product Identification Code Industrial Temperature Range Green (Pb/Halide-free) Packaging Option
• •
•
•
• • • • •
1-Megabit (128K x 8) Unregulated Battery-Voltage OTP EPROM AT27BV010
1. Description
The AT27BV010 is a high-performance, low-power, low-voltage 1,048,576-bit onetime programmable read-only memory (OTP EPROM) organized as 128K by 8 bits. It requires only one supply in the range of 2.7V to 3.6V in normal read mode operation, making it ideal for fast, portable systems using either regulated or unregulated battery power. Atmel’s innovative design techniques provide fast speeds that rival 5V parts while keeping the low power consumption of a 3V supply. At VCC = 2.7V, any byte can be accessed in less than 90 ns. With a typical power draw of only 18 mW at 5 MHz and VCC = 3V, the AT27BV010 consumes less than one fifth the power of a standard 5V EPROM. Standby mode supply current is typically less than 1 µA at 3V. The AT27BV010 simplifies system design and stretches battery lifetime even further by eliminating the need for power supply regulation. The AT27BV010 is available in industry-standard JEDEC-approved one-time programmable (OTP) plastic PLCC, TSOP, and VSOP packages. All devices feature two-line control (CE, OE) to give designers the flexibility to prevent bus contention. The AT27BV010 operating with VCC at 3.0V produces TTL level outputs that are compatible with standard TTL logic devices operating at VCC = 5.0V. At VCC = 2.7V, the part is compatible with JEDEC approved low voltage battery operation (LVBO) interface specifications. The device is also capable of standard 5-volt operation making it ideally suited for dual supply range systems or card products that are pluggable in both 3-volt and 5-volt hosts.
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Atmel’s AT27BV010 has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages. The AT27BV010 programs exactly the same way as a standard 5V AT27C010 and uses the same programming equipment.
2. Pin Configurations
Pin Name A0 - A16 O0 - O7 CE OE PGM NC Function Addresses Outputs Chip Enable Output Enable Program Strobe No Connect
2.1
32-lead TSOP/VSOP (Type 1) Top View
A11 A9 A8 A13 A14 NC PGM VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE O7 O6 O5 O4 O3 GND O2 O1 O0 A0 A1 A2 A3
2.2
32-lead PLCC Top View
A12 A15 A16 VPP VCC PGM NC
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AT27BV010
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O1 O2 GND O3 O4 O5 O6
14 15 16 17 18 19 20
A7 A6 A5 A4 A3 A2 A1 A0 O0
5 6 7 8 9 10 11 12 13
4 3 2 1 32 31 30
29 28 27 26 25 24 23 22 21
A14 A13 A8 A9 A11 OE A10 CE O7
AT27BV010
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C Storage Temperature ..................................... -65°C to +125°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on A9 with Respect to Ground ......................................-2.0V to +14.0V(1) VPP Supply Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) Note: 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC which may be exceeded if certain precautions are observed (consult application notes) and which may overshoot to +7.0V for pulses of less than 20 ns. *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
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6. Operating Modes
Mode/Pin Read
(2)
CE VIL X VIH
(3)
OE VIL VIH X VIH VIL X VIL
PGM X X X VIL VIH X X
(1)
Ai Ai X X Ai Ai X A9 = VH A0 = VIH or VIL A1 - A16 = VIL
(4)
VPP X X X VPP VPP VPP X
VCC VCC VCC VCC VCC VCC VCC VCC
Outputs DOUT High Z High Z DIN DOUT High Z Identification Code
Output Disable(2) Standby(2) Rapid Program PGM Verify
(3)
VIL VIL VIH VIL
PGM Inhibit(3) Product Identification(3)(5) Notes: 1. X can be VIL or VIH.
2. Read, output disable, and standby modes require, 2.7V ≤VCC ≤3.6V, or 4.5V ≤VCC ≤5.5V. 3. Refer to Programming Characteristics. Programming modes require VCC = 6.5V. 4. VH = 12.0 ± 0.5V. 5. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
7. DC and AC Operating Conditions for Read Operation
AT27BV010-90 Industrial Operating Temperature (Case) VCC Power Supply -40°C - 85°C 2.7V to 3.6V 5V ± 10%
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AT27BV010
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AT27BV010
8. DC and Operating Characteristics for Read Operation
Symbol Parameter Condition Min Max Units VCC = 2.7V to 3.6V ILI ILO IPP1 ISB ICC VIL
(2)
Input Load Current Output Leakage Current VPP(1) Read/Standby Current
VIN = 0V to VCC VOUT = 0V to VCC VPP = VCC ISB1 (CMOS), CE = VCC ± 0.3V ISB2 (TTL), CE = 2.0 to VCC + 0.5V f = 5 MHz, IOUT = 0 mA, CE = VIL, VCC = 3.6V VCC = 3.0 to 3.6V VCC = 2.7 to 3.6V -0.6 -0.6 2.0 0.7 x VCC
±1 ±5 10 20 100 8 0.8 0.2 x VCC VCC + 0.5 VCC + 0.5 0.4 0.2 0.1 2.4 VCC - 0.2 VCC - 0.1 ±1 ±5 10 100 1 25 -0.6 2.0 0.8 VCC + 0.5 0.4 2.4
µA µA µA µA µA mA V V V V V V V V V V
VCC(1) Standby Current VCC Active Current Input Low Voltage
VIH
Input High Voltage
VCC = 3.0 to 3.6V VCC = 2.7 to 3.6V IOL = 2.0 mA
VOL
Output Low Voltage
IOL = 100 µA IOL = 20 µA IOH = -2.0 mA
VOH
Output High Voltage
IOH = -100 µA IOH = -20 µA
VCC = 4.5V to 5.5V ILI ILO IPP1 ISB ICC VIL VIH VOL VOH Notes:
(2)
Input Load Current Output Leakage Current VPP(1) Read/Standby Current
VIN = 0V to VCC VOUT = 0V to VCC VPP = VCC ISB1 (CMOS), CE = VCC ± 0.3V ISB2 (TTL), CE = 2.0 to VCC + 0.5V f = 5 MHz, IOUT = 0 mA, CE = VIL
µA µA µA µA mA mA V V V V
VCC(1) Standby Current VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
IOL = 2.1 mA IOH = -400 µA
1. VCC must be applied simultaneously with or before VPP, and removed simultaneously with or after VPP. 2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
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9. AC Characteristics for Read Operation
VCC = 2.7V to 3.6V and 4.5V to 5.5V
-90 Symbol tACC(3) tCE(2) tOE(2)(3) tDF(4)(5) tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay OE or CE High to Output Float, Whichever Occurred First Output Hold from Address, CE or OE, Whichever Occurred First 0 Condition CE = OE = VIL OE = VIL CE = VIL Min Max 90 90 50 40 Units ns ns ns ns ns
10. AC Waveforms for Read Operation(1)
Notes:
1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified. 2. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE. 3. OE may be delayed up to tACC-tOE after the address is valid without impact on tACC. 4. This parameter is only sampled and is not 100% tested. 5. Output float is defined as the point when data is no longer driven.
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AT27BV010
11. Input Test Waveform and Measurement Level
tR, tF < 20 ns (10% to 90%)
12. Output Test Load
Note: CL = 100 pF including jig capacitance.
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol CIN COUT Note: Typ 4 8 Max 8 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
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14. Programming Waveforms(1)
Notes:
1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. 3. When programming the AT27BV010, a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage transients.
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AT27BV010
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AT27BV010
15. DC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits Symbol ILI VIL VIH VOL VOH ICC2 IPP2 VID Parameter Input Load Current Input Low Level Input High Level Output Low Voltage Output High Voltage VCC Supply Current (Program and Verify) VPP Supply Current A9 Product Identification Voltage CE = PGM = VIL 11.5 IOL = 2.1 mA IOH = -400 µA 2.4 40 20 12.5 Test Conditions VIN = VIL, VIH -0.6 2.0 Min Max ±10 0.8 VCC + 1 0.4 Units µA V V V V mA mA V
16. AC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.2V
Limits Symbol tAS tCES tOES tDS tAH tDH tDFP tVPS tVCS tPW tOE tPRT Notes: Parameter Address Setup Time CE Setup Time OE Setup Time Data Setup Time Address Hold Time Data Hold Time OE High to Output Float Delay VPP Setup Time VCC Setup Time PGM Program Pulse Width Data Valid from OE VPP Pulse Rise Time During Programming 50
(3) (2)
Test Conditions(1)
Min 2
Max
Units µs µs µs µs µs µs
Input Rise and Fall Times: (10% to 90%) 20 ns Input Pulse Levels: 0.45V to 2.4V Input Timing Reference Level: 0.8V to 2.0V Output Timing Reference Level: 0.8V to 2.0V
2 2 2 0 2 0 2 2 95 105 150 130
ns µs µs µs ns ns
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven – see timing diagram. 3. Program Pulse width tolerance is 100 µsec ± 5%.
17. Atmel’s AT27BV010 Integrated Product Identification Code(1)
Pins Codes Manufacturer Device Type Note: A0 0 1 O7 0 0 O6 0 0 O5 0 0 O4 1 0 O3 1 0 O2 1 1 O1 1 0 O0 0 1 Hex Data 1E 05
1. The AT27BV010 has the same Product Identification Code as the AT27C010. Both are programming compatible.
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18. Rapid Programming Algorithm
A 100 µs PGM pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 100 µs PGM pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All bytes are read again and compared with the original data to determine if the device passes or fails.
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AT27BV010
19. Ordering Information
19.1
tACC (ns) 90
Standard Package
ICC (mA) VCC = 3.6V Active 8 Standby 0.02 Ordering Code AT27BV010-90JI AT27BV010-90TI AT27BV010-90VI Package 32J 32T 32V(1) Operation Range Industrial (-40°C to 85°C)
Note:
Not recommended for new designs. Use Green package option.
19.2
tACC (ns) 90 Note:
Green Package (Pb/Halide-free)
ICC (mA) VCC = 3.6V Active 8 Standby 0.02 Ordering Code AT27BV010-90JU AT27BV010-90TU Package 32J 32T Operation Range Industrial (-40°C to 85°C)
1. The 32-lead VSOP package is not recommended for new designs.
Package Type 32J 32T 32V 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32-lead, Plastic Thin Small Outline Package (TSOP) 33-lead, Plastic Thin Small Outline Package (VSOP)
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20. Packaging Information
20.1 32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
E2
e D1 D A A2 A1
0.51(0.020)MAX 45˚ MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
D2
MIN 3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330
NOM – – – – – – – – – – – 1.270 TYP
MAX 3.556 2.413 – 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533
NOTE
A A1 A2 D D1 D2
Note 2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum.
E E1 E2 B B1 e
Note 2
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 32J REV. B
R
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AT27BV010
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AT27BV010
20.2 32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.05 0.95 19.80 18.30 7.90 0.50 NOM – – 1.00 20.00 18.40 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 – 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 8.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 32T REV. B
R
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20.3
32V – VSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation BA. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.05 0.95 13.80 12.30 7.90 0.50 NOM – – 1.00 14.00 12.40 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 – 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 14.20 12.50 8.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline Package, Type I (VSOP) DRAWING NO. 32V REV. B
R
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Headquarters
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