AT27C2048-55JI

Features • Fast Read Access Time – 55 ns • Low Power CMOS Operation – 100 µA Maximum Standby – 35 mA Maximum Active at 5 MHz JEDEC Standard Packages – 40-lead PDIP – 44-lead PLCC – 40-lead VSOP Direct Upgrade from 512-Kbit and 1-Mbit (AT27C516 and AT27C1024) EPROMs 5V ± 10% Power Supply High Reliability CMOS Technology – 2,000V ESD Protection – 200 mA Latchup Immunity Rapid Programming Algorithm – 50 µs/Word (Typical) CMOS and TTL Compatible Inputs and Outputs Integrated Product Identification Code Industrial Temperature Range • • • • 2-Megabit (128K x 16) OTP EPROM AT27C2048 • • • • 1. Description The AT27C2048 is a low-power, high-performance 2,097,152-bit one-time programmable read-only memory (OTP EPROM) organized 128K by 16 bits. It requires a single 5V power supply in normal read mode operation. Any word can be accessed in less than 55 ns, eliminating the need for speed-reducing WAIT states. The by-16 organization makes this part ideal for high-performance 16 and 32 bit microprocessor systems. In read mode, the AT27C2048 typically consumes 15 mA. Standby mode supply current is typically less than 10 µA. The AT27C2048 is available in industry-standard JEDEC-approved one-time programmable (OTP) plastic PDIP, PLCC, and VSOP packages. The device features two-line control (CE, OE) to eliminate bus contention in high-speed systems. With high density 128K word storage capability, the AT27C2048 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. Atmel’s AT27C2048 has additional features that ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 50 µs/word. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages. 0632F–EPROM–12/07 2. Pin Configurations Pin Name A0 - A16 O0 - O15 CE OE PGM NC DC Note: Function Addresses Outputs Chip Enable Output Enable Program Strobe No Connect Don’t Connect Both GND pins must be connected. A9 A10 A11 A12 A13 A14 A15 A16 PGM VCC VPP CE O15 O14 O13 O12 O11 O10 O9 O8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 OE O0 O1 O2 O3 O4 O5 O6 O7 GND 2.2 40-lead VSOP (Type 1) Top View 2.1 40-lead PDIP Top View VPP CE O15 O14 O13 O12 O11 O10 O9 O8 GND O7 O6 O5 O4 O3 O2 O1 O0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC PGM A16 A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 2.3 44-lead PLCC Top View O13 O14 O15 CE VPP DC VCC PGM A16 A15 A14 Note: Note: PLCC package pins 1 and 23 are Don’t Connect. 2 AT27C2048 0632F–EPROM–12/07 O3 O2 O1 O0 OE DC A0 A1 A2 A3 A4 18 19 20 21 22 23 24 25 26 27 28 O12 O11 O10 O9 O8 GND NC O7 O6 O5 O4 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5 AT27C2048 3. System Considerations Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. 4. Block Diagram VCC GND VPP OE CE A0 - A17 ADDRESS INPUTS OE, CE AND PROGRAM LOGIC Y DECODER X DECODER IDENTIFICATION DATA OUTPUTS O0 - O15 OUTPUT BUFFERS Y-GATING CELL MATRIX 5. Absolute Maximum Ratings* Temperature Under Bias............................... -55° C to +125° C Storage Temperature .................................... -65° C to +150° C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on A9 with Respect to Ground ......................................-2.0V to +14.0V(1) VPP Supply Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) Note: 1. Maximum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns. *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 0632F–EPROM–12/07 6. Operating Modes Mode/Pin Read Output Disable Standby Rapid Program(2) PGM Verify PGM Inhibit Product Identification(4) Notes: 1. X can be VIL or VIH. 2. Refer to the Programming characteristics. 3. VH = 12.0 ± 0.5V. 4. Two identifier words may be selected. All Ai inputs are held low (VIL), except A9, which is set to VH, and A0, which is toggled low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word. 5. Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB. CE VIL X VIH VIL VIL VIH VIL OE VIL VIH X VIH VIL X VIL PGM X(1) X X VIL VIH X X Ai Ai X X Ai Ai X A9 = A0 = VIH or VIL A1 - A16 = VIL VH(3) VPP X(1) X X (5) Outputs DOUT High Z High Z DIN DOUT High Z Identification Code VPP VPP VPP VCC 7. DC and AC Operating Conditions for Read Operation AT27C2048 -55 Industrial Operating Temperature (Case) VCC Power Supply -40° C - 85° C 5V ± 10% -90 -40° C - 85° C 5V ± 10% 8. DC and Operating Characteristics for Read Operation Symbol ILI ILO IPP1 (2) Parameter Input Load Current Output Leakage Current VPP(1) Read/Standby Current Condition VIN = 0V to VCC VOUT = 0V to VCC VPP = VCC ISB1 (CMOS) CE = VCC ± 0.3V ISB2 (TTL) CE = 2.0 to VCC + 0.5V f = 5 MHz, IOUT = 0 mA, CE = VIL Min Max ±1 ±5 10 100 1 35 Units µA µA µA µA mA mA V V V V ISB VCC(1) Standby Current ICC VIL VIH VOL VOH Notes: VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage -0.6 2.0 IOL = 2.1 mA IOH = -400 µA 2.4 0.8 VCC + 0.5 0.4 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP. 4 AT27C2048 0632F–EPROM–12/07 AT27C2048 9. AC Characteristics for Read Operation AT27C2048 -55 Symbol tACC(3) tCE(2) tOE(2)(3) tDF(4)(5) tOH(4) Note: Parameter Address to Output Delay CE to Output Delay OE to Output Delay Condition CE = OE = VIL OE = VIL CE = VIL Min Max 55 55 20 20 7 0 Min -90 Max 90 90 35 20 Units ns ns ns ns ns OE or CE High to Output Float, Whichever Occurred First Output Hold from Address, CE or OE, Whichever Occurred First 2, 3, 4, 5. See the AC Waveforms for Read Operation diagram. 10. AC Waveforms for Read Operation(1) Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE. 3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC. 4. This parameter is only sampled and is not 100% tested. 5. Output float is defined as the point when data is no longer driven. 5 0632F–EPROM–12/07 11. Input Test Waveforms and Measurement Levels For -55 devices only: tR, tF < 5 ns (10% to 90%) For -90 devices: tR, tF < 20 ns (10% to 90%) 12. Output Test Load Note: CL = 100 pF including jig capacitance, except for the -55 devices, where CL = 30 pF. 13. Pin Capacitance Symbol CIN COUT Note: Typ 4 8 Max 10 12 Units pF pF Conditions VIN = 0V VOUT = 0V Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 6 AT27C2048 0632F–EPROM–12/07 AT27C2048 14. Programming Waveforms(1) Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. 3. When programming the AT27C2048, a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage transients. 15. DC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Limits Symbol ILI VIL VIH VOL VOH ICC2 IPP2 VID Parameter Input Load Current Input Low Level Input High Level Output Low Voltage Output High Voltage VCC Supply Current (Program and Verify) VPP Supply Current A9 Product Identification Voltage CE = VIL 11.5 IOL = 2.1 mA IOH = -400 µA 2.4 50 30 12.5 Test Conditions VIN = VIL, VIH -0.6 2.0 Min Max ±10 0.8 VCC + 0.5 0.4 Units µA V V V V mA mA V 7 0632F–EPROM–12/07 16. AC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Limits Symbol tAS tOES tDS tAH tDH tDFP tVPS tVCS tPW tOE tPRT Notes: Parameter Address Setup Time OE Setup Time Data Setup Time Address Hold Time Data Hold Time OE High to Output Float Delay VPP Setup Time VCC Setup Time PGM Program Pulse Width(3) Data Valid from OE VPP Pulse Rise Time During Programming (2) Test Conditions(1) Min 2 2 Max Units µs µs µs µs µs Input Rise and Fall Times (10% to 90%) 20 ns Input Pulse Levels 0.45V to 2.4V Input Timing Reference Level 0.8V to 2.0V Output Timing Reference Level 0.8V to 2.0V 2 0 2 0 2 2 47.5 52.5 150 50 130 ns µs µs µs ns ns 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven – see timing diagram. 3. Program Pulse width tolerance is 50 µsec ± 5%. 17. Atmel’s 27C2048 Intergrated Product Identification Code Pins Codes Manufacturer Device Type A0 0 1 O15-O8 0 0 O7 0 1 O6 0 1 O5 0 1 O4 1 1 O3 1 0 O2 1 1 O1 1 1 O0 0 1 Hex Data 001E 00F7 8 AT27C2048 0632F–EPROM–12/07 AT27C2048 18. Rapid Programming Algorithm A 50 µs CE pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 50 µs CE pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a word fails to pass verification, up to 10 successive 50 µs pulses are applied with a verification after each pulse. If the word fails to verify after 10 pulses have been applied, the part is considered failed. After the word verifies properly, the next address is selected until all have been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All words are read again and compared with the original data to determine if the device passes or fails. 9 0632F–EPROM–12/07 19. Ordering Information 19.1 tACC (ns) 55 Standard Package ICC (mA) Active 35 Standby 0.1 Ordering Code AT27C2048-55JI AT27C2048-55PI AT27C2048-55VI AT27C2048-90JI AT27C2048-90PI AT27C2048-90VI Package 44J 40P6 40V(1) 44J 40P6 40V(1) Operation Range Industrial (-40° C to 85° C) Industrial (-40° C to 85° C) 90 35 0.1 Note: Not recommended for new designs. Use Green package option. 19.2 tACC (ns) 55 90 Note: Green Package (Pb/Halide-free) ICC (mA) Active 35 35 Standby 0.1 0.1 Ordering Code AT27C2048-55JU AT27C2048-55PU AT27C2048-90JU AT27C2048-90PU Package 44J 40P6 44J 40P6 Operation Range Industrial (-40° C to 85° C) Industrial (-40° C to 85° C) 1. The 40-lead VSOP package is not recommended for new designs. Package Type 44J 40P6 40V 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 40-lead, Plastic Thin Small Outline Package (VSOP) 10 AT27C2048 0632F–EPROM–12/07 AT27C2048 20. Packaging Information 20.1 44J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) E1 B E B1 D2/E2 e D1 D A A2 A1 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 17.399 16.510 17.399 16.510 14.986 0.660 0.330 NOM – – – – – – – – – – 1.270 TYP MAX 4.572 3.048 – 17.653 16.662 17.653 16.662 16.002 0.813 0.533 Note 2 Note 2 NOTE 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 44J REV. B R 11 0632F–EPROM–12/07 20.2 40P6 – PDIP D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eB 0º ~ 15º REF SYMBOL A A1 D E E1 B COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.381 52.070 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM – – – – – – – – – – 2.540 TYP MAX 4.826 – 52.578 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 2 Note 2 NOTE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB e 09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B R 12 AT27C2048 0632F–EPROM–12/07 AT27C2048 20.3 40V – VSOP PIN 1 0º ~ 8º c Pin 1 Identifier D1 D L e b L1 E A2 A SEATING PLANE GAGE PLANE A1 SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation CA. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.05 0.95 13.80 12.30 9.90 0.50 NOM – – 1.00 14.00 12.40 10.00 0.60 0.25 BASIC 0.17 0.10 0.22 – 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 14.20 12.50 10.10 0.70 Note 2 Note 2 NOTE 10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40V, 40-lead (10 x 14 mm Package) Plastic Thin Small Outline Package, Type I (VSOP) DRAWING NO. 40V REV. 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