AT28C010-12DK-SV

Features • Fast Read Access Time – 120 ns • Automatic Page Write Operation • • • • • • • • • • • – Internal Address and Data Latches for 128 Bytes – Internal Control Timer Fast Write Cycle Time – Page Write Cycle Time – 10 ms Maximum – 1 to 128-byte Page Write Operation Low Power Dissipation – 50 mA Active Current – 10 mA CMOS Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology – Endurance: 5.104 Read Cycles – Data Retention: 10 Years Operating Range: 4.5V to 5.5V, -55 to +125°C CMOS and TTL Compatible Inputs and Outputs No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2 Tested up to a Total Dose of (according to MIL STD 883 Method 1019): – 10 kRads (Si) Read-only Mode when Biased – 30 kRads (Si) Read-only Mode when Unbiased JEDEC Approved byte-Wide Pinout 435 Mils Wide 32-Pin Flat Pack Package AT28C010-12DK Mil Space 1-megabit (128K x 8) Paged Parallel EEPROMs AT28C010-12DK Description The AT28C010-12DK is a high-performance Electrically Erasable and Programmable Read-Only Memory. Its one megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 275 mW. When the device is deselected, the CMOS standby current is less than 10 mA. The AT28C010-12DK is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel's 28C010 has additional features to ensure high quality in manufacturing. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 128 bytes of EEPROM for device identification or tracking. Rev. 4259C–AERO–05/05 1 Pin Configuration Pin Name A0 - A16 CE OE WE I/O0 - I/O7 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect FLATPACK Top View A16 A15 A12 A7 A6 NC A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC NC WE A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Block Diagram 2 AT28C010-12DK 4259C–AERO–05/05 AT28C010-12DK Device Operation • READ: The AT28C010-12DK is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the AT28C010-12DK allows 1 to 128 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127 additional bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28C010-12DK will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same. The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C010-12DK features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28C010-12DK provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. For more information see the application note: http://www.atmel.com/dyn/resources/prod_documents/DOC0544.PDF HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28C010-12DK in the following ways: (a) VDD sense – if VDD is below 3.8V (typical) the write function is inhibited; (b) VDD power-on delay – once VDD has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C010-12DK. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled • • • • • • • 3 4259C–AERO–05/05 or disabled by the user; the AT28C010-12DK is shipped from Atmel with SDP disabled. • SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after tWC the entire AT28C010-12DK will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C010-12DK. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28C010-12DK during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. DEVICE IDENTIFICATION: An extra 128 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be written to or read from in the same manner as the regular memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software code. Please see Software Chip Erase application note for details. • • • • DC and AC Operating Range AT28C010-12DK-12 Operating Temperature (Case) VDD Power Supply -55°C to +125°C 5V ± 10% 4 AT28C010-12DK 4259C–AERO–05/05 AT28C010-12DK Operating Modes Mode Read Write (1) CE VIL VIL VIH X VIH X VIL VIL VIL VIL X OE VIL VIH X X X VIL VIL VIH VIH VH VIH WE VIH VIL X VIH X X VIL VIL VIL VIL X I/O DOUT DIN High Z DOUT or High Z High Z DOUT or High Z No operation DIN DIN VIH High Z Standby Write Inhibit Write Inhibit Write Inhibit Write Inhibit Software Chip Clear Software Write Protect High Voltage Chip Clear Output Disable VIH = High Logic, “1” state, VIL = Low Logic “0” state. X = logic “don’t care” state, High Z = high impedance state. VH = Chip clear voltage, DOUT = Data out, and DIN = Data in. Notes: 1. Refer to AC Programming Waveforms 5 4259C–AERO–05/05 Electrical Characteristics Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VDD + 0.6V Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics Symbol IIL , IIH IOZL , IOZH ICC3 ICC2 ICC1 VIL VIH VOL VOH1 VOH2 Parameter Low Level Input Current Output Leakage Current VDD Standby Current CMOS VDD Standby Current TTL VDD Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS IOL = 2.1 mA IOH = -400 µA IOH = -100 µA; VDD = 4.5V 2.4 4,2 2.0 0.45 Condition VIN = 0V to VDD +1V VI/O = 0V to VDD CE = VDD - 0.3V to VDD + 1V CE = 2.0V to VDD + 1V f = 5 MHz; IOUT = 0 mA Min -10 -10 Max 10 10 10 10 50 0.8 Units µA µA mA mA mA V V V V V 6 AT28C010-12DK 4259C–AERO–05/05 AT28C010-12DK AC Read Characteristics Symbol Parameter AT28C010-12DK Min TAVQV TELQV(1) TOLQV(2) TEHQZ(3,4) TAXQX Address Access Time CE Access Time OE Access Time Chip disable to output in high Z Output Hold from OE, CE or Address, whichever occurred first 0 Max 120 120 50 50 ns ns ns ns ns Units AC Read Waveforms(1)(2)(3)(4) TELQV TOLQV T EHQZ TAXQX T AVQV Notes: 1. CE may be delayed up to TAVQV - TELQV after the address transition without impact on TAVQV. 2. OE may be delayed up to TELQV - TOLQV after the falling edge of CE without impact on TELQV or by TAVQV - TOLQV after an address change without impact in TAVQV. 3. TEHQZ is specified from OE or CE wichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 7 4259C–AERO–05/05 Input Test Waveforms and Measurement Level Output Test Load Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol CIN COUT Note: Typ 4 8 Max 10 12 Units pF pF Conditions VIN = 0V VOUT = 0V 1. This parameter is 100% characterized and is not 100% tested. AC Write Characteristics Symbol TAVEL, TAVWL, TOHWL, TOHEL, TELAX, TWLAX TWLEL, TELWL TEHWH, TWHEH TELEH, TWLWHI TDVEH, TDVWH TEHDX, TWHDX, TWHOL, TEHOL TWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 50 0 0 100 50 0 50 Max Units ns ns ns ns ns ns ns ns 8 AT28C010-12DK 4259C–AERO–05/05 AT28C010-12DK AC Write Waveforms WE Controlled TOHWL TWHOL TAVWL TWLAX TWHEH TELWL TWPH TWLWH1 TDVWH TWHDX CE Controlled TOHEL EHOL TAVEL TELAX EHWH TWLEL TWPH TELEH TDVEH TEHDX 9 4259C–AERO–05/05 Page Mode Characteristics Symbol TWHWL1 TAVWL, TOHWL TWLAX TDVWH TWHDX, TWHOL TWLWH1 TWHWL2 TWPH Parameter Write Cycle Time Address Set-up Time, OE Set up time Address Hold Time Data Set-up Time Data Hold Time, OE Hold time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 50 0 50 50 0 100 150 Min Max 10 Units ms ns ns ns ns ns µs ns Page Mode Write Waveforms (1)(2) TWLWH1 TAVWL TWLAX TWPH TWHWL2 TWHDX TDVWH TWHWL1 Notes: 1. A7 through A16 must specify the page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. 10 AT28C010-12DK 4259C–AERO–05/05 AT28C010-12DK Chip Erase Waveforms tS = 5 msec (min.) tW = tH = 10 msec (min.) VH = 12.0V ± 0.5V Software Data Figure 1. Protection Enable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(3) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. 1 to 128 bytes of data are loaded. 11 4259C–AERO–05/05 Figure 2. Protection Disable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 EXIT DATA PROTECT STATE(3) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data if loaded. 4. 1 to 128 bytes of data are loaded. 12 AT28C010-12DK 4259C–AERO–05/05 AT28C010-12DK Software Protected Program Cycle Waveform(1)(2)(3) TWLWH1 TAVWL TWLAX TWPH TWHWL2 TDVWH TWHDX Notes: TWHWL1 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16) must be the same for each high to low transition of WE (or CE). 3. OE must be high only when WE and CE are both low. 13 4259C–AERO–05/05 Data Polling Characteristics(1) Symbol TWHDX TWHOL TOLQV tWR Notes: Parameter Data Hold Time OE Hold Time OE Access Time(2) Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. 0 Min 10 10 Typ Max Units ns ns ns ns Data Polling Waveforms TWHOL TWHDX TOLQV 14 AT28C010-12DK 4259C–AERO–05/05 AT28C010-12DK Toggle Bit Characteristics(1) Symbol TWHDX TWHOL TOLQV TOEHP TWR Notes: Parameter Data Hold Time OE Hold Time OE Access Time(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. 150 0 Min 10 10 Typ Max Units ns ns ns ns ns Toggle Bit Waveforms(1)(2)(3) TWHOL TWHDX Notes: TOEHP TOLQV 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any addres location may be used but the address should not vary. 15 4259C–AERO–05/05 Ordering Information tACC (ns) Active ICC (mA) Standby AT28C010-12DK-E 120 50 10 AT28C010-12DK-MQ AT28C010-12DK-SV FP32.4 Engineering Samples Military Level B Space Level B Ordering Code Package Packing 16 AT28C010-12DK 4259C–AERO–05/05 AT28C010-12DK Packaging Information FP32.435 32F, 32-Lead, Non-Windowed, Ceramic Bottom Brazed Flat Package (Flatpack) Dimensions in Inches and Millimeters MIL-STD-1835 F-18 CONFIG B JEDEC OUTLINE MO-115 17 4259C–AERO–05/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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