AT28C040-20FISL703

Features • Read Access Time – 200 ns • Automatic Page Write Operation – Internal Address and Data Latches for 256 Bytes – Internal Control Timer Fast Write Cycle Time – Page Write Cycle Time – 10 ms Maximum – 1 to 256 Byte Page Write Operation Low Power Dissipation – 50 mA Active Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology – Endurance: 10,000 Cycles – Data Retention: 10 Years Single 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout • • • • • • • • 4-Megabit (512K x 8) Paged Parallel EEPROMs AT28C040 1. Description The AT28C040 is a high-performance electrically erasable and programmable readonly memory (EEPROM). Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 440 mW. The AT28C040 is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 256-byte page register to allow writing of up to 256 bytes simultaneously. During a write cycle, the address and 1 to 256 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by Data Polling of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. Atmel's AT28C040 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 256 bytes of EEPROM for device identification or tracking. 0542E–PEEPR–1/08 2. Pin Configurations Pin Name A0 - A18 CE OE WE I/O0 - I/O7 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect 2.2 48-lead TSOP – Top View NC NC NC NC A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 NC NC NC NC 2.1 44-lead LCC – Top View A15 A16 A18 NC NC NC VCC WE NC A17 A14 2.3 32-lead Flatpack – Top View A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 2 AT28C040 0542E–PEEPR–1/08 A0 I/O0 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 I/O6 I/O7 18 19 20 21 22 23 24 25 26 27 28 A12 A7 A6 A5 NC NC NC A4 A3 A2 A1 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 A13 A8 A9 A11 NC NC NC NC OE A10 CE AT28C040 3. Block Diagram 4. Absolute Maximum Ratings* Temperature Under Bias............................... -55° C to +125° C Storage Temperature .................................... -65° C to +150° C All Input Voltages (including NC pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 0542E–PEEPR–1/08 5. Device Operation 5.1 Read The AT28C040 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their systems. 5.2 Byte Write A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. 5.3 Page Write The page write operation of the AT28C040 allows 1 to 256 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 255 additional bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded, the AT28C040 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A8 - A18 inputs. For each WE high to low transition during the page write operation, A8 - A18 must be the same. The A0 to A7 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. 5.4 Data Polling The AT28C040 features Data Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. Data Polling may begin at anytime during the write cycle. 5.5 Toggle Bit In addition to Data Polling, the AT28C040 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. 5.6 Data Protection If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel® has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4 AT28C040 0542E–PEEPR–1/08 AT28C040 5.6.1 Hardware Protection Hardware features protect against inadvertent writes to the AT28C040 in the following ways: (a) VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay – once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. Software Data Protection A software controlled data protection feature has been implemented on the AT28C040. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C040 is shipped from Atmel with SDP disabled. SDP is enabled when the host system issues a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after tWC, the entire AT28C040 will be protected against inadvertent write operations. It should be noted that once protected, the host can still perform a byte or page write to the AT28C040. To do so, the same 3-byte command sequence used to enable SDP must precede the data to be written. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP, and SDP will protect the AT28C040 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device, and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. 5.6.2 5.7 Device Identification An extra 256 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FF80H to 7FFFFH, the bytes may be written to or read from in the same manner as the regular memory array. 5.8 Optional Chip Erase Mode The entire device can be erased using a 6-byte software erase code. Please see Software Chip Erase application note for details. 5 0542E–PEEPR–1/08 6. DC and AC Operating Range AT28C040-20 Operation Read Industrial Operating Temperature (Case) Extended VCC Power Supply -55°C - 125°C 5V ± 10% -40°C - 85°C 5V ± 10% -40°C - 85°C Program -40°C - 85°C 7. Operating Modes Mode Read Write(2) Write Inhibit Write Inhibit Output Disable Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. CE VIL VIL X X X OE VIL VIH X VIL VIH WE VIH VIL VIH X X High Z I/O DOUT DIN 8. DC Characteristics Symbol ILI ILO ICC VIL VIH VOL VOH1 VOH2 Parameter Input Load Current Output Leakage Current VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS IOL = 2.1 mA IOH = -400 µA IOH = -100 µA; VCC = 4.5V 2.4 4.2 2.0 0.45 Condition VIN = 0V to VCC + 1V VI/O = 0V to VCC f = 5 MHz; IOUT = 0 mA Min Max 10 10 50 0.8 Units µA µA mA V V V V V 6 AT28C040 0542E–PEEPR–1/08 AT28C040 9. AC Read Characteristics AT28C040-20 Symbol tACC tCE(1) tOE(2) tDF(3)(4) tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first 0 0 0 Min Max 200 200 55 55 Units ns ns ns ns ns 10. AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE May be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 11. Input Test Waveforms and Measurement Level tR, tF < 5 ns 12. Output Test Load 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol CIN COUT Note: Typ 4 8 Max 10 12 Units pF pF Conditions VIN = 0V VOUT = 0V 1. This parameter is characterized and is not 100% tested. 7 0542E–PEEPR–1/08 14. AC Write Characteristics Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Min 0 50 0 0 100 50 0 Max Units ns ns ns ns ns ns ns 15. AC Write Waveforms 15.1 WE Controlled 15.2 CE Controlled 8 AT28C040 0542E–PEEPR–1/08 AT28C040 16. Page Mode Characteristics Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 50 0 50 50 0 100 150 Min Max 10 Units ms ns ns ns ns ns µs ns 17. Page Mode Write Waveforms(1)(2) Notes: 1. A8 through A18 must specify the page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. 9 0542E–PEEPR–1/08 18. Software Data Protection Enable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 19. Software Data Protection Disable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA 80 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD DATA AA TO ADDRESS 5555 LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE LOAD DATA 55 TO ADDRESS 2AAA Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 256 bytes of data are loaded. LOAD DATA 20 TO ADDRESS 5555 EXIT DATA PROTECT STATE(3) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS 20. Software Protected Program Cycle Waveform(1)(2)(3) Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A8 - A18) must be the same for each high to low transition of WE (or CE). 3. OE must be high only when WE and CE are both low. 10 AT28C040 0542E–PEEPR–1/08 AT28C040 21. Data Polling Characteristics(1) Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay (2) Min 10 10 Typ Max Units ns ns ns Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. 0 ns 22. Data Polling Waveforms 23. Toggle Bit Characteristics(1) Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. 150 0 Min 10 10 Typ Max Units ns ns ns ns ns 24. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 11 0542E–PEEPR–1/08 25. Ordering Information 25.1 tACC (ns) Standard Packaging ICC (mA) Active 50 Ordering Code AT28C040-20TI AT28C040-20FI AT28C040-20LI AT28C040-20FI SL703 AT28C040-20LI SL703 Package 48T 32F 44L 32F 44L Operation Range Industrial (-40° to 85° C) Extended (See DC and AC Operating Range Table) 200 50 Note: 1. See Valid Part Numbers. 26. Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers AT28C040 Speed 20 Package and Temperature Combinations FI, LI, TI, FI SL703, LI SL703 Package Type 48T 32F 44L 48-Lead, Plastic Thin Small Outline Package (TSOP) 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms 12 AT28C040 0542E–PEEPR–1/08 AT28C040 27. Packaging Information 27.1 48T – TSOP PIN 1 0º ~ 8º c Pin 1 Identifier D1 D L e b L1 E A2 A SEATING PLANE GAGE PLANE A1 SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.05 0.95 19.80 18.30 11.90 0.50 NOM – – 1.00 20.00 18.40 12.00 0.60 0.25 BASIC 0.17 0.10 0.22 – 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 12.10 0.70 Note 2 Note 2 NOTE 10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 48T REV. B R 13 0542E–PEEPR–1/08 27.2 32F – Flatpack Dimensions in Millimeters and (Inches). Controlling dimension: Inches. JEDEC Outline MO-115 AA PIN #1 ID 9.40(0.370) 6.86(0.270) 0.51(0.020) 0.38(0.015) 21.08(0.830) 20.60(0.811) 1.27(0.050) BSC 12.40(0.488) 11.99(0.472) 1.14(0.045) MAX 0.18(0.007) 0.10(0.004) 10.36(0.408) 9.02(0.355) 1.83(0.072) 0.76(0.030) 3.05(0.120) 2.49(0.098) 1.14(0.045) 0.66(0.026) 10/21/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 32F, 32-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (FlatPack) DRAWING NO. 32F REV. B R 14 AT28C040 0542E–PEEPR–1/08 AT28C040 27.3 44L – LCC Dimensions in Millimeters and (Inches) Controlling dimension: Inches MIL-STD-1835 C-5 16.81(0.662) 16.26(0.640) 2.74(0.108) 2.16(0.085) 16.81(0.662) 16.26(0.640) PIN 1 1.40(0.055) 1.14(0.045) 2.03(0.080) 1.40(0.055) 2.41(0.095) 1.91(0.075) INDEX CORNER 0.635(0.025) X 45˚ 0.381(0.015) 0.305(0.012) RADIUS 0.178(0.007) 12.70(0.500) BSC 0.737(0.029) 0.533(0.021) 1.27(0.050) TYP 1.02(0.040) X 45˚ 2.16(0.085) 1.65(0.065) 12.70(0.500) BSC 04/11/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44L, 44-pad (0.600" Wide), Non-windowed, Ceramic Lid, Leadless Chip Carrier (LCC) DRAWING NO. 44L REV. A R 15 0542E–PEEPR–1/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support p_eeprom@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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